perf/x86/intel: Use Intel family macros for core perf events
Use the new model number macros instead of spelling things out in the comments. Note that this is missing a Nehalem model that is mentioned in intel_idle which is fixed up in a later patch. The resulting binary (arch/x86/events/intel/core.o) is exactly the same with and without this patch modulo some harmless changes to restoring %esi in the return path of functions, even those untouched by this patch. Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave@sr71.net> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Kan Liang <kan.liang@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: jacob.jun.pan@intel.com Link: http://lkml.kernel.org/r/20160603001929.C5F1C079@viggo.jf.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Dave Hansen
Ingo Molnar
parent
020d704c3e
commit
ef5f9f47d4
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@ -16,6 +16,7 @@
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#include <asm/cpufeature.h>
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#include <asm/hardirq.h>
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#include <asm/intel-family.h>
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#include <asm/apic.h>
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#include "../perf_event.h"
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@ -3319,11 +3320,11 @@ static int intel_snb_pebs_broken(int cpu)
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u32 rev = UINT_MAX; /* default to broken for unknown models */
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switch (cpu_data(cpu).x86_model) {
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case 42: /* SNB */
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case INTEL_FAM6_SANDYBRIDGE:
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rev = 0x28;
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break;
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case 45: /* SNB-EP */
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case INTEL_FAM6_SANDYBRIDGE_X:
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switch (cpu_data(cpu).x86_mask) {
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case 6: rev = 0x618; break;
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case 7: rev = 0x70c; break;
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@ -3573,15 +3574,15 @@ __init int intel_pmu_init(void)
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* Install the hw-cache-events table:
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*/
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switch (boot_cpu_data.x86_model) {
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case 14: /* 65nm Core "Yonah" */
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case INTEL_FAM6_CORE_YONAH:
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pr_cont("Core events, ");
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break;
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case 15: /* 65nm Core2 "Merom" */
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case INTEL_FAM6_CORE2_MEROM:
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x86_add_quirk(intel_clovertown_quirk);
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case 22: /* 65nm Core2 "Merom-L" */
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case 23: /* 45nm Core2 "Penryn" */
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case 29: /* 45nm Core2 "Dunnington (MP) */
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case INTEL_FAM6_CORE2_MEROM_L:
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case INTEL_FAM6_CORE2_PENRYN:
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case INTEL_FAM6_CORE2_DUNNINGTON:
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memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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@ -3592,9 +3593,9 @@ __init int intel_pmu_init(void)
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pr_cont("Core2 events, ");
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break;
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case 30: /* 45nm Nehalem */
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case 26: /* 45nm Nehalem-EP */
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case 46: /* 45nm Nehalem-EX */
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case INTEL_FAM6_NEHALEM:
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case INTEL_FAM6_NEHALEM_EP:
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case INTEL_FAM6_NEHALEM_EX:
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memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
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@ -3622,11 +3623,11 @@ __init int intel_pmu_init(void)
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pr_cont("Nehalem events, ");
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break;
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case 28: /* 45nm Atom "Pineview" */
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case 38: /* 45nm Atom "Lincroft" */
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case 39: /* 32nm Atom "Penwell" */
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case 53: /* 32nm Atom "Cloverview" */
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case 54: /* 32nm Atom "Cedarview" */
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case INTEL_FAM6_ATOM_PINEVIEW:
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case INTEL_FAM6_ATOM_LINCROFT:
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case INTEL_FAM6_ATOM_PENWELL:
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case INTEL_FAM6_ATOM_CLOVERVIEW:
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case INTEL_FAM6_ATOM_CEDARVIEW:
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memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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@ -3638,9 +3639,9 @@ __init int intel_pmu_init(void)
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pr_cont("Atom events, ");
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break;
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case 55: /* 22nm Atom "Silvermont" */
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case 76: /* 14nm Atom "Airmont" */
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case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
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case INTEL_FAM6_ATOM_SILVERMONT1:
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case INTEL_FAM6_ATOM_SILVERMONT2:
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case INTEL_FAM6_ATOM_AIRMONT:
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memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
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@ -3656,8 +3657,8 @@ __init int intel_pmu_init(void)
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pr_cont("Silvermont events, ");
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break;
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case 92: /* 14nm Atom "Goldmont" */
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case 95: /* 14nm Atom "Goldmont Denverton" */
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case INTEL_FAM6_ATOM_GOLDMONT:
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case INTEL_FAM6_ATOM_DENVERTON:
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memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
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@ -3680,9 +3681,9 @@ __init int intel_pmu_init(void)
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pr_cont("Goldmont events, ");
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break;
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case 37: /* 32nm Westmere */
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case 44: /* 32nm Westmere-EP */
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case 47: /* 32nm Westmere-EX */
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case INTEL_FAM6_WESTMERE:
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case INTEL_FAM6_WESTMERE_EP:
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case INTEL_FAM6_WESTMERE_EX:
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memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
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@ -3709,8 +3710,8 @@ __init int intel_pmu_init(void)
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pr_cont("Westmere events, ");
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break;
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case 42: /* 32nm SandyBridge */
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case 45: /* 32nm SandyBridge-E/EN/EP */
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case INTEL_FAM6_SANDYBRIDGE:
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case INTEL_FAM6_SANDYBRIDGE_X:
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x86_add_quirk(intel_sandybridge_quirk);
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x86_add_quirk(intel_ht_bug);
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memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
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@ -3723,7 +3724,7 @@ __init int intel_pmu_init(void)
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x86_pmu.event_constraints = intel_snb_event_constraints;
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x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
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x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
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if (boot_cpu_data.x86_model == 45)
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if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
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x86_pmu.extra_regs = intel_snbep_extra_regs;
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else
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x86_pmu.extra_regs = intel_snb_extra_regs;
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@ -3745,8 +3746,8 @@ __init int intel_pmu_init(void)
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pr_cont("SandyBridge events, ");
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break;
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case 58: /* 22nm IvyBridge */
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case 62: /* 22nm IvyBridge-EP/EX */
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case INTEL_FAM6_IVYBRIDGE:
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case INTEL_FAM6_IVYBRIDGE_X:
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x86_add_quirk(intel_ht_bug);
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memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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@ -3762,7 +3763,7 @@ __init int intel_pmu_init(void)
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x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
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x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
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x86_pmu.pebs_prec_dist = true;
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if (boot_cpu_data.x86_model == 62)
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if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
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x86_pmu.extra_regs = intel_snbep_extra_regs;
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else
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x86_pmu.extra_regs = intel_snb_extra_regs;
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@ -3780,10 +3781,10 @@ __init int intel_pmu_init(void)
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break;
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case 60: /* 22nm Haswell Core */
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case 63: /* 22nm Haswell Server */
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case 69: /* 22nm Haswell ULT */
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case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
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case INTEL_FAM6_HASWELL_CORE:
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case INTEL_FAM6_HASWELL_X:
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case INTEL_FAM6_HASWELL_ULT:
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case INTEL_FAM6_HASWELL_GT3E:
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x86_add_quirk(intel_ht_bug);
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x86_pmu.late_ack = true;
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memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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@ -3807,10 +3808,10 @@ __init int intel_pmu_init(void)
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pr_cont("Haswell events, ");
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break;
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case 61: /* 14nm Broadwell Core-M */
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case 86: /* 14nm Broadwell Xeon D */
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case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
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case 79: /* 14nm Broadwell Server */
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case INTEL_FAM6_BROADWELL_CORE:
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case INTEL_FAM6_BROADWELL_XEON_D:
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case INTEL_FAM6_BROADWELL_GT3E:
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case INTEL_FAM6_BROADWELL_X:
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x86_pmu.late_ack = true;
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memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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@ -3843,7 +3844,7 @@ __init int intel_pmu_init(void)
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pr_cont("Broadwell events, ");
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break;
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case 87: /* Knights Landing Xeon Phi */
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case INTEL_FAM6_XEON_PHI_KNL:
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memcpy(hw_cache_event_ids,
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slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs,
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@ -3861,11 +3862,11 @@ __init int intel_pmu_init(void)
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pr_cont("Knights Landing events, ");
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break;
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case 142: /* 14nm Kabylake Mobile */
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case 158: /* 14nm Kabylake Desktop */
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case 78: /* 14nm Skylake Mobile */
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case 94: /* 14nm Skylake Desktop */
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case 85: /* 14nm Skylake Server */
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case INTEL_FAM6_SKYLAKE_MOBILE:
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case INTEL_FAM6_SKYLAKE_DESKTOP:
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case INTEL_FAM6_SKYLAKE_X:
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case INTEL_FAM6_KABYLAKE_MOBILE:
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case INTEL_FAM6_KABYLAKE_DESKTOP:
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x86_pmu.late_ack = true;
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memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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