ARC: Disable caches in early boot if so configured
Requested-by: Noam Camus <noamc@ezchip.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
e87a850b9c
commit
ef680cdc24
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@ -55,4 +55,31 @@ extern void read_decode_cache_bcr(void);
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#endif /* !__ASSEMBLY__ */
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/* Instruction cache related Auxiliary registers */
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#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
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#define ARC_REG_IC_IVIC 0x10
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#define ARC_REG_IC_CTRL 0x11
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#define ARC_REG_IC_IVIL 0x19
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#if defined(CONFIG_ARC_MMU_V3) || defined (CONFIG_ARC_MMU_V4)
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#define ARC_REG_IC_PTAG 0x1E
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#endif
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/* Bit val in IC_CTRL */
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#define IC_CTRL_CACHE_DISABLE 0x1
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/* Data cache related Auxiliary registers */
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#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
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#define ARC_REG_DC_IVDC 0x47
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#define ARC_REG_DC_CTRL 0x48
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#define ARC_REG_DC_IVDL 0x4A
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#define ARC_REG_DC_FLSH 0x4B
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#define ARC_REG_DC_FLDL 0x4C
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#if defined(CONFIG_ARC_MMU_V3) || defined (CONFIG_ARC_MMU_V4)
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#define ARC_REG_DC_PTAG 0x5C
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#endif
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/* Bit val in DC_CTRL */
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#define DC_CTRL_INV_MODE_FLUSH 0x40
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#define DC_CTRL_FLUSH_STATUS 0x100
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#endif /* _ASM_CACHE_H */
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@ -12,10 +12,42 @@
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* to skip certain things during boot on simulator
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/entry.h>
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#include <linux/linkage.h>
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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.macro CPU_EARLY_SETUP
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; Setting up Vectror Table (in case exception happens in early boot
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sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
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; Disable I-cache/D-cache if kernel so configured
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lr r5, [ARC_REG_IC_BCR]
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breq r5, 0, 1f ; I$ doesn't exist
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lr r5, [ARC_REG_IC_CTRL]
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#ifdef CONFIG_ARC_HAS_ICACHE
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bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
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#else
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bset r5, r5, 0 ; I$ exists, but is not used
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#endif
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sr r5, [ARC_REG_IC_CTRL]
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1:
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lr r5, [ARC_REG_DC_BCR]
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breq r5, 0, 1f ; D$ doesn't exist
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lr r5, [ARC_REG_DC_CTRL]
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bclr r5, r5, 6 ; Invalidate (discard w/o wback)
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#ifdef CONFIG_ARC_HAS_DCACHE
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bclr r5, r5, 0 ; Enable (+Inv)
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#else
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bset r5, r5, 0 ; Disable (+Inv)
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#endif
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sr r5, [ARC_REG_DC_CTRL]
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1:
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.endm
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.cpu A7
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@ -27,7 +59,7 @@ stext:
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; Don't clobber r0-r2 yet. It might have bootloader provided info
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;-------------------------------------------------------------------
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sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
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CPU_EARLY_SETUP
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#ifdef CONFIG_SMP
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; Ensure Boot (Master) proceeds. Others wait in platform dependent way
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@ -90,7 +122,7 @@ stext:
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first_lines_of_secondary:
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sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
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CPU_EARLY_SETUP
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; setup per-cpu idle task as "current" on this CPU
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ld r0, [@secondary_idle_tsk]
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@ -73,33 +73,6 @@
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#include <asm/cachectl.h>
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#include <asm/setup.h>
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/* Instruction cache related Auxiliary registers */
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#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
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#define ARC_REG_IC_IVIC 0x10
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#define ARC_REG_IC_CTRL 0x11
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#define ARC_REG_IC_IVIL 0x19
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#if (CONFIG_ARC_MMU_VER > 2)
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#define ARC_REG_IC_PTAG 0x1E
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#endif
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/* Bit val in IC_CTRL */
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#define IC_CTRL_CACHE_DISABLE 0x1
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/* Data cache related Auxiliary registers */
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#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
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#define ARC_REG_DC_IVDC 0x47
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#define ARC_REG_DC_CTRL 0x48
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#define ARC_REG_DC_IVDL 0x4A
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#define ARC_REG_DC_FLSH 0x4B
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#define ARC_REG_DC_FLDL 0x4C
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#if (CONFIG_ARC_MMU_VER > 2)
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#define ARC_REG_DC_PTAG 0x5C
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#endif
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/* Bit val in DC_CTRL */
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#define DC_CTRL_INV_MODE_FLUSH 0x40
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#define DC_CTRL_FLUSH_STATUS 0x100
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char *arc_cache_mumbojumbo(int c, char *buf, int len)
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{
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int n = 0;
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@ -168,72 +141,43 @@ void read_decode_cache_bcr(void)
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*/
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void arc_cache_init(void)
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{
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unsigned int cpu = smp_processor_id();
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struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
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struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
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unsigned int dcache_does_alias, temp;
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unsigned int __maybe_unused cpu = smp_processor_id();
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struct cpuinfo_arc_cache __maybe_unused *ic, __maybe_unused *dc;
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char str[256];
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printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
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if (!ic->ver)
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goto chk_dc;
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#ifdef CONFIG_ARC_HAS_ICACHE
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/* 1. Confirm some of I-cache params which Linux assumes */
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if (ic->line_len != L1_CACHE_BYTES)
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panic("Cache H/W doesn't match kernel Config");
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ic = &cpuinfo_arc700[cpu].icache;
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if (ic->ver) {
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if (ic->line_len != L1_CACHE_BYTES)
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panic("ICache line [%d] != kernel Config [%d]",
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ic->line_len, L1_CACHE_BYTES);
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if (ic->ver != CONFIG_ARC_MMU_VER)
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panic("Cache ver doesn't match MMU ver\n");
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if (ic->ver != CONFIG_ARC_MMU_VER)
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panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
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ic->ver, CONFIG_ARC_MMU_VER);
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}
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#endif
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/* Enable/disable I-Cache */
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temp = read_aux_reg(ARC_REG_IC_CTRL);
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#ifdef CONFIG_ARC_HAS_ICACHE
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temp &= ~IC_CTRL_CACHE_DISABLE;
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#else
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temp |= IC_CTRL_CACHE_DISABLE;
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#endif
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write_aux_reg(ARC_REG_IC_CTRL, temp);
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chk_dc:
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if (!dc->ver)
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return;
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#ifdef CONFIG_ARC_HAS_DCACHE
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if (dc->line_len != L1_CACHE_BYTES)
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panic("Cache H/W doesn't match kernel Config");
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dc = &cpuinfo_arc700[cpu].dcache;
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if (dc->ver) {
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unsigned int dcache_does_alias;
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/* check for D-Cache aliasing */
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dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
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if (dc->line_len != L1_CACHE_BYTES)
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panic("DCache line [%d] != kernel Config [%d]",
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dc->line_len, L1_CACHE_BYTES);
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if (dcache_does_alias && !cache_is_vipt_aliasing())
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panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
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else if (!dcache_does_alias && cache_is_vipt_aliasing())
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panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
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/* check for D-Cache aliasing */
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dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
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if (dcache_does_alias && !cache_is_vipt_aliasing())
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panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
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else if (!dcache_does_alias && cache_is_vipt_aliasing())
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panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
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}
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#endif
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/* Set the default Invalidate Mode to "simpy discard dirty lines"
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* as this is more frequent then flush before invalidate
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* Ofcourse we toggle this default behviour when desired
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*/
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temp = read_aux_reg(ARC_REG_DC_CTRL);
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temp &= ~DC_CTRL_INV_MODE_FLUSH;
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#ifdef CONFIG_ARC_HAS_DCACHE
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/* Enable D-Cache: Clear Bit 0 */
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write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE);
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#else
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/* Flush D cache */
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write_aux_reg(ARC_REG_DC_FLSH, 0x1);
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/* Disable D cache */
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write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE);
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#endif
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return;
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}
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#define OP_INV 0x1
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