davinci: add power management support
This patch adds core power management (suspend-to-RAM) support for DaVinci SoCs. The code depends on the the "deepsleep" feature to suspend the SoC and saves power by gating the input clock. The wakeup can be based on an external event as supported by the SoC. Assembly code (in sleep.S) is added to aid gating DDR2 clocks. Code doing this work should not be accessing DDR2. The assembly code is relocated to SRAM by the code in pm.c The support has been validated on DA850/OMAP-L138 only though the code is (hopefully) generic enough that other SoCs supporting deepsleep feature simply requires SoC specific code to start using this driver. Note that all the device drivers don't support suspend/resume still and are being worked on. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Sekhar Nori
Kevin Hilman
parent
7307d093e6
commit
efc1bb8a6f
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@ -34,3 +34,4 @@ obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
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# Power Management
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obj-$(CONFIG_CPU_FREQ) += cpufreq.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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obj-$(CONFIG_SUSPEND) += pm.o sleep.o
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@ -33,6 +33,7 @@
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#define DDR2_SDRCR_OFFSET 0xc
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#define DDR2_SRPD_BIT BIT(23)
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#define DDR2_MCLKSTOPEN_BIT BIT(30)
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#define DDR2_LPMODEN_BIT BIT(31)
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/*
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@ -0,0 +1,54 @@
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/*
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* TI DaVinci platform support for power management.
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*
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* Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MACH_DAVINCI_PM_H
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#define _MACH_DAVINCI_PM_H
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/*
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* Caution: Assembly code in sleep.S makes assumtion on the order
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* of the members of this structure.
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*/
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struct davinci_pm_config {
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void __iomem *ddr2_ctlr_base;
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void __iomem *ddrpsc_reg_base;
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int ddrpsc_num;
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void __iomem *ddrpll_reg_base;
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void __iomem *deepsleep_reg;
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void __iomem *cpupll_reg_base;
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/*
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* Note on SLEEPCOUNT:
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* The SLEEPCOUNT feature is mainly intended for cases in which
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* the internal oscillator is used. The internal oscillator is
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* fully disabled in deep sleep mode. When you exist deep sleep
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* mode, the oscillator will be turned on and will generate very
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* small oscillations which will not be detected by the deep sleep
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* counter. Eventually those oscillations will grow to an amplitude
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* large enough to start incrementing the deep sleep counter.
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* In this case recommendation from hardware engineers is that the
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* SLEEPCOUNT be set to 4096. This means that 4096 valid clock cycles
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* must be detected before the clock is passed to the rest of the
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* system.
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* In the case that the internal oscillator is not used and the
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* clock is generated externally, the SLEEPCOUNT value can be very
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* small since the clock input is assumed to be stable before SoC
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* is taken out of deepsleep mode. A value of 128 would be more than
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* adequate.
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*/
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int sleepcount;
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};
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extern unsigned int davinci_cpu_suspend_sz;
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extern void davinci_cpu_suspend(struct davinci_pm_config *);
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#endif
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@ -0,0 +1,158 @@
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/*
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* DaVinci Power Management Routines
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*
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* Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <asm/cacheflush.h>
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#include <asm/delay.h>
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#include <mach/da8xx.h>
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#include <mach/sram.h>
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#include <mach/pm.h>
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#include "clock.h"
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#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
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static void (*davinci_sram_suspend) (struct davinci_pm_config *);
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static struct davinci_pm_config *pdata;
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static void davinci_sram_push(void *dest, void *src, unsigned int size)
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{
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memcpy(dest, src, size);
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flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
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}
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static void davinci_pm_suspend(void)
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{
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unsigned val;
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if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
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/* Switch CPU PLL to bypass mode */
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val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
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val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
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__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
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udelay(PLL_BYPASS_TIME);
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/* Powerdown CPU PLL */
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val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
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val |= PLLCTL_PLLPWRDN;
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__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
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}
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/* Configure sleep count in deep sleep register */
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val = __raw_readl(pdata->deepsleep_reg);
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val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
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val |= pdata->sleepcount;
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__raw_writel(val, pdata->deepsleep_reg);
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/* System goes to sleep in this call */
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davinci_sram_suspend(pdata);
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if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
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/* put CPU PLL in reset */
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val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
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val &= ~PLLCTL_PLLRST;
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__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
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/* put CPU PLL in power down */
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val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
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val &= ~PLLCTL_PLLPWRDN;
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__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
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/* wait for CPU PLL reset */
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udelay(PLL_RESET_TIME);
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/* bring CPU PLL out of reset */
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val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
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val |= PLLCTL_PLLRST;
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__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
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/* Wait for CPU PLL to lock */
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udelay(PLL_LOCK_TIME);
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/* Remove CPU PLL from bypass mode */
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val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
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val &= ~PLLCTL_PLLENSRC;
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val |= PLLCTL_PLLEN;
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__raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
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}
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}
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static int davinci_pm_enter(suspend_state_t state)
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{
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int ret = 0;
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switch (state) {
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case PM_SUSPEND_STANDBY:
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case PM_SUSPEND_MEM:
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davinci_pm_suspend();
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static struct platform_suspend_ops davinci_pm_ops = {
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.enter = davinci_pm_enter,
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.valid = suspend_valid_only_mem,
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};
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static int __init davinci_pm_probe(struct platform_device *pdev)
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{
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pdata = pdev->dev.platform_data;
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if (!pdata) {
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dev_err(&pdev->dev, "cannot get platform data\n");
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return -ENOENT;
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}
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davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
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if (!davinci_sram_suspend) {
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dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
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return -ENOMEM;
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}
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davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
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davinci_cpu_suspend_sz);
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suspend_set_ops(&davinci_pm_ops);
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return 0;
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}
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static int __exit davinci_pm_remove(struct platform_device *pdev)
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{
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sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
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return 0;
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}
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static struct platform_driver davinci_pm_driver = {
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.driver = {
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.name = "pm-davinci",
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.owner = THIS_MODULE,
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},
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.remove = __exit_p(davinci_pm_remove),
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};
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static int __init davinci_pm_init(void)
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{
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return platform_driver_probe(&davinci_pm_driver, davinci_pm_probe);
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}
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late_initcall(davinci_pm_init);
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@ -0,0 +1,224 @@
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/*
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* (C) Copyright 2009, Texas Instruments, Inc. http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* replicated define because linux/bitops.h cannot be included in assembly */
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#define BIT(nr) (1 << (nr))
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/psc.h>
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#include <mach/memory.h>
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#include "clock.h"
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/* Arbitrary, hardware currently does not update PHYRDY correctly */
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#define PHYRDY_CYCLES 0x1000
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/* Assume 25 MHz speed for the cycle conversions since PLLs are bypassed */
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#define PLL_BYPASS_CYCLES (PLL_BYPASS_TIME * 25)
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#define PLL_RESET_CYCLES (PLL_RESET_TIME * 25)
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#define PLL_LOCK_CYCLES (PLL_LOCK_TIME * 25)
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#define DEEPSLEEP_SLEEPENABLE_BIT BIT(31)
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.text
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/*
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* Move DaVinci into deep sleep state
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*
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* Note: This code is copied to internal SRAM by PM code. When the DaVinci
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* wakes up it continues execution at the point it went to sleep.
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* Register Usage:
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* r0: contains virtual base for DDR2 controller
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* r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
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* r2: contains PSC number for DDR2
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* r3: contains virtual base DDR2 PLL controller
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* r4: contains virtual address of the DEEPSLEEP register
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*/
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ENTRY(davinci_cpu_suspend)
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stmfd sp!, {r0-r12, lr} @ save registers on stack
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ldr ip, CACHE_FLUSH
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blx ip
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ldmia r0, {r0-r4}
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/*
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* Switch DDR to self-refresh mode.
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*/
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/* calculate SDRCR address */
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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bic ip, ip, #DDR2_SRPD_BIT
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orr ip, ip, #DDR2_LPMODEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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orr ip, ip, #DDR2_MCLKSTOPEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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mov ip, #PHYRDY_CYCLES
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1: subs ip, ip, #0x1
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bne 1b
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/* Disable DDR2 LPSC */
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mov r7, r0
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mov r0, #0x2
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bl davinci_ddr_psc_config
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mov r0, r7
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/* Disable clock to DDR PHY */
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ldr ip, [r3, #PLLDIV1]
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bic ip, ip, #PLLDIV_EN
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str ip, [r3, #PLLDIV1]
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/* Put the DDR PLL in bypass and power down */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLENSRC
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bic ip, ip, #PLLCTL_PLLEN
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str ip, [r3, #PLLCTL]
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/* Wait for PLL to switch to bypass */
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mov ip, #PLL_BYPASS_CYCLES
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2: subs ip, ip, #0x1
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bne 2b
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/* Power down the PLL */
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ldr ip, [r3, #PLLCTL]
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orr ip, ip, #PLLCTL_PLLPWRDN
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str ip, [r3, #PLLCTL]
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/* Go to deep sleep */
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ldr ip, [r4]
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orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
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/* System goes to sleep beyond after this instruction */
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str ip, [r4]
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/* Wake up from sleep */
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/* Clear sleep enable */
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ldr ip, [r4]
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bic ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
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str ip, [r4]
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/* initialize the DDR PLL controller */
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/* Put PLL in reset */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLRST
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str ip, [r3, #PLLCTL]
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/* Clear PLL power down */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLPWRDN
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str ip, [r3, #PLLCTL]
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mov ip, #PLL_RESET_CYCLES
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3: subs ip, ip, #0x1
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bne 3b
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/* Bring PLL out of reset */
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ldr ip, [r3, #PLLCTL]
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orr ip, ip, #PLLCTL_PLLRST
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str ip, [r3, #PLLCTL]
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/* Wait for PLL to lock (assume prediv = 1, 25MHz OSCIN) */
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mov ip, #PLL_LOCK_CYCLES
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4: subs ip, ip, #0x1
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bne 4b
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/* Remove PLL from bypass mode */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLENSRC
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orr ip, ip, #PLLCTL_PLLEN
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str ip, [r3, #PLLCTL]
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/* Start 2x clock to DDR2 */
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ldr ip, [r3, #PLLDIV1]
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orr ip, ip, #PLLDIV_EN
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str ip, [r3, #PLLDIV1]
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/* Enable VCLK */
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/* Enable DDR2 LPSC */
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mov r7, r0
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mov r0, #0x3
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bl davinci_ddr_psc_config
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mov r0, r7
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/* clear MCLKSTOPEN */
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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bic ip, ip, #DDR2_MCLKSTOPEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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bic ip, ip, #DDR2_LPMODEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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/* Restore registers and return */
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ldmfd sp!, {r0-r12, pc}
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ENDPROC(davinci_cpu_suspend)
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/*
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* Disables or Enables DDR2 LPSC
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* Register Usage:
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* r0: Enable or Disable LPSC r0 = 0x3 => Enable, r0 = 0x2 => Disable LPSC
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* r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
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* r2: contains PSC number for DDR2
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*/
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ENTRY(davinci_ddr_psc_config)
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/* Set next state in mdctl for DDR2 */
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mov r6, #MDCTL
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add r6, r6, r2, lsl #2
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ldr ip, [r1, r6]
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bic ip, ip, #MDSTAT_STATE_MASK
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orr ip, ip, r0
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str ip, [r1, r6]
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/* Enable the Power Domain Transition Command */
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ldr ip, [r1, #PTCMD]
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orr ip, ip, #0x1
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str ip, [r1, #PTCMD]
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/* Check for Transition Complete (PTSTAT) */
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ptstat_done:
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ldr ip, [r1, #PTSTAT]
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and ip, ip, #0x1
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cmp ip, #0x0
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bne ptstat_done
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/* Check for DDR2 clock disable completion; */
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mov r6, #MDSTAT
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add r6, r6, r2, lsl #2
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ddr2clk_stop_done:
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ldr ip, [r1, r6]
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and ip, ip, #MDSTAT_STATE_MASK
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cmp ip, r0
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bne ddr2clk_stop_done
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mov pc, lr
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ENDPROC(davinci_ddr_psc_config)
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CACHE_FLUSH:
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.word arm926_flush_kern_cache_all
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ENTRY(davinci_cpu_suspend_sz)
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.word . - davinci_cpu_suspend
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ENDPROC(davinci_cpu_suspend_sz)
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