sky2: document GPHY_CTRL bits
Add documentation of GPHY_CTRL register bits even if driver is not using them (yet). Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -1850,6 +1850,28 @@ enum {
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/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
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enum {
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GPC_TX_PAUSE = 1<<30, /* Tx pause enabled (ro) */
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GPC_RX_PAUSE = 1<<29, /* Rx pause enabled (ro) */
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GPC_SPEED = 3<<27, /* PHY speed (ro) */
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GPC_LINK = 1<<26, /* Link up (ro) */
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GPC_DUPLEX = 1<<25, /* Duplex (ro) */
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GPC_CLOCK = 1<<24, /* 125Mhz clock stable (ro) */
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GPC_PDOWN = 1<<23, /* Internal regulator 2.5 power down */
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GPC_TSTMODE = 1<<22, /* Test mode */
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GPC_REG18 = 1<<21, /* Reg18 Power down */
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GPC_REG12SEL = 3<<19, /* Reg12 power setting */
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GPC_REG18SEL = 3<<17, /* Reg18 power setting */
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GPC_SPILOCK = 1<<16, /* SPI lock (ASF) */
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GPC_LEDMUX = 3<<14, /* LED Mux */
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GPC_INTPOL = 1<<13, /* Interrupt polarity */
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GPC_DETECT = 1<<12, /* Energy detect */
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GPC_1000HD = 1<<11, /* Enable 1000Mbit HD */
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GPC_SLAVE = 1<<10, /* Slave mode */
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GPC_PAUSE = 1<<9, /* Pause enable */
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GPC_LEDCTL = 3<<6, /* GPHY Leds */
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GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
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GPC_RST_SET = 1<<0, /* Set GPHY Reset */
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};
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