clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6
The pll6 has a /4 output that is used as an input to the ahb mux clock. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -1088,11 +1088,12 @@ static const struct divs_data pll5_divs_data __initconst = {
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static const struct divs_data pll6_divs_data __initconst = {
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.factors = &sun4i_pll6_data,
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.ndivs = 3,
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.ndivs = 4,
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.div = {
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{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
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{ .fixed = 2 }, /* P, other */
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{ .self = 1 }, /* base factor clock, 2x */
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{ .fixed = 4 }, /* pll6 / 4, used as ahb input */
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}
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};
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