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Merge branch 'shmobile' into devel

This commit is contained in:
Russell King 2010-07-31 14:19:22 +01:00
parent e910b63d00 5da3e714e3
commit f13b1035ce
327 changed files with 2761 additions and 1188 deletions
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6
Documentation/00-INDEX
View File

@ -32,8 +32,6 @@ DocBook/
- directory with DocBook templates etc. for kernel documentation.
HOWTO
- the process and procedures of how to do Linux kernel development.
IO-mapping.txt
- how to access I/O mapped memory from within device drivers.
IPMI.txt
- info on Linux Intelligent Platform Management Interface (IPMI) Driver.
IRQ-affinity.txt
@ -84,6 +82,8 @@ blockdev/
- info on block devices & drivers
btmrvl.txt
- info on Marvell Bluetooth driver usage.
bus-virt-phys-mapping.txt
- how to access I/O mapped memory from within device drivers.
cachetlb.txt
- describes the cache/TLB flushing interfaces Linux uses.
cdrom/
@ -168,6 +168,8 @@ initrd.txt
- how to use the RAM disk as an initial/temporary root filesystem.
input/
- info on Linux input device support.
io-mapping.txt
- description of io_mapping functions in linux/io-mapping.h
io_ordering.txt
- info on ordering I/O writes to memory-mapped addresses.
ioctl/

0
Documentation/IO-mapping.txt → Documentation/bus-virt-phys-mapping.txt
View File

7
Documentation/feature-removal-schedule.txt
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@ -647,3 +647,10 @@ Who: Stefan Richter <stefanr@s5r6.in-berlin.de>
----------------------------
What: The acpi_sleep=s4_nonvs command line option
When: 2.6.37
Files: arch/x86/kernel/acpi/sleep.c
Why: superseded by acpi_sleep=nonvs
Who: Rafael J. Wysocki <rjw@sisk.pl>
----------------------------

4
Documentation/kernel-parameters.txt
View File

@ -254,8 +254,8 @@ and is between 256 and 4096 characters. It is defined in the file
control method, with respect to putting devices into
low power states, to be enforced (the ACPI 2.0 ordering
of _PTS is used by default).
s4_nonvs prevents the kernel from saving/restoring the
ACPI NVS memory during hibernation.
nonvs prevents the kernel from saving/restoring the
ACPI NVS memory during suspend/hibernation and resume.
sci_force_enable causes the kernel to set SCI_EN directly
on resume from S1/S3 (which is against the ACPI spec,
but some broken systems don't work without it).

1
MAINTAINERS
View File

@ -5336,6 +5336,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next-2.6.git
S: Maintained
F: arch/sparc/
F: drivers/sbus
SPARC SERIAL DRIVERS
M: "David S. Miller" <davem@davemloft.net>

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 35
EXTRAVERSION = -rc5
EXTRAVERSION = -rc6
NAME = Sheep on Meth
# *DOCUMENTATION*

1
arch/arm/Kconfig
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@ -1173,6 +1173,7 @@ config HZ
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
default 100
config THUMB2_KERNEL

1
arch/arm/mach-clps711x/include/mach/debug-macro.S
View File

@ -11,6 +11,7 @@
*
*/
#include <mach/hardware.h>
#include <asm/hardware/clps7111.h>
.macro addruart, rx, tmp

8
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -25,6 +25,7 @@
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/tps6507x.h>
#include <linux/mfd/tps6507x.h>
#include <linux/input/tps6507x-ts.h>
@ -469,6 +470,11 @@ struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
},
};
/* We take advantage of the fact that both defdcdc{2,3} are tied high */
static struct tps6507x_reg_platform_data tps6507x_platform_data = {
.defdcdc_default = true,
};
struct regulator_init_data tps65070_regulator_data[] = {
/* dcdc1 */
{
@ -494,6 +500,7 @@ struct regulator_init_data tps65070_regulator_data[] = {
},
.num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
.consumer_supplies = tps65070_dcdc2_consumers,
.driver_data = &tps6507x_platform_data,
},
/* dcdc3 */
@ -507,6 +514,7 @@ struct regulator_init_data tps65070_regulator_data[] = {
},
.num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
.consumer_supplies = tps65070_dcdc3_consumers,
.driver_data = &tps6507x_platform_data,
},
/* ldo1 */

2
arch/arm/mach-footbridge/common.c
View File

@ -232,7 +232,7 @@ EXPORT_SYMBOL(__bus_to_virt);
unsigned long __pfn_to_bus(unsigned long pfn)
{
return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET));
return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET);
}
EXPORT_SYMBOL(__pfn_to_bus);

6
arch/arm/mach-h720x/include/mach/debug-macro.S
View File

@ -11,8 +11,10 @@
*
*/
.equ io_virt, IO_BASE
.equ io_phys, IO_START
#include <mach/hardware.h>
.equ io_virt, IO_VIRT
.equ io_phys, IO_PHYS
.macro addruart, rx, tmp
mrc p15, 0, \rx, c1, c0

2
arch/arm/mach-kirkwood/tsx1x-common.c
View File

@ -77,7 +77,7 @@ struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = {
},
};
void qnap_tsx1x_register_flash(void)
void __init qnap_tsx1x_register_flash(void)
{
spi_register_board_info(qnap_tsx1x_spi_slave_info,
ARRAY_SIZE(qnap_tsx1x_spi_slave_info));

2
arch/arm/mach-kirkwood/tsx1x-common.h
View File

@ -1,7 +1,7 @@
#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H
#define __ARCH_KIRKWOOD_TSX1X_COMMON_H
extern void qnap_tsx1x_register_flash(void);
extern void __init qnap_tsx1x_register_flash(void);
extern void qnap_tsx1x_power_off(void);
#endif

1
arch/arm/mach-ns9xxx/include/mach/debug-macro.S
View File

@ -8,6 +8,7 @@
* the Free Software Foundation.
*/
#include <mach/hardware.h>
#include <asm/memory.h>
#include <mach/regs-board-a9m9750dev.h>

30
arch/arm/mach-ns9xxx/include/mach/uncompress.h
View File

@ -20,50 +20,49 @@ static void putc_dummy(char c, void __iomem *base)
/* nothing */
}
static int timeout;
static void putc_ns9360(char c, void __iomem *base)
{
static int t = 0x10000;
do {
if (t)
--t;
if (timeout)
--timeout;
if (__raw_readl(base + 8) & (1 << 3)) {
__raw_writeb(c, base + 16);
t = 0x10000;
timeout = 0x10000;
break;
}
} while (t);
} while (timeout);
}
static void putc_a9m9750dev(char c, void __iomem *base)
{
static int t = 0x10000;
do {
if (t)
--t;
if (timeout)
--timeout;
if (__raw_readb(base + 5) & (1 << 5)) {
__raw_writeb(c, base);
t = 0x10000;
timeout = 0x10000;
break;
}
} while (t);
} while (timeout);
}
static void putc_ns921x(char c, void __iomem *base)
{
static int t = 0x10000;
do {
if (t)
--t;
if (timeout)
--timeout;
if (!(__raw_readl(base) & (1 << 11))) {
__raw_writeb(c, base + 0x0028);
t = 0x10000;
timeout = 0x10000;
break;
}
} while (t);
} while (timeout);
}
#define MSCS __REG(0xA0900184)
@ -89,6 +88,7 @@ static void putc_ns921x(char c, void __iomem *base)
static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
{
timeout = 0x10000;
if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
/* ns9360 or ns9750 */
if (NS9360_UART_ENABLED(NS9360_UARTA)) {

17
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@ -175,6 +175,10 @@ static void __init rx51_add_gpio_keys(void)
#endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */
static int board_keymap[] = {
/*
* Note that KEY(x, 8, KEY_XXX) entries represent "entrire row
* connected to the ground" matrix state.
*/
KEY(0, 0, KEY_Q),
KEY(0, 1, KEY_O),
KEY(0, 2, KEY_P),
@ -182,6 +186,7 @@ static int board_keymap[] = {
KEY(0, 4, KEY_BACKSPACE),
KEY(0, 6, KEY_A),
KEY(0, 7, KEY_S),
KEY(1, 0, KEY_W),
KEY(1, 1, KEY_D),
KEY(1, 2, KEY_F),
@ -190,6 +195,7 @@ static int board_keymap[] = {
KEY(1, 5, KEY_J),
KEY(1, 6, KEY_K),
KEY(1, 7, KEY_L),
KEY(2, 0, KEY_E),
KEY(2, 1, KEY_DOT),
KEY(2, 2, KEY_UP),
@ -197,6 +203,8 @@ static int board_keymap[] = {
KEY(2, 5, KEY_Z),
KEY(2, 6, KEY_X),
KEY(2, 7, KEY_C),
KEY(2, 8, KEY_F9),
KEY(3, 0, KEY_R),
KEY(3, 1, KEY_V),
KEY(3, 2, KEY_B),
@ -205,20 +213,23 @@ static int board_keymap[] = {
KEY(3, 5, KEY_SPACE),
KEY(3, 6, KEY_SPACE),
KEY(3, 7, KEY_LEFT),
KEY(4, 0, KEY_T),
KEY(4, 1, KEY_DOWN),
KEY(4, 2, KEY_RIGHT),
KEY(4, 4, KEY_LEFTCTRL),
KEY(4, 5, KEY_RIGHTALT),
KEY(4, 6, KEY_LEFTSHIFT),
KEY(4, 8, KEY_F10),
KEY(5, 0, KEY_Y),
KEY(5, 8, KEY_F11),
KEY(6, 0, KEY_U),
KEY(7, 0, KEY_I),
KEY(7, 1, KEY_F7),
KEY(7, 2, KEY_F8),
KEY(0xff, 2, KEY_F9),
KEY(0xff, 4, KEY_F10),
KEY(0xff, 5, KEY_F11),
};
static struct matrix_keymap_data board_map_data = {

3
arch/arm/mach-pxa/colibri-pxa300.c
View File

@ -26,6 +26,7 @@
#include <mach/colibri.h>
#include <mach/ohci.h>
#include <mach/pxafb.h>
#include <mach/audio.h>
#include "generic.h"
#include "devices.h"
@ -145,7 +146,7 @@ static void __init colibri_pxa300_init_lcd(void)
static inline void colibri_pxa300_init_lcd(void) {}
#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
#if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE)
#if defined(CONFIG_SND_AC97_CODEC) || defined(CONFIG_SND_AC97_CODEC_MODULE)
static mfp_cfg_t colibri_pxa310_ac97_pin_config[] __initdata = {
GPIO24_AC97_SYSCLK,
GPIO23_AC97_nACRESET,

2
arch/arm/mach-pxa/corgi.c
View File

@ -446,7 +446,7 @@ static struct platform_device corgiled_device = {
static struct pxamci_platform_data corgi_mci_platform_data = {
.detect_delay_ms = 250,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.gpio_card_detect = -1,
.gpio_card_detect = CORGI_GPIO_nSD_DETECT,
.gpio_card_ro = CORGI_GPIO_nSD_WP,
.gpio_power = CORGI_GPIO_SD_PWR,
};

8
arch/arm/mach-pxa/cpufreq-pxa2xx.c
View File

@ -256,13 +256,9 @@ static void init_sdram_rows(void)
static u32 mdrefr_dri(unsigned int freq)
{
u32 dri = 0;
u32 interval = freq * SDRAM_TREF / sdram_rows;
if (cpu_is_pxa25x())
dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
if (cpu_is_pxa27x())
dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
return dri;
return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
}
/* find a valid frequency point */

6
arch/arm/mach-pxa/pxa27x.c
View File

@ -41,10 +41,10 @@ void pxa27x_clear_otgph(void)
EXPORT_SYMBOL(pxa27x_clear_otgph);
static unsigned long ac97_reset_config[] = {
GPIO95_AC97_nRESET,
GPIO95_GPIO,
GPIO113_AC97_nRESET,
GPIO113_GPIO,
GPIO113_AC97_nRESET,
GPIO95_GPIO,
GPIO95_AC97_nRESET,
};
void pxa27x_assert_ac97reset(int reset_gpio, int on)

3
arch/arm/mach-shark/include/mach/debug-macro.S
View File

@ -20,6 +20,9 @@
strb \rd, [\rx]
.endm
.macro waituart,rd,rx
.endm
.macro busyuart,rd,rx
mov \rd, #0
1001: add \rd, \rd, #1

12
arch/arm/mach-shmobile/Kconfig
View File

@ -70,6 +70,18 @@ endmenu
menu "Timer and clock configuration"
config SHMOBILE_TIMER_HZ
int "Kernel HZ (jiffies per second)"
range 32 1024
default "128"
help
Allows the configuration of the timer frequency. It is customary
to have the timer interrupt run at 1000 Hz or 100 Hz, but in the
case of low timer frequencies other values may be more suitable.
SH-Mobile systems using a 32768 Hz RCLK for clock events may want
to select a HZ value such as 128 that can evenly divide RCLK.
A HZ value that does not divide evenly may cause timer drift.
config SH_TIMER_CMT
bool "CMT timer driver"
default y

1
arch/arm/mach-shmobile/include/mach/irqs.h
View File

@ -2,7 +2,6 @@
#define __ASM_MACH_IRQS_H
#define NR_IRQS 512
#define NR_IRQS_LEGACY 8
#define evt2irq(evt) (((evt) >> 5) - 16)
#define irq2evt(irq) (((irq) + 16) << 5)

2
arch/arm/mach-w90x900/cpu.c
View File

@ -93,7 +93,7 @@ static struct clk_lookup nuc900_clkregs[] = {
DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL),
DEF_CLKLOOK(&clk_adc, "nuc900-ts", NULL),
DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
DEF_CLKLOOK(&clk_ext, NULL, "ext"),
DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),

4
arch/arm/plat-spear/include/plat/debug-macro.S
View File

@ -17,8 +17,8 @@
.macro addruart, rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, =SPEAR_DBG_UART_BASE @ Physical base
movne \rx, =VA_SPEAR_DBG_UART_BASE @ Virtual base
moveq \rx, #SPEAR_DBG_UART_BASE @ Physical base
movne \rx, #VA_SPEAR_DBG_UART_BASE @ Virtual base
.endm
.macro senduart, rd, rx

3
arch/avr32/include/asm/ioctls.h
View File

@ -54,6 +54,9 @@
#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
#define TIOCGRS485 0x542E
#define TIOCSRS485 0x542F
#define FIONCLEX 0x5450
#define FIOCLEX 0x5451
#define FIOASYNC 0x5452

2
arch/avr32/mach-at32ap/include/mach/board.h
View File

@ -5,6 +5,7 @@
#define __ASM_ARCH_BOARD_H
#include <linux/types.h>
#include <linux/serial.h>
#define GPIO_PIN_NONE (-1)
@ -35,6 +36,7 @@ struct atmel_uart_data {
short use_dma_tx; /* use transmit DMA? */
short use_dma_rx; /* use receive DMA? */
void __iomem *regs; /* virtual base address, if any */
struct serial_rs485 rs485; /* rs485 settings */
};
void at32_map_usart(unsigned int hw_id, unsigned int line, int flags);
struct platform_device *at32_add_device_usart(unsigned int id);

9
arch/mips/alchemy/common/platform.c
View File

@ -435,20 +435,21 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
static int __init au1xxx_platform_init(void)
{
unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
int i;
int err, i;
/* Fill up uartclk. */
for (i = 0; au1x00_uart_data[i].flags; i++)
au1x00_uart_data[i].uartclk = uartclk;
err = platform_add_devices(au1xxx_platform_devices,
ARRAY_SIZE(au1xxx_platform_devices));
#ifndef CONFIG_SOC_AU1100
/* Register second MAC if enabled in pinfunc */
if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
platform_device_register(&au1xxx_eth1_device);
#endif
return platform_add_devices(au1xxx_platform_devices,
ARRAY_SIZE(au1xxx_platform_devices));
return err;
}
arch_initcall(au1xxx_platform_init);

8
arch/mips/alchemy/mtx-1/board_setup.c
View File

@ -67,8 +67,6 @@ static void mtx1_power_off(void)
void __init board_setup(void)
{
alchemy_gpio2_enable();
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
/* Enable USB power switch */
alchemy_gpio_direction_output(204, 0);
@ -117,11 +115,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
if (assert && devsel != 0)
/* Suppress signal to Cardbus */
gpio_set_value(1, 0); /* set EXT_IO3 OFF */
alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
else
gpio_set_value(1, 1); /* set EXT_IO3 ON */
alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
au_sync_udelay(1);
udelay(1);
return 1;
}

3
arch/mips/bcm63xx/dev-enet.c
View File

@ -104,6 +104,9 @@ int __init bcm63xx_enet_register(int unit,
if (unit > 1)
return -ENODEV;
if (unit == 1 && BCMCPU_IS_6338())
return -ENODEV;
if (!shared_device_registered) {
shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
shared_res[0].end = shared_res[0].start;

24
arch/mips/include/asm/atomic.h
View File

@ -434,7 +434,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
__asm__ __volatile__(
" .set mips3 \n"
"1: lld %0, %1 # atomic64_add \n"
" addu %0, %2 \n"
" daddu %0, %2 \n"
" scd %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
@ -446,7 +446,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
__asm__ __volatile__(
" .set mips3 \n"
"1: lld %0, %1 # atomic64_add \n"
" addu %0, %2 \n"
" daddu %0, %2 \n"
" scd %0, %1 \n"
" beqz %0, 2f \n"
" .subsection 2 \n"
@ -479,7 +479,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
__asm__ __volatile__(
" .set mips3 \n"
"1: lld %0, %1 # atomic64_sub \n"
" subu %0, %2 \n"
" dsubu %0, %2 \n"
" scd %0, %1 \n"
" beqzl %0, 1b \n"
" .set mips0 \n"
@ -491,7 +491,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
__asm__ __volatile__(
" .set mips3 \n"
"1: lld %0, %1 # atomic64_sub \n"
" subu %0, %2 \n"
" dsubu %0, %2 \n"
" scd %0, %1 \n"
" beqz %0, 2f \n"
" .subsection 2 \n"
@ -524,10 +524,10 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
__asm__ __volatile__(
" .set mips3 \n"
"1: lld %1, %2 # atomic64_add_return \n"
" addu %0, %1, %3 \n"
" daddu %0, %1, %3 \n"
" scd %0, %2 \n"
" beqzl %0, 1b \n"
" addu %0, %1, %3 \n"
" daddu %0, %1, %3 \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
@ -538,10 +538,10 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
__asm__ __volatile__(
" .set mips3 \n"
"1: lld %1, %2 # atomic64_add_return \n"
" addu %0, %1, %3 \n"
" daddu %0, %1, %3 \n"
" scd %0, %2 \n"
" beqz %0, 2f \n"
" addu %0, %1, %3 \n"
" daddu %0, %1, %3 \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"
@ -576,10 +576,10 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
__asm__ __volatile__(
" .set mips3 \n"
"1: lld %1, %2 # atomic64_sub_return \n"
" subu %0, %1, %3 \n"
" dsubu %0, %1, %3 \n"
" scd %0, %2 \n"
" beqzl %0, 1b \n"
" subu %0, %1, %3 \n"
" dsubu %0, %1, %3 \n"
" .set mips0 \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
@ -590,10 +590,10 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
__asm__ __volatile__(
" .set mips3 \n"
"1: lld %1, %2 # atomic64_sub_return \n"
" subu %0, %1, %3 \n"
" dsubu %0, %1, %3 \n"
" scd %0, %2 \n"
" beqz %0, 2f \n"
" subu %0, %1, %3 \n"
" dsubu %0, %1, %3 \n"
" .subsection 2 \n"
"2: b 1b \n"
" .previous \n"

5
arch/mips/include/asm/unistd.h
View File

@ -984,16 +984,17 @@
#define __NR_perf_event_open (__NR_Linux + 296)
#define __NR_accept4 (__NR_Linux + 297)
#define __NR_recvmmsg (__NR_Linux + 298)
#define __NR_getdents64 (__NR_Linux + 299)
/*
* Offset of the last N32 flavoured syscall
*/
#define __NR_Linux_syscalls 298
#define __NR_Linux_syscalls 299
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
#define __NR_N32_Linux 6000
#define __NR_N32_Linux_syscalls 298
#define __NR_N32_Linux_syscalls 299
#ifdef __KERNEL__

1
arch/mips/kernel/scall64-n32.S
View File

@ -419,4 +419,5 @@ EXPORT(sysn32_call_table)
PTR sys_perf_event_open
PTR sys_accept4
PTR compat_sys_recvmmsg
PTR sys_getdents
.size sysn32_call_table,.-sysn32_call_table

4
arch/mips/kernel/vdso.c
View File

@ -61,11 +61,9 @@ static int __init init_vdso(void)
vunmap(vdso);
pr_notice("init_vdso successfull\n");
return 0;
}
device_initcall(init_vdso);
subsys_initcall(init_vdso);
static unsigned long vdso_addr(unsigned long start)
{

2
arch/mips/mti-malta/malta-pci.c
View File

@ -247,6 +247,8 @@ void __init mips_pcibios_init(void)
iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
ioport_resource.end = controller->io_resource->end;
controller->io_map_base = mips_io_port_base;
register_pci_controller(controller);
}

1
arch/mips/nxp/pnx8550/common/pci.c
View File

@ -44,6 +44,7 @@ extern struct pci_ops pnx8550_pci_ops;
static struct pci_controller pnx8550_controller = {
.pci_ops = &pnx8550_pci_ops,
.io_map_base = PNX8550_PORT_BASE,
.io_resource = &pci_io_resource,
.mem_resource = &pci_mem_resource,
};

2
arch/mips/nxp/pnx8550/common/setup.c
View File

@ -113,7 +113,7 @@ void __init plat_mem_setup(void)
PNX8550_GLB2_ENAB_INTA_O = 0;
/* IO/MEM resources. */
set_io_port_base(KSEG1);
set_io_port_base(PNX8550_PORT_BASE);
ioport_resource.start = 0;
ioport_resource.end = ~0;
iomem_resource.start = 0;

1
arch/mips/pci/ops-pmcmsp.c
View File

@ -944,6 +944,7 @@ static struct pci_controller msp_pci_controller = {
.pci_ops = &msp_pci_ops,
.mem_resource = &pci_mem_resource,
.mem_offset = 0,
.io_map_base = MSP_PCI_IOSPACE_BASE,
.io_resource = &pci_io_resource,
.io_offset = 0
};

1
arch/mips/pci/pci-yosemite.c
View File

@ -54,6 +54,7 @@ static int __init pmc_yosemite_setup(void)
panic(ioremap_failed);
set_io_port_base(io_v_base);
py_controller.io_map_base = io_v_base;
TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
ioport_resource.end = TITAN_IO_SIZE - 1;

5
arch/mips/powertv/asic/asic_devices.c
View File

@ -472,6 +472,9 @@ void __init configure_platform(void)
* it*/
platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
/* Cronus and Cronus Lite have the same register map */
set_register_map(CRONUS_IO_BASE, &cronus_register_map);
/* ASIC version will determine if this is a real CronusLite or
* Castrati(Cronus) */
chipversion = asic_read(chipver3) << 24;
@ -484,8 +487,6 @@ void __init configure_platform(void)
else
asic = ASIC_CRONUSLITE;
/* Cronus and Cronus Lite have the same register map */
set_register_map(CRONUS_IO_BASE, &cronus_register_map);
gp_resources = non_dvr_cronuslite_resources;
pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
"chipversion=0x%08X\n",

6
arch/powerpc/include/asm/kexec.h
View File

@ -8,9 +8,9 @@
* On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory
* and therefore we can only deal with memory within this range
*/
#define KEXEC_SOURCE_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL)
#define KEXEC_DESTINATION_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL)
#define KEXEC_CONTROL_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL)
#define KEXEC_SOURCE_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL - 1)
#define KEXEC_DESTINATION_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL - 1)
#define KEXEC_CONTROL_MEMORY_LIMIT (2 * 1024 * 1024 * 1024UL - 1)
#else

4
arch/powerpc/include/asm/mmu-hash64.h
View File

@ -250,7 +250,9 @@ extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
pte_t *ptep, unsigned long trap, int local, int ssize,
unsigned int shift, unsigned int mmu_psize);
extern void hash_failure_debug(unsigned long ea, unsigned long access,
unsigned long vsid, unsigned long trap,
int ssize, int psize, unsigned long pte);
extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
unsigned long pstart, unsigned long prot,
int psize, int ssize);

6
arch/powerpc/kernel/perf_event_fsl_emb.c
View File

@ -566,9 +566,9 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
* Finally record data if requested.
*/
if (record) {
struct perf_sample_data data = {
.period = event->hw.last_period,
};
struct perf_sample_data data;
perf_sample_data_init(&data, 0);
if (perf_event_overflow(event, nmi, &data, regs)) {
/*

2
arch/powerpc/kernel/prom.c
View File

@ -414,7 +414,7 @@ static int __init early_init_dt_scan_drconf_memory(unsigned long node)
u64 base, size, memblock_size;
unsigned int is_kexec_kdump = 0, rngs;
ls = of_get_flat_dt_prop(node, "ibm,memblock-size", &l);
ls = of_get_flat_dt_prop(node, "ibm,lmb-size", &l);
if (ls == NULL || l < dt_root_size_cells * sizeof(__be32))
return 0;
memblock_size = dt_mem_next_cell(dt_root_size_cells, &ls);

9
arch/powerpc/mm/hash_low_64.S
View File

@ -68,9 +68,6 @@ _GLOBAL(__hash_page_4K)
std r8,STK_PARM(r8)(r1)
std r9,STK_PARM(r9)(r1)
/* Add _PAGE_PRESENT to access */
ori r4,r4,_PAGE_PRESENT
/* Save non-volatile registers.
* r31 will hold "old PTE"
* r30 is "new PTE"
@ -347,9 +344,6 @@ _GLOBAL(__hash_page_4K)
std r8,STK_PARM(r8)(r1)
std r9,STK_PARM(r9)(r1)
/* Add _PAGE_PRESENT to access */
ori r4,r4,_PAGE_PRESENT
/* Save non-volatile registers.
* r31 will hold "old PTE"
* r30 is "new PTE"
@ -687,9 +681,6 @@ _GLOBAL(__hash_page_64K)
std r8,STK_PARM(r8)(r1)
std r9,STK_PARM(r9)(r1)
/* Add _PAGE_PRESENT to access */
ori r4,r4,_PAGE_PRESENT
/* Save non-volatile registers.
* r31 will hold "old PTE"
* r30 is "new PTE"

53
arch/powerpc/mm/hash_utils_64.c
View File

@ -871,6 +871,18 @@ static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
}
#endif
void hash_failure_debug(unsigned long ea, unsigned long access,
unsigned long vsid, unsigned long trap,
int ssize, int psize, unsigned long pte)
{
if (!printk_ratelimit())
return;
pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
ea, access, current->comm);
pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
trap, vsid, ssize, psize, pte);
}
/* Result code is:
* 0 - handled
* 1 - normal page fault
@ -955,6 +967,17 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
return 1;
}
/* Add _PAGE_PRESENT to the required access perm */
access |= _PAGE_PRESENT;
/* Pre-check access permissions (will be re-checked atomically
* in __hash_page_XX but this pre-check is a fast path
*/
if (access & ~pte_val(*ptep)) {
DBG_LOW(" no access !\n");
return 1;
}
#ifdef CONFIG_HUGETLB_PAGE
if (hugeshift)
return __hash_page_huge(ea, access, vsid, ptep, trap, local,
@ -967,14 +990,6 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
pte_val(*(ptep + PTRS_PER_PTE)));
#endif
/* Pre-check access permissions (will be re-checked atomically
* in __hash_page_XX but this pre-check is a fast path
*/
if (access & ~pte_val(*ptep)) {
DBG_LOW(" no access !\n");
return 1;
}
/* Do actual hashing */
#ifdef CONFIG_PPC_64K_PAGES
/* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
@ -1033,6 +1048,12 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
local, ssize, spp);
}
/* Dump some info in case of hash insertion failure, they should
* never happen so it is really useful to know if/when they do
*/
if (rc == -1)
hash_failure_debug(ea, access, vsid, trap, ssize, psize,
pte_val(*ptep));
#ifndef CONFIG_PPC_64K_PAGES
DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
#else
@ -1051,8 +1072,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
void *pgdir;
pte_t *ptep;
unsigned long flags;
int local = 0;
int ssize;
int rc, ssize, local = 0;
BUG_ON(REGION_ID(ea) != USER_REGION_ID);
@ -1098,11 +1118,18 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
/* Hash it in */
#ifdef CONFIG_PPC_HAS_HASH_64K
if (mm->context.user_psize == MMU_PAGE_64K)
__hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
else
#endif /* CONFIG_PPC_HAS_HASH_64K */
__hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
subpage_protection(pgdir, ea));
rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
subpage_protection(pgdir, ea));
/* Dump some info in case of hash insertion failure, they should
* never happen so it is really useful to know if/when they do
*/
if (rc == -1)
hash_failure_debug(ea, access, vsid, trap, ssize,
mm->context.user_psize, pte_val(*ptep));
local_irq_restore(flags);
}

40
arch/powerpc/mm/hugetlbpage-hash64.c
View File

@ -21,21 +21,13 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
unsigned long old_pte, new_pte;
unsigned long va, rflags, pa, sz;
long slot;
int err = 1;
BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
/* Search the Linux page table for a match with va */
va = hpt_va(ea, vsid, ssize);
/*
* Check the user's access rights to the page. If access should be
* prevented then send the problem up to do_page_fault.
*/
if (unlikely(access & ~pte_val(*ptep)))
goto out;
/*
* At this point, we have a pte (old_pte) which can be used to build
/* At this point, we have a pte (old_pte) which can be used to build
* or update an HPTE. There are 2 cases:
*
* 1. There is a valid (present) pte with no associated HPTE (this is
@ -49,9 +41,17 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
do {
old_pte = pte_val(*ptep);
if (old_pte & _PAGE_BUSY)
goto out;
/* If PTE busy, retry the access */
if (unlikely(old_pte & _PAGE_BUSY))
return 0;
/* If PTE permissions don't match, take page fault */
if (unlikely(access & ~old_pte))
return 1;
/* Try to lock the PTE, add ACCESSED and DIRTY if it was
* a write access */
new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED;
if (access & _PAGE_RW)
new_pte |= _PAGE_DIRTY;
} while(old_pte != __cmpxchg_u64((unsigned long *)ptep,
old_pte, new_pte));
@ -121,8 +121,16 @@ repeat:
}
}
if (unlikely(slot == -2))
panic("hash_huge_page: pte_insert failed\n");
/*
* Hypervisor failure. Restore old pte and return -1
* similar to __hash_page_*
*/
if (unlikely(slot == -2)) {
*ptep = __pte(old_pte);
hash_failure_debug(ea, access, vsid, trap, ssize,
mmu_psize, old_pte);
return -1;
}
new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX);
}
@ -131,9 +139,5 @@ repeat:
* No need to use ldarx/stdcx here
*/
*ptep = __pte(new_pte & ~_PAGE_BUSY);
err = 0;
out:
return err;
return 0;
}

24
arch/powerpc/mm/numa.c
View File

@ -398,15 +398,15 @@ static int of_get_drconf_memory(struct device_node *memory, const u32 **dm)
}
/*
* Retreive and validate the ibm,memblock-size property for drconf memory
* Retreive and validate the ibm,lmb-size property for drconf memory
* from the device tree.
*/
static u64 of_get_memblock_size(struct device_node *memory)
static u64 of_get_lmb_size(struct device_node *memory)
{
const u32 *prop;
u32 len;
prop = of_get_property(memory, "ibm,memblock-size", &len);
prop = of_get_property(memory, "ibm,lmb-size", &len);
if (!prop || len < sizeof(unsigned int))
return 0;
@ -562,7 +562,7 @@ static unsigned long __init numa_enforce_memory_limit(unsigned long start,
static inline int __init read_usm_ranges(const u32 **usm)
{
/*
* For each memblock in ibm,dynamic-memory a corresponding
* For each lmb in ibm,dynamic-memory a corresponding
* entry in linux,drconf-usable-memory property contains
* a counter followed by that many (base, size) duple.
* read the counter from linux,drconf-usable-memory
@ -578,7 +578,7 @@ static void __init parse_drconf_memory(struct device_node *memory)
{
const u32 *dm, *usm;
unsigned int n, rc, ranges, is_kexec_kdump = 0;
unsigned long memblock_size, base, size, sz;
unsigned long lmb_size, base, size, sz;
int nid;
struct assoc_arrays aa;
@ -586,8 +586,8 @@ static void __init parse_drconf_memory(struct device_node *memory)
if (!n)
return;
memblock_size = of_get_memblock_size(memory);
if (!memblock_size)
lmb_size = of_get_lmb_size(memory);
if (!lmb_size)
return;
rc = of_get_assoc_arrays(memory, &aa);
@ -611,7 +611,7 @@ static void __init parse_drconf_memory(struct device_node *memory)
continue;
base = drmem.base_addr;
size = memblock_size;
size = lmb_size;
ranges = 1;
if (is_kexec_kdump) {
@ -1072,7 +1072,7 @@ static int hot_add_drconf_scn_to_nid(struct device_node *memory,
{
const u32 *dm;
unsigned int drconf_cell_cnt, rc;
unsigned long memblock_size;
unsigned long lmb_size;
struct assoc_arrays aa;
int nid = -1;
@ -1080,8 +1080,8 @@ static int hot_add_drconf_scn_to_nid(struct device_node *memory,
if (!drconf_cell_cnt)
return -1;
memblock_size = of_get_memblock_size(memory);
if (!memblock_size)
lmb_size = of_get_lmb_size(memory);
if (!lmb_size)
return -1;
rc = of_get_assoc_arrays(memory, &aa);
@ -1100,7 +1100,7 @@ static int hot_add_drconf_scn_to_nid(struct device_node *memory,
continue;
if ((scn_addr < drmem.base_addr)
|| (scn_addr >= (drmem.base_addr + memblock_size)))
|| (scn_addr >= (drmem.base_addr + lmb_size)))
continue;
nid = of_drconf_to_nid_single(&drmem, &aa);

22
arch/powerpc/platforms/pseries/hotplug-memory.c
View File

@ -69,7 +69,7 @@ static int pseries_remove_memory(struct device_node *np)
const char *type;
const unsigned int *regs;
unsigned long base;
unsigned int memblock_size;
unsigned int lmb_size;
int ret = -EINVAL;
/*
@ -87,9 +87,9 @@ static int pseries_remove_memory(struct device_node *np)
return ret;
base = *(unsigned long *)regs;
memblock_size = regs[3];
lmb_size = regs[3];
ret = pseries_remove_memblock(base, memblock_size);
ret = pseries_remove_memblock(base, lmb_size);
return ret;
}
@ -98,7 +98,7 @@ static int pseries_add_memory(struct device_node *np)
const char *type;
const unsigned int *regs;
unsigned long base;
unsigned int memblock_size;
unsigned int lmb_size;
int ret = -EINVAL;
/*
@ -116,36 +116,36 @@ static int pseries_add_memory(struct device_node *np)
return ret;
base = *(unsigned long *)regs;
memblock_size = regs[3];
lmb_size = regs[3];
/*
* Update memory region to represent the memory add
*/
ret = memblock_add(base, memblock_size);
ret = memblock_add(base, lmb_size);
return (ret < 0) ? -EINVAL : 0;
}
static int pseries_drconf_memory(unsigned long *base, unsigned int action)
{
struct device_node *np;
const unsigned long *memblock_size;
const unsigned long *lmb_size;
int rc;
np = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
if (!np)
return -EINVAL;
memblock_size = of_get_property(np, "ibm,memblock-size", NULL);
if (!memblock_size) {
lmb_size = of_get_property(np, "ibm,lmb-size", NULL);
if (!lmb_size) {
of_node_put(np);
return -EINVAL;
}
if (action == PSERIES_DRCONF_MEM_ADD) {
rc = memblock_add(*base, *memblock_size);
rc = memblock_add(*base, *lmb_size);
rc = (rc < 0) ? -EINVAL : 0;
} else if (action == PSERIES_DRCONF_MEM_REMOVE) {
rc = pseries_remove_memblock(*base, *memblock_size);
rc = pseries_remove_memblock(*base, *lmb_size);
} else {
rc = -EINVAL;
}

49
arch/sparc/configs/sparc64_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.34-rc3
# Sat Apr 3 15:49:56 2010
# Linux kernel version: 2.6.34
# Wed May 26 21:14:01 2010
#
CONFIG_64BIT=y
CONFIG_SPARC=y
@ -107,10 +107,9 @@ CONFIG_PERF_COUNTERS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PCI_QUIRKS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
@ -239,6 +238,7 @@ CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_COMPACTION is not set
CONFIG_MIGRATION=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_ZONE_DMA_FLAG=0
@ -351,6 +351,7 @@ CONFIG_IPV6_TUNNEL=m
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
CONFIG_VLAN_8021Q=m
@ -367,6 +368,7 @@ CONFIG_VLAN_8021Q=m
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
CONFIG_RPS=y
#
# Network testing
@ -386,9 +388,14 @@ CONFIG_WIRELESS=y
#
# CFG80211 needs to be enabled for MAC80211
#
#
# Some wireless drivers require a rate control algorithm
#
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
#
# Device Drivers
@ -658,6 +665,7 @@ CONFIG_PHYLIB=m
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=m
@ -734,6 +742,8 @@ CONFIG_NETDEV_10000=y
# CONFIG_CHELSIO_T1 is not set
CONFIG_CHELSIO_T3_DEPENDS=y
# CONFIG_CHELSIO_T3 is not set
CONFIG_CHELSIO_T4_DEPENDS=y
# CONFIG_CHELSIO_T4 is not set
# CONFIG_ENIC is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
@ -766,6 +776,7 @@ CONFIG_NIU=m
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
@ -778,7 +789,6 @@ CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_MPPE=m
CONFIG_PPPOE=m
# CONFIG_PPPOL2TP is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
# CONFIG_NET_FC is not set
@ -816,6 +826,7 @@ CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_QT2160 is not set
CONFIG_KEYBOARD_LKKBD=m
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
@ -840,6 +851,7 @@ CONFIG_MOUSE_SERIAL=y
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
CONFIG_INPUT_SPARCSPKR=y
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
@ -848,6 +860,7 @@ CONFIG_INPUT_SPARCSPKR=y
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
#
# Hardware I/O ports
@ -871,6 +884,7 @@ CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_DEVKMEM is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_NOZOMI is not set
#
@ -893,6 +907,8 @@ CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_TIMBERDALE is not set
# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -1306,11 +1322,14 @@ CONFIG_USB_HIDDEV=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
# CONFIG_HID_CANDO is not set
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
# CONFIG_HID_PRODIKEYS is not set
CONFIG_HID_CYPRESS=y
CONFIG_HID_DRAGONRISE=y
# CONFIG_DRAGONRISE_FF is not set
# CONFIG_HID_EGALAX is not set
CONFIG_HID_EZKEY=y
CONFIG_HID_KYE=y
CONFIG_HID_GYRATION=y
@ -1328,7 +1347,9 @@ CONFIG_HID_ORTEK=y
CONFIG_HID_PANTHERLORD=y
# CONFIG_PANTHERLORD_FF is not set
CONFIG_HID_PETALYNX=y
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_QUANTA is not set
# CONFIG_HID_ROCCAT_KONE is not set
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
# CONFIG_HID_STANTUM is not set
@ -1342,6 +1363,7 @@ CONFIG_HID_THRUSTMASTER=y
# CONFIG_THRUSTMASTER_FF is not set
CONFIG_HID_ZEROPLUS=y
# CONFIG_ZEROPLUS_FF is not set
# CONFIG_HID_ZYDACRON is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
@ -1356,7 +1378,6 @@ CONFIG_USB=y
# CONFIG_USB_DEVICEFS is not set
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_WUSB is not set
# CONFIG_USB_WUSB_CBAF is not set
@ -1521,10 +1542,6 @@ CONFIG_RTC_DRV_STARFIRE=y
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
#
# TI VLYNQ
#
# CONFIG_STAGING is not set
#
@ -1706,8 +1723,8 @@ CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
CONFIG_SCHEDSTATS=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
@ -1742,6 +1759,9 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
@ -1769,12 +1789,12 @@ CONFIG_BLK_DEV_IO_TRACE=y
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_DCFLUSH is not set
# CONFIG_STACK_DEBUG is not set
# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
#
@ -1895,6 +1915,7 @@ CONFIG_CRYPTO_DEFLATE=y
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_NIAGARA2 is not set
# CONFIG_CRYPTO_DEV_HIFN_795X is not set
CONFIG_BINARY_PRINTF=y

1
arch/sparc/include/asm/cache.h
View File

@ -11,7 +11,6 @@
#define L1_CACHE_SHIFT 5
#define L1_CACHE_BYTES 32
#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
#ifdef CONFIG_SPARC32
#define SMP_CACHE_BYTES_SHIFT 5

5
arch/sparc/include/asm/pgtable_32.h
View File

@ -142,13 +142,12 @@ BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t)
#define pmd_page(pmd) BTFIXUP_CALL(pmd_page)(pmd)
#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd)
BTFIXUPDEF_SETHI(none_mask)
BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t)
BTFIXUPDEF_CALL(void, pte_clear, pte_t *)
static inline int pte_none(pte_t pte)
{
return !(pte_val(pte) & ~BTFIXUP_SETHI(none_mask));
return !pte_val(pte);
}
#define pte_present(pte) BTFIXUP_CALL(pte_present)(pte)
@ -160,7 +159,7 @@ BTFIXUPDEF_CALL(void, pmd_clear, pmd_t *)
static inline int pmd_none(pmd_t pmd)
{
return !(pmd_val(pmd) & ~BTFIXUP_SETHI(none_mask));
return !pmd_val(pmd);
}
#define pmd_bad(pmd) BTFIXUP_CALL(pmd_bad)(pmd)

1
arch/sparc/kernel/perf_event.c
View File

@ -657,6 +657,7 @@ static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
cpuc->current_idx[i] = idx;
enc = perf_event_get_enc(cpuc->events[i]);
pcr &= ~mask_for_index(idx);
pcr |= event_encoding(enc, idx);
}
out:

2
arch/sparc/kernel/sun4d_irq.c
View File

@ -183,7 +183,7 @@ void sun4d_free_irq(unsigned int irq, void *dev_id)
goto out_unlock;
}
if (action && tmp)
if (tmp)
tmp->next = action->next;
else
*actionp = action->next;

2
arch/sparc/kernel/ttable.S
View File

@ -64,7 +64,7 @@ tl0_irq6: TRAP_IRQ(smp_call_function_single_client, 6)
tl0_irq6: BTRAP(0x46)
#endif
tl0_irq7: TRAP_IRQ(deferred_pcr_work_irq, 7)
#ifdef CONFIG_KGDB
#if defined(CONFIG_KGDB) && defined(CONFIG_SMP)
tl0_irq8: TRAP_IRQ(smp_kgdb_capture_client, 8)
#else
tl0_irq8: BTRAP(0x48)

2
arch/sparc/mm/srmmu.c
View File

@ -2215,8 +2215,6 @@ void __init ld_mmu_srmmu(void)
BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
BTFIXUPSET_SETHI(none_mask, 0xF0000000);
BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);

3
arch/sparc/mm/sun4c.c
View File

@ -2087,9 +2087,6 @@ void __init ld_mmu_sun4c(void)
BTFIXUPSET_CALL(set_pte, sun4c_set_pte, BTFIXUPCALL_STO1O0);
/* The 2.4.18 code does not set this on sun4c, how does it work? XXX */
/* BTFIXUPSET_SETHI(none_mask, 0x00000000); */ /* Defaults to zero? */
BTFIXUPSET_CALL(pte_pfn, sun4c_pte_pfn, BTFIXUPCALL_NORM);
#if 0 /* PAGE_SHIFT <= 12 */ /* Eek. Investigate. XXX */
BTFIXUPSET_CALL(pmd_page, sun4c_pmd_page, BTFIXUPCALL_ANDNINT(PAGE_SIZE - 1));

9
arch/x86/kernel/acpi/cstate.c
View File

@ -145,6 +145,15 @@ int acpi_processor_ffh_cstate_probe(unsigned int cpu,
percpu_entry->states[cx->index].eax = cx->address;
percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
}
/*
* For _CST FFH on Intel, if GAS.access_size bit 1 is cleared,
* then we should skip checking BM_STS for this C-state.
* ref: "Intel Processor Vendor-Specific ACPI Interface Specification"
*/
if ((c->x86_vendor == X86_VENDOR_INTEL) && !(reg->access_size & 0x2))
cx->bm_sts_skip = 1;
return retval;
}
EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);

9
arch/x86/kernel/acpi/sleep.c
View File

@ -157,9 +157,14 @@ static int __init acpi_sleep_setup(char *str)
#ifdef CONFIG_HIBERNATION
if (strncmp(str, "s4_nohwsig", 10) == 0)
acpi_no_s4_hw_signature();
if (strncmp(str, "s4_nonvs", 8) == 0)
acpi_s4_no_nvs();
if (strncmp(str, "s4_nonvs", 8) == 0) {
pr_warning("ACPI: acpi_sleep=s4_nonvs is deprecated, "
"please use acpi_sleep=nonvs instead");
acpi_nvs_nosave();
}
#endif
if (strncmp(str, "nonvs", 5) == 0)
acpi_nvs_nosave();
if (strncmp(str, "old_ordering", 12) == 0)
acpi_old_suspend_ordering();
str = strchr(str, ',');

2
arch/x86/kernel/apic/apic.c
View File

@ -921,7 +921,7 @@ void disable_local_APIC(void)
unsigned int value;
/* APIC hasn't been mapped yet */
if (!apic_phys)
if (!x2apic_mode && !apic_phys)
return;
clear_local_APIC();

41
arch/x86/kernel/cpu/cpufreq/pcc-cpufreq.c
View File

@ -368,22 +368,16 @@ static int __init pcc_cpufreq_do_osc(acpi_handle *handle)
return -ENODEV;
out_obj = output.pointer;
if (out_obj->type != ACPI_TYPE_BUFFER) {
ret = -ENODEV;
goto out_free;
}
if (out_obj->type != ACPI_TYPE_BUFFER)
return -ENODEV;
errors = *((u32 *)out_obj->buffer.pointer) & ~(1 << 0);
if (errors) {
ret = -ENODEV;
goto out_free;
}
if (errors)
return -ENODEV;
supported = *((u32 *)(out_obj->buffer.pointer + 4));
if (!(supported & 0x1)) {
ret = -ENODEV;
goto out_free;
}
if (!(supported & 0x1))
return -ENODEV;
out_free:
kfree(output.pointer);
@ -397,13 +391,17 @@ static int __init pcc_cpufreq_probe(void)
struct pcc_memory_resource *mem_resource;
struct pcc_register_resource *reg_resource;
union acpi_object *out_obj, *member;
acpi_handle handle, osc_handle;
acpi_handle handle, osc_handle, pcch_handle;
int ret = 0;
status = acpi_get_handle(NULL, "\\_SB", &handle);
if (ACPI_FAILURE(status))
return -ENODEV;
status = acpi_get_handle(handle, "PCCH", &pcch_handle);
if (ACPI_FAILURE(status))
return -ENODEV;
status = acpi_get_handle(handle, "_OSC", &osc_handle);
if (ACPI_SUCCESS(status)) {
ret = pcc_cpufreq_do_osc(&osc_handle);
@ -543,13 +541,13 @@ static int pcc_cpufreq_cpu_init(struct cpufreq_policy *policy)
if (!pcch_virt_addr) {
result = -1;
goto pcch_null;
goto out;
}
result = pcc_get_offset(cpu);
if (result) {
dprintk("init: PCCP evaluation failed\n");
goto free;
goto out;
}
policy->max = policy->cpuinfo.max_freq =
@ -558,14 +556,15 @@ static int pcc_cpufreq_cpu_init(struct cpufreq_policy *policy)
ioread32(&pcch_hdr->minimum_frequency) * 1000;
policy->cur = pcc_get_freq(cpu);
if (!policy->cur) {
dprintk("init: Unable to get current CPU frequency\n");
result = -EINVAL;
goto out;
}
dprintk("init: policy->max is %d, policy->min is %d\n",
policy->max, policy->min);
return 0;
free:
pcc_clear_mapping();
free_percpu(pcc_cpu_info);
pcch_null:
out:
return result;
}

11
arch/x86/kernel/cpu/cpufreq/powernow-k8.c
View File

@ -1023,13 +1023,12 @@ static int get_transition_latency(struct powernow_k8_data *data)
}
if (max_latency == 0) {
/*
* Fam 11h always returns 0 as transition latency.
* This is intended and means "very fast". While cpufreq core
* and governors currently can handle that gracefully, better
* set it to 1 to avoid problems in the future.
* For all others it's a BIOS bug.
* Fam 11h and later may return 0 as transition latency. This
* is intended and means "very fast". While cpufreq core and
* governors currently can handle that gracefully, better set it
* to 1 to avoid problems in the future.
*/
if (boot_cpu_data.x86 != 0x11)
if (boot_cpu_data.x86 < 0x11)
printk(KERN_ERR FW_WARN PFX "Invalid zero transition "
"latency\n");
max_latency = 1;

18
arch/x86/kernel/early-quirks.c
View File

@ -18,6 +18,7 @@
#include <asm/apic.h>
#include <asm/iommu.h>
#include <asm/gart.h>
#include <asm/hpet.h>
static void __init fix_hypertransport_config(int num, int slot, int func)
{
@ -191,6 +192,21 @@ static void __init ati_bugs_contd(int num, int slot, int func)
}
#endif
/*
* Force the read back of the CMP register in hpet_next_event()
* to work around the problem that the CMP register write seems to be
* delayed. See hpet_next_event() for details.
*
* We do this on all SMBUS incarnations for now until we have more
* information about the affected chipsets.
*/
static void __init ati_hpet_bugs(int num, int slot, int func)
{
#ifdef CONFIG_HPET_TIMER
hpet_readback_cmp = 1;
#endif
}
#define QFLAG_APPLY_ONCE 0x1
#define QFLAG_APPLIED 0x2
#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
@ -220,6 +236,8 @@ static struct chipset early_qrk[] __initdata = {
PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
{ PCI_VENDOR_ID_ATI, PCI_ANY_ID,
PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_hpet_bugs },
{}
};

4
arch/x86/kernel/entry_64.S
View File

@ -571,8 +571,8 @@ auditsys:
* masked off.
*/
sysret_audit:
movq %rax,%rsi /* second arg, syscall return value */
cmpq $0,%rax /* is it < 0? */
movq RAX-ARGOFFSET(%rsp),%rsi /* second arg, syscall return value */
cmpq $0,%rsi /* is it < 0? */
setl %al /* 1 if so, 0 if not */
movzbl %al,%edi /* zero-extend that into %edi */
inc %edi /* first arg, 0->1(AUDITSC_SUCCESS), 1->2(AUDITSC_FAILURE) */

2
arch/x86/kernel/hpet.c
View File

@ -964,7 +964,7 @@ fs_initcall(hpet_late_init);
void hpet_disable(void)
{
if (is_hpet_capable()) {
if (is_hpet_capable() && hpet_virt_address) {
unsigned int cfg = hpet_readl(HPET_CFG);
if (hpet_legacy_int_enabled) {

25
arch/x86/kernel/i8259.c
View File

@ -276,16 +276,6 @@ static struct sys_device device_i8259A = {
.cls = &i8259_sysdev_class,
};
static int __init i8259A_init_sysfs(void)
{
int error = sysdev_class_register(&i8259_sysdev_class);
if (!error)
error = sysdev_register(&device_i8259A);
return error;
}
device_initcall(i8259A_init_sysfs);
static void mask_8259A(void)
{
unsigned long flags;
@ -407,3 +397,18 @@ struct legacy_pic default_legacy_pic = {
};
struct legacy_pic *legacy_pic = &default_legacy_pic;
static int __init i8259A_init_sysfs(void)
{
int error;
if (legacy_pic != &default_legacy_pic)
return 0;
error = sysdev_class_register(&i8259_sysdev_class);
if (!error)
error = sysdev_register(&device_i8259A);
return error;
}
device_initcall(i8259A_init_sysfs);

9
arch/x86/kernel/kgdb.c
View File

@ -572,7 +572,6 @@ static int __kgdb_notify(struct die_args *args, unsigned long cmd)
return NOTIFY_STOP;
}
#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
int kgdb_ll_trap(int cmd, const char *str,
struct pt_regs *regs, long err, int trap, int sig)
{
@ -590,7 +589,6 @@ int kgdb_ll_trap(int cmd, const char *str,
return __kgdb_notify(&args, cmd);
}
#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
static int
kgdb_notify(struct notifier_block *self, unsigned long cmd, void *ptr)
@ -625,6 +623,12 @@ int kgdb_arch_init(void)
return register_die_notifier(&kgdb_notifier);
}
static void kgdb_hw_overflow_handler(struct perf_event *event, int nmi,
struct perf_sample_data *data, struct pt_regs *regs)
{
kgdb_ll_trap(DIE_DEBUG, "debug", regs, 0, 0, SIGTRAP);
}
void kgdb_arch_late(void)
{
int i, cpu;
@ -655,6 +659,7 @@ void kgdb_arch_late(void)
for_each_online_cpu(cpu) {
pevent = per_cpu_ptr(breakinfo[i].pev, cpu);
pevent[0]->hw.sample_period = 1;
pevent[0]->overflow_handler = kgdb_hw_overflow_handler;
if (pevent[0]->destroy != NULL) {
pevent[0]->destroy = NULL;
release_bp_slot(*pevent);

2
arch/x86/kernel/kprobes.c
View File

@ -640,8 +640,8 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
/* Skip cs, ip, orig_ax and gs. */ \
" subl $16, %esp\n" \
" pushl %fs\n" \
" pushl %ds\n" \
" pushl %es\n" \
" pushl %ds\n" \
" pushl %eax\n" \
" pushl %ebp\n" \
" pushl %edi\n" \

5
arch/x86/kernel/quirks.c
View File

@ -498,15 +498,10 @@ void force_hpet_resume(void)
* See erratum #27 (Misinterpreted MSI Requests May Result in
* Corrupted LPC DMA Data) in AMD Publication #46837,
* "SB700 Family Product Errata", Rev. 1.0, March 2010.
*
* Also force the read back of the CMP register in hpet_next_event()
* to work around the problem that the CMP register write seems to be
* delayed. See hpet_next_event() for details.
*/
static void force_disable_hpet_msi(struct pci_dev *unused)
{
hpet_msi_disable = 1;
hpet_readback_cmp = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,

17
arch/x86/kernel/setup_percpu.c
View File

@ -238,6 +238,15 @@ void __init setup_per_cpu_areas(void)
#ifdef CONFIG_NUMA
per_cpu(x86_cpu_to_node_map, cpu) =
early_per_cpu_map(x86_cpu_to_node_map, cpu);
/*
* Ensure that the boot cpu numa_node is correct when the boot
* cpu is on a node that doesn't have memory installed.
* Also cpu_up() will call cpu_to_node() for APs when
* MEMORY_HOTPLUG is defined, before per_cpu(numa_node) is set
* up later with c_init aka intel_init/amd_init.
* So set them all (boot cpu and all APs).
*/
set_cpu_numa_node(cpu, early_cpu_to_node(cpu));
#endif
#endif
/*
@ -257,14 +266,6 @@ void __init setup_per_cpu_areas(void)
early_per_cpu_ptr(x86_cpu_to_node_map) = NULL;
#endif
#if defined(CONFIG_X86_64) && defined(CONFIG_NUMA)
/*
* make sure boot cpu numa_node is right, when boot cpu is on the
* node that doesn't have mem installed
*/
set_cpu_numa_node(boot_cpu_id, early_cpu_to_node(boot_cpu_id));
#endif
/* Setup node to cpumask map */
setup_node_to_cpumask_map();

2
arch/x86/kvm/mmu.c
View File

@ -2926,7 +2926,7 @@ static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm)
return kvm_mmu_zap_page(kvm, page) + 1;
}
static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
{
struct kvm *kvm;
struct kvm *kvm_freed = NULL;

1
arch/x86/kvm/paging_tmpl.h
View File

@ -342,6 +342,7 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
/* advance table_gfn when emulating 1gb pages with 4k */
if (delta == 0)
table_gfn += PT_INDEX(addr, level);
access &= gw->pte_access;
} else {
direct = 0;
table_gfn = gw->table_gfn[level - 2];

4
arch/x86/kvm/x86.c
View File

@ -1562,7 +1562,7 @@ static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
r = -ENOMEM;
size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
entries = vmalloc(size);
entries = kmalloc(size, GFP_KERNEL);
if (!entries)
goto out;
@ -1581,7 +1581,7 @@ static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
r = n;
out_free:
vfree(entries);
kfree(entries);
out:
return r;
}

1
arch/x86/pci/i386.c
View File

@ -184,6 +184,7 @@ static void __init pcibios_allocate_resources(int pass)
idx, r, disabled, pass);
if (pci_claim_resource(dev, idx) < 0) {
/* We'll assign a new address later */
dev->fw_addr[idx] = r->start;
r->end -= r->start;
r->start = 0;
}

7
arch/x86/pci/mrst.c
View File

@ -66,8 +66,9 @@ static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
devfn, pos, 4, &pcie_cap))
return 0;
if (pcie_cap == 0xffffffff)
return 0;
if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
break;
if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
@ -76,7 +77,7 @@ static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
return pos;
}
pos = pcie_cap >> 20;
pos = PCI_EXT_CAP_NEXT(pcie_cap);
}
return 0;

2
crypto/ablkcipher.c
View File

@ -165,7 +165,7 @@ static inline int ablkcipher_next_slow(struct ablkcipher_request *req,
p = kmalloc(n, GFP_ATOMIC);
if (!p)
ablkcipher_walk_done(req, walk, -ENOMEM);
return ablkcipher_walk_done(req, walk, -ENOMEM);
base = p + 1;

19
drivers/acpi/acpica/evxfevnt.c
View File

@ -70,6 +70,7 @@ acpi_ev_get_gpe_device(struct acpi_gpe_xrupt_info *gpe_xrupt_info,
acpi_status acpi_enable(void)
{
acpi_status status;
int retry;
ACPI_FUNCTION_TRACE(acpi_enable);
@ -98,16 +99,18 @@ acpi_status acpi_enable(void)
/* Sanity check that transition succeeded */
if (acpi_hw_get_mode() != ACPI_SYS_MODE_ACPI) {
ACPI_ERROR((AE_INFO,
"Hardware did not enter ACPI mode"));
return_ACPI_STATUS(AE_NO_HARDWARE_RESPONSE);
for (retry = 0; retry < 30000; ++retry) {
if (acpi_hw_get_mode() == ACPI_SYS_MODE_ACPI) {
if (retry != 0)
ACPI_WARNING((AE_INFO,
"Platform took > %d00 usec to enter ACPI mode", retry));
return_ACPI_STATUS(AE_OK);
}
acpi_os_stall(100); /* 100 usec */
}
ACPI_DEBUG_PRINT((ACPI_DB_INIT,
"Transition to ACPI mode successful\n"));
return_ACPI_STATUS(AE_OK);
ACPI_ERROR((AE_INFO, "Hardware did not enter ACPI mode"));
return_ACPI_STATUS(AE_NO_HARDWARE_RESPONSE);
}
ACPI_EXPORT_SYMBOL(acpi_enable)

8
drivers/acpi/battery.c
View File

@ -868,9 +868,15 @@ static void acpi_battery_remove_fs(struct acpi_device *device)
static void acpi_battery_notify(struct acpi_device *device, u32 event)
{
struct acpi_battery *battery = acpi_driver_data(device);
#ifdef CONFIG_ACPI_SYSFS_POWER
struct device *old;
#endif
if (!battery)
return;
#ifdef CONFIG_ACPI_SYSFS_POWER
old = battery->bat.dev;
#endif
acpi_battery_update(battery);
acpi_bus_generate_proc_event(device, event,
acpi_battery_present(battery));
@ -879,7 +885,7 @@ static void acpi_battery_notify(struct acpi_device *device, u32 event)
acpi_battery_present(battery));
#ifdef CONFIG_ACPI_SYSFS_POWER
/* acpi_battery_update could remove power_supply object */
if (battery->bat.dev)
if (old && battery->bat.dev)
power_supply_changed(&battery->bat);
#endif
}

2
drivers/acpi/blacklist.c
View File

@ -214,7 +214,7 @@ static struct dmi_system_id acpi_osi_dmi_table[] __initdata = {
.ident = "Sony VGN-SR290J",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
DMI_MATCH(DMI_PRODUCT_NAME, "Sony VGN-SR290J"),
DMI_MATCH(DMI_PRODUCT_NAME, "VGN-SR290J"),
},
},
{

2
drivers/acpi/processor_core.c
View File

@ -223,7 +223,7 @@ static bool processor_physically_present(acpi_handle handle)
type = (acpi_type == ACPI_TYPE_DEVICE) ? 1 : 0;
cpuid = acpi_get_cpuid(handle, type, acpi_id);
if (cpuid == -1)
if ((cpuid == -1) && (num_possible_cpus() > 1))
return false;
return true;

10
drivers/acpi/processor_idle.c
View File

@ -76,14 +76,19 @@ static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
module_param(max_cstate, uint, 0000);
static unsigned int nocst __read_mostly;
module_param(nocst, uint, 0000);
static int bm_check_disable __read_mostly;
module_param(bm_check_disable, uint, 0000);
static unsigned int latency_factor __read_mostly = 2;
module_param(latency_factor, uint, 0644);
#ifdef CONFIG_ACPI_PROCFS
static u64 us_to_pm_timer_ticks(s64 t)
{
return div64_u64(t * PM_TIMER_FREQUENCY, 1000000);
}
#endif
/*
* IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
* For now disable this. Probably a bug somewhere else.
@ -763,6 +768,9 @@ static int acpi_idle_bm_check(void)
{
u32 bm_status = 0;
if (bm_check_disable)
return 0;
acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
if (bm_status)
acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
@ -947,7 +955,7 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
if (acpi_idle_suspend)
return(acpi_idle_enter_c1(dev, state));
if (acpi_idle_bm_check()) {
if (!cx->bm_sts_skip && acpi_idle_bm_check()) {
if (dev->safe_state) {
dev->last_state = dev->safe_state;
return dev->safe_state->enter(dev, dev->safe_state);

35
drivers/acpi/sleep.c
View File

@ -81,6 +81,20 @@ static int acpi_sleep_prepare(u32 acpi_state)
#ifdef CONFIG_ACPI_SLEEP
static u32 acpi_target_sleep_state = ACPI_STATE_S0;
/*
* The ACPI specification wants us to save NVS memory regions during hibernation
* and to restore them during the subsequent resume. Windows does that also for
* suspend to RAM. However, it is known that this mechanism does not work on
* all machines, so we allow the user to disable it with the help of the
* 'acpi_sleep=nonvs' kernel command line option.
*/
static bool nvs_nosave;
void __init acpi_nvs_nosave(void)
{
nvs_nosave = true;
}
/*
* ACPI 1.0 wants us to execute _PTS before suspending devices, so we allow the
* user to request that behavior by using the 'acpi_old_suspend_ordering'
@ -197,8 +211,7 @@ static int acpi_suspend_begin(suspend_state_t pm_state)
u32 acpi_state = acpi_suspend_states[pm_state];
int error = 0;
error = suspend_nvs_alloc();
error = nvs_nosave ? 0 : suspend_nvs_alloc();
if (error)
return error;
@ -388,20 +401,6 @@ static struct dmi_system_id __initdata acpisleep_dmi_table[] = {
#endif /* CONFIG_SUSPEND */
#ifdef CONFIG_HIBERNATION
/*
* The ACPI specification wants us to save NVS memory regions during hibernation
* and to restore them during the subsequent resume. However, it is not certain
* if this mechanism is going to work on all machines, so we allow the user to
* disable this mechanism using the 'acpi_sleep=s4_nonvs' kernel command line
* option.
*/
static bool s4_no_nvs;
void __init acpi_s4_no_nvs(void)
{
s4_no_nvs = true;
}
static unsigned long s4_hardware_signature;
static struct acpi_table_facs *facs;
static bool nosigcheck;
@ -415,7 +414,7 @@ static int acpi_hibernation_begin(void)
{
int error;
error = s4_no_nvs ? 0 : suspend_nvs_alloc();
error = nvs_nosave ? 0 : suspend_nvs_alloc();
if (!error) {
acpi_target_sleep_state = ACPI_STATE_S4;
acpi_sleep_tts_switch(acpi_target_sleep_state);
@ -510,7 +509,7 @@ static int acpi_hibernation_begin_old(void)
error = acpi_sleep_prepare(ACPI_STATE_S4);
if (!error) {
if (!s4_no_nvs)
if (!nvs_nosave)
error = suspend_nvs_alloc();
if (!error)
acpi_target_sleep_state = ACPI_STATE_S4;

2
drivers/base/core.c
View File

@ -673,7 +673,7 @@ static struct kobject *get_device_parent(struct device *dev,
*/
if (parent == NULL)
parent_kobj = virtual_device_parent(dev);
else if (parent->class)
else if (parent->class && !dev->class->ns_type)
return &parent->kobj;
else
parent_kobj = &parent->kobj;

13
drivers/char/agp/intel-gtt.c
View File

@ -1216,17 +1216,20 @@ static int intel_i915_get_gtt_size(void)
/* G33's GTT size defined in gmch_ctrl */
pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
case G33_PGETBL_SIZE_1M:
switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
case I830_GMCH_GMS_STOLEN_512:
size = 512;
break;
case I830_GMCH_GMS_STOLEN_1024:
size = 1024;
break;
case G33_PGETBL_SIZE_2M:
size = 2048;
case I830_GMCH_GMS_STOLEN_8192:
size = 8*1024;
break;
default:
dev_info(&agp_bridge->dev->dev,
"unknown page table size 0x%x, assuming 512KB\n",
(gmch_ctrl & G33_PGETBL_SIZE_MASK));
(gmch_ctrl & I830_GMCH_GMS_MASK));
size = 512;
}
} else {

2
drivers/char/sysrq.c
View File

@ -493,7 +493,7 @@ static void __sysrq_put_key_op(int key, struct sysrq_key_op *op_p)
sysrq_key_table[i] = op_p;
}
static void __handle_sysrq(int key, struct tty_struct *tty, int check_mask)
void __handle_sysrq(int key, struct tty_struct *tty, int check_mask)
{
struct sysrq_key_op *op_p;
int orig_log_level;

9
drivers/char/tpm/tpm_tis.c
View File

@ -623,7 +623,14 @@ static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg)
static int tpm_tis_pnp_resume(struct pnp_dev *dev)
{
return tpm_pm_resume(&dev->dev);
struct tpm_chip *chip = pnp_get_drvdata(dev);
int ret;
ret = tpm_pm_resume(&dev->dev);
if (!ret)
tpm_continue_selftest(chip);
return ret;
}
static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = {

2
drivers/clocksource/cs5535-clockevt.c
View File

@ -194,6 +194,6 @@ err_timer:
module_init(cs5535_mfgpt_init);
MODULE_AUTHOR("Andres Salomon <dilinger@collabora.co.uk>");
MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
MODULE_DESCRIPTION("CS5535/CS5536 MFGPT clock event driver");
MODULE_LICENSE("GPL");

12
drivers/cpufreq/cpufreq.c
View File

@ -1077,6 +1077,7 @@ err_out_unregister:
err_unlock_policy:
unlock_policy_rwsem_write(cpu);
free_cpumask_var(policy->related_cpus);
err_free_cpumask:
free_cpumask_var(policy->cpus);
err_free_policy:
@ -1762,17 +1763,8 @@ static int __cpufreq_set_policy(struct cpufreq_policy *data,
dprintk("governor switch\n");
/* end old governor */
if (data->governor) {
/*
* Need to release the rwsem around governor
* stop due to lock dependency between
* cancel_delayed_work_sync and the read lock
* taken in the delayed work handler.
*/
unlock_policy_rwsem_write(data->cpu);
if (data->governor)
__cpufreq_governor(data, CPUFREQ_GOV_STOP);
lock_policy_rwsem_write(data->cpu);
}
/* start new governor */
data->governor = policy->governor;

6
drivers/crypto/talitos.c
View File

@ -1183,10 +1183,14 @@ static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
/* Copy part of this segment */
ignore = skip - offset;
len = miter.length - ignore;
if (boffset + len > buflen)
len = buflen - boffset;
memcpy(buf + boffset, miter.addr + ignore, len);
} else {
/* Copy all of this segment */
/* Copy all of this segment (up to buflen) */
len = miter.length;
if (boffset + len > buflen)
len = buflen - boffset;
memcpy(buf + boffset, miter.addr, len);
}
boffset += len;

2
drivers/edac/Kconfig
View File

@ -209,7 +209,7 @@ config EDAC_I5100
config EDAC_MPC85XX
tristate "Freescale MPC83xx / MPC85xx"
depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || MPC85xx)
depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
help
Support for error detection and correction on the Freescale
MPC8349, MPC8560, MPC8540, MPC8548

2
drivers/edac/i7core_edac.c
View File

@ -1300,7 +1300,7 @@ int i7core_get_onedevice(struct pci_dev **prev, int devno,
if (devno == 0)
return -ENODEV;
i7core_printk(KERN_ERR,
i7core_printk(KERN_INFO,
"Device not found: dev %02x.%d PCI ID %04x:%04x\n",
dev_descr->dev, dev_descr->func,
PCI_VENDOR_ID_INTEL, dev_descr->dev_id);

4
drivers/edac/mpc85xx_edac.c
View File

@ -336,6 +336,7 @@ static struct of_device_id mpc85xx_pci_err_of_match[] = {
},
{},
};
MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match);
static struct of_platform_driver mpc85xx_pci_err_driver = {
.probe = mpc85xx_pci_err_probe,
@ -650,6 +651,7 @@ static struct of_device_id mpc85xx_l2_err_of_match[] = {
{ .compatible = "fsl,p2020-l2-cache-controller", },
{},
};
MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
static struct of_platform_driver mpc85xx_l2_err_driver = {
.probe = mpc85xx_l2_err_probe,
@ -1120,11 +1122,13 @@ static struct of_device_id mpc85xx_mc_err_of_match[] = {
{ .compatible = "fsl,mpc8555-memory-controller", },
{ .compatible = "fsl,mpc8560-memory-controller", },
{ .compatible = "fsl,mpc8568-memory-controller", },
{ .compatible = "fsl,mpc8569-memory-controller", },
{ .compatible = "fsl,mpc8572-memory-controller", },
{ .compatible = "fsl,mpc8349-memory-controller", },
{ .compatible = "fsl,p2020-memory-controller", },
{},
};
MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
static struct of_platform_driver mpc85xx_mc_err_driver = {
.probe = mpc85xx_mc_err_probe,

2
drivers/gpio/cs5535-gpio.c
View File

@ -352,6 +352,6 @@ static void __exit cs5535_gpio_exit(void)
module_init(cs5535_gpio_init);
module_exit(cs5535_gpio_exit);
MODULE_AUTHOR("Andres Salomon <dilinger@collabora.co.uk>");
MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
MODULE_LICENSE("GPL");

7
drivers/gpio/gpiolib.c
View File

@ -893,10 +893,12 @@ EXPORT_SYMBOL_GPL(gpio_sysfs_set_active_low);
void gpio_unexport(unsigned gpio)
{
struct gpio_desc *desc;
int status = -EINVAL;
int status = 0;
if (!gpio_is_valid(gpio))
if (!gpio_is_valid(gpio)) {
status = -EINVAL;
goto done;
}
mutex_lock(&sysfs_lock);
@ -911,7 +913,6 @@ void gpio_unexport(unsigned gpio)
clear_bit(FLAG_EXPORT, &desc->flags);
put_device(dev);
device_unregister(dev);
status = 0;
} else
status = -ENODEV;
}

3
drivers/gpu/drm/i915/i915_debugfs.c
View File

@ -605,6 +605,9 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
case FBC_NOT_TILED:
seq_printf(m, "scanout buffer not tiled");
break;
case FBC_MULTIPLE_PIPES:
seq_printf(m, "multiple pipes are enabled");
break;
default:
seq_printf(m, "unknown reason");
}

2
drivers/gpu/drm/i915/i915_dma.c
View File

@ -1300,7 +1300,7 @@ static void i915_cleanup_compression(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
drm_mm_put_block(dev_priv->compressed_fb);
if (!IS_GM45(dev))
if (dev_priv->compressed_llb)
drm_mm_put_block(dev_priv->compressed_llb);
}

5
drivers/gpu/drm/i915/i915_drv.h
View File

@ -215,6 +215,7 @@ enum no_fbc_reason {
FBC_MODE_TOO_LARGE, /* mode too large for compression */
FBC_BAD_PLANE, /* fbc not supported on plane */
FBC_NOT_TILED, /* buffer not tiled */
FBC_MULTIPLE_PIPES, /* more than one pipe active */
};
enum intel_pch {
@ -222,6 +223,8 @@ enum intel_pch {
PCH_CPT, /* Cougarpoint PCH */
};
#define QUIRK_PIPEA_FORCE (1<<0)
struct intel_fbdev;
typedef struct drm_i915_private {
@ -337,6 +340,8 @@ typedef struct drm_i915_private {
/* PCH chipset type */
enum intel_pch pch_type;
unsigned long quirks;
/* Register state */
bool modeset_on_lid;
u8 saveLBB;

16
drivers/gpu/drm/i915/i915_gem.c
View File

@ -2241,6 +2241,7 @@ i915_gem_object_get_pages(struct drm_gem_object *obj,
page = read_cache_page_gfp(mapping, i,
GFP_HIGHUSER |
__GFP_COLD |
__GFP_RECLAIMABLE |
gfpmask);
if (IS_ERR(page))
goto err_pages;
@ -3646,6 +3647,7 @@ i915_gem_wait_for_pending_flip(struct drm_device *dev,
return ret;
}
int
i915_gem_do_execbuffer(struct drm_device *dev, void *data,
struct drm_file *file_priv,
@ -3793,7 +3795,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
unsigned long long total_size = 0;
int num_fences = 0;
for (i = 0; i < args->buffer_count; i++) {
obj_priv = object_list[i]->driver_private;
obj_priv = to_intel_bo(object_list[i]);
total_size += object_list[i]->size;
num_fences +=
@ -4741,6 +4743,16 @@ i915_gem_load(struct drm_device *dev)
list_add(&dev_priv->mm.shrink_list, &shrink_list);
spin_unlock(&shrink_list_lock);
/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
if (IS_GEN3(dev)) {
u32 tmp = I915_READ(MI_ARB_STATE);
if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
/* arb state is a masked write, so set bit + bit in mask */
tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
I915_WRITE(MI_ARB_STATE, tmp);
}
}
/* Old X drivers will take 0-2 for front, back, depth buffers */
if (!drm_core_check_feature(dev, DRIVER_MODESET))
dev_priv->fence_reg_start = 3;
@ -4977,7 +4989,7 @@ i915_gpu_is_active(struct drm_device *dev)
}
static int
i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
{
drm_i915_private_t *dev_priv, *next_dev;
struct drm_i915_gem_object *obj_priv, *next_obj;

65
drivers/gpu/drm/i915/i915_reg.h
View File

@ -359,6 +359,70 @@
#define LM_BURST_LENGTH 0x00000700
#define LM_FIFO_WATERMARK 0x0000001F
#define MI_ARB_STATE 0x020e4 /* 915+ only */
#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
/* Make render/texture TLB fetches lower priorty than associated data
* fetches. This is not turned on by default
*/
#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
/* Isoch request wait on GTT enable (Display A/B/C streams).
* Make isoch requests stall on the TLB update. May cause
* display underruns (test mode only)
*/
#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
/* Block grant count for isoch requests when block count is
* set to a finite value.
*/
#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
/* Enable render writes to complete in C2/C3/C4 power states.
* If this isn't enabled, render writes are prevented in low
* power states. That seems bad to me.
*/
#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
/* This acknowledges an async flip immediately instead
* of waiting for 2TLB fetches.
*/
#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
/* Enables non-sequential data reads through arbiter
*/
#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
/* Disable FSB snooping of cacheable write cycles from binner/render
* command stream
*/
#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
/* Arbiter time slice for non-isoch streams */
#define MI_ARB_TIME_SLICE_MASK (7 << 5)
#define MI_ARB_TIME_SLICE_1 (0 << 5)
#define MI_ARB_TIME_SLICE_2 (1 << 5)
#define MI_ARB_TIME_SLICE_4 (2 << 5)
#define MI_ARB_TIME_SLICE_6 (3 << 5)
#define MI_ARB_TIME_SLICE_8 (4 << 5)
#define MI_ARB_TIME_SLICE_10 (5 << 5)
#define MI_ARB_TIME_SLICE_14 (6 << 5)
#define MI_ARB_TIME_SLICE_16 (7 << 5)
/* Low priority grace period page size */
#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
/* Disable display A/B trickle feed */
#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
/* Set display plane priority */
#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
#define CACHE_MODE_0 0x02120 /* 915+ only */
#define CM0_MASK_SHIFT 16
#define CM0_IZ_OPT_DISABLE (1<<6)
@ -2805,6 +2869,7 @@
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
#define PANEL_UNLOCK_REGS (0xabcd << 16)
#define EDP_FORCE_VDD (1 << 3)
#define EDP_BLC_ENABLE (1 << 2)
#define PANEL_POWER_RESET (1 << 1)

109
drivers/gpu/drm/i915/intel_display.c
View File

@ -862,8 +862,8 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
intel_clock_t clock;
int max_n;
bool found;
/* approximately equals target * 0.00488 */
int err_most = (target >> 8) + (target >> 10);
/* approximately equals target * 0.00585 */
int err_most = (target >> 8) + (target >> 9);
found = false;
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
@ -1180,8 +1180,12 @@ static void intel_update_fbc(struct drm_crtc *crtc,
struct drm_framebuffer *fb = crtc->fb;
struct intel_framebuffer *intel_fb;
struct drm_i915_gem_object *obj_priv;
struct drm_crtc *tmp_crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int plane = intel_crtc->plane;
int crtcs_enabled = 0;
DRM_DEBUG_KMS("\n");
if (!i915_powersave)
return;
@ -1199,10 +1203,21 @@ static void intel_update_fbc(struct drm_crtc *crtc,
* If FBC is already on, we just have to verify that we can
* keep it that way...
* Need to disable if:
* - more than one pipe is active
* - changing FBC params (stride, fence, mode)
* - new fb is too large to fit in compressed buffer
* - going to an unsupported config (interlace, pixel multiply, etc.)
*/
list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
if (tmp_crtc->enabled)
crtcs_enabled++;
}
DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
if (crtcs_enabled > 1) {
DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
goto out_disable;
}
if (intel_fb->obj->size > dev_priv->cfb_size) {
DRM_DEBUG_KMS("framebuffer too large, disabling "
"compression\n");
@ -1255,7 +1270,7 @@ out_disable:
}
}
static int
int
intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
{
struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
@ -2255,6 +2270,11 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
intel_wait_for_vblank(dev);
}
/* Don't disable pipe A or pipe A PLLs if needed */
if (pipeconf_reg == PIPEACONF &&
(dev_priv->quirks & QUIRK_PIPEA_FORCE))
goto skip_pipe_off;
/* Next, disable display pipes */
temp = I915_READ(pipeconf_reg);
if ((temp & PIPEACONF_ENABLE) != 0) {
@ -2270,7 +2290,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
I915_READ(dpll_reg);
}
skip_pipe_off:
/* Wait for the clocks to turn off. */
udelay(150);
break;
@ -2356,8 +2376,6 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
if (mode->clock * 3 > 27000 * 4)
return MODE_CLOCK_HIGH;
}
drm_mode_set_crtcinfo(adjusted_mode, 0);
return true;
}
@ -3736,6 +3754,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
if (dev_priv->lvds_dither) {
if (HAS_PCH_SPLIT(dev)) {
pipeconf |= PIPE_ENABLE_DITHER;
pipeconf &= ~PIPE_DITHER_TYPE_MASK;
pipeconf |= PIPE_DITHER_TYPE_ST01;
} else
lvds |= LVDS_ENABLE_DITHER;
@ -4412,7 +4431,8 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
DRM_DEBUG_DRIVER("upclocking LVDS\n");
/* Unlock panel regs */
I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
PANEL_UNLOCK_REGS);
dpll &= ~DISPLAY_RATE_SELECT_FPA1;
I915_WRITE(dpll_reg, dpll);
@ -4455,7 +4475,8 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
DRM_DEBUG_DRIVER("downclocking LVDS\n");
/* Unlock panel regs */
I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
PANEL_UNLOCK_REGS);
dpll |= DISPLAY_RATE_SELECT_FPA1;
I915_WRITE(dpll_reg, dpll);
@ -4695,7 +4716,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
struct drm_gem_object *obj;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_unpin_work *work;
unsigned long flags;
unsigned long flags, offset;
int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
int ret, pipesrc;
u32 flip_mask;
@ -4762,19 +4783,23 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
while (I915_READ(ISR) & flip_mask)
;
/* Offset into the new buffer for cases of shared fbs between CRTCs */
offset = obj_priv->gtt_offset;
offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
BEGIN_LP_RING(4);
if (IS_I965G(dev)) {
OUT_RING(MI_DISPLAY_FLIP |
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
OUT_RING(fb->pitch);
OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
OUT_RING(offset | obj_priv->tiling_mode);
pipesrc = I915_READ(pipesrc_reg);
OUT_RING(pipesrc & 0x0fff0fff);
} else {
OUT_RING(MI_DISPLAY_FLIP_I915 |
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
OUT_RING(fb->pitch);
OUT_RING(obj_priv->gtt_offset);
OUT_RING(offset);
OUT_RING(MI_NOOP);
}
ADVANCE_LP_RING();
@ -5506,6 +5531,66 @@ static void intel_init_display(struct drm_device *dev)
}
}
/*
* Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
* resume, or other times. This quirk makes sure that's the case for
* affected systems.
*/
static void quirk_pipea_force (struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
dev_priv->quirks |= QUIRK_PIPEA_FORCE;
DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
}
struct intel_quirk {
int device;
int subsystem_vendor;
int subsystem_device;
void (*hook)(struct drm_device *dev);
};
struct intel_quirk intel_quirks[] = {
/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
{ 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
/* HP Mini needs pipe A force quirk (LP: #322104) */
{ 0x27ae,0x103c, 0x361a, quirk_pipea_force },
/* Thinkpad R31 needs pipe A force quirk */
{ 0x3577, 0x1014, 0x0505, quirk_pipea_force },
/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
{ 0x3577, 0x1014, 0x0513, quirk_pipea_force },
/* ThinkPad X40 needs pipe A force quirk */
/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
/* 855 & before need to leave pipe A & dpll A up */
{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
};
static void intel_init_quirks(struct drm_device *dev)
{
struct pci_dev *d = dev->pdev;
int i;
for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
struct intel_quirk *q = &intel_quirks[i];
if (d->device == q->device &&
(d->subsystem_vendor == q->subsystem_vendor ||
q->subsystem_vendor == PCI_ANY_ID) &&
(d->subsystem_device == q->subsystem_device ||
q->subsystem_device == PCI_ANY_ID))
q->hook(dev);
}
}
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@ -5518,6 +5603,8 @@ void intel_modeset_init(struct drm_device *dev)
dev->mode_config.funcs = (void *)&intel_mode_funcs;
intel_init_quirks(dev);
intel_init_display(dev);
if (IS_I965G(dev)) {

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