MIPS: BMIPS: Make whitespacely correct.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
21b30c00f3
commit
f241265fdc
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@ -27,16 +27,16 @@
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#define cacheop(kva, size, linesize, op) \
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#define cacheop(kva, size, linesize, op) \
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.set noreorder ; \
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.set noreorder ; \
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addu t1, kva, size ; \
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addu t1, kva, size ; \
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subu t2, linesize, 1 ; \
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subu t2, linesize, 1 ; \
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not t2 ; \
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not t2 ; \
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and t0, kva, t2 ; \
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and t0, kva, t2 ; \
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addiu t1, t1, -1 ; \
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addiu t1, t1, -1 ; \
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and t1, t2 ; \
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and t1, t2 ; \
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9: cache op, 0(t0) ; \
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9: cache op, 0(t0) ; \
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bne t0, t1, 9b ; \
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bne t0, t1, 9b ; \
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addu t0, linesize ; \
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addu t0, linesize ; \
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.set reorder ;
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.set reorder ;
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@ -59,13 +59,13 @@
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#define CP0_BRCM_MODE $22, 1
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#define CP0_BRCM_MODE $22, 1
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#define CP0_CONFIG_K0_MASK 7
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#define CP0_CONFIG_K0_MASK 7
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#define CP0_ICACHE_TAG_LO $28
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#define CP0_ICACHE_TAG_LO $28
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#define CP0_ICACHE_DATA_LO $28, 1
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#define CP0_ICACHE_DATA_LO $28, 1
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#define CP0_DCACHE_TAG_LO $28, 2
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#define CP0_DCACHE_TAG_LO $28, 2
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#define CP0_D_SEC_CACHE_DATA_LO $28, 3
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#define CP0_D_SEC_CACHE_DATA_LO $28, 3
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#define CP0_ICACHE_TAG_HI $29
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#define CP0_ICACHE_TAG_HI $29
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#define CP0_ICACHE_DATA_HI $29, 1
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#define CP0_ICACHE_DATA_HI $29, 1
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#define CP0_DCACHE_TAG_HI $29, 2
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#define CP0_DCACHE_TAG_HI $29, 2
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#define CP0_BRCM_MODE_Luc_MASK (1 << 11)
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#define CP0_BRCM_MODE_Luc_MASK (1 << 11)
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#define CP0_BRCM_CONFIG0_CWF_MASK (1 << 20)
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#define CP0_BRCM_CONFIG0_CWF_MASK (1 << 20)
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@ -78,7 +78,7 @@
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#define CP0_BRCM_MODE_BrHIST_SHIFT 20
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#define CP0_BRCM_MODE_BrHIST_SHIFT 20
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/* ZSC L2 Cache Register Access Register Definitions */
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/* ZSC L2 Cache Register Access Register Definitions */
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#define BRCM_ZSC_ALL_REGS_SELECT 0x7 << 24
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#define BRCM_ZSC_ALL_REGS_SELECT 0x7 << 24
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#define BRCM_ZSC_CONFIG_REG 0 << 3
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#define BRCM_ZSC_CONFIG_REG 0 << 3
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#define BRCM_ZSC_REQ_BUFFER_REG 2 << 3
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#define BRCM_ZSC_REQ_BUFFER_REG 2 << 3
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@ -117,9 +117,9 @@
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*/
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*/
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LEAF(size_i_cache)
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LEAF(size_i_cache)
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.set noreorder
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.set noreorder
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mfc0 a0, CP0_CONFIG, 1
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mfc0 a0, CP0_CONFIG, 1
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move t0, a0
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move t0, a0
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/*
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/*
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@ -131,13 +131,13 @@ LEAF(size_i_cache)
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* vi) 0x5 - 0x7: Reserved.
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* vi) 0x5 - 0x7: Reserved.
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*/
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*/
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srl a0, a0, IS_SHIFT
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srl a0, a0, IS_SHIFT
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and a0, a0, IS_MASK
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and a0, a0, IS_MASK
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/* sets per way = (64<<IS) */
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/* sets per way = (64<<IS) */
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li v0, 0x40
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li v0, 0x40
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sllv v0, v0, a0
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sllv v0, v0, a0
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/*
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/*
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* Determine line size
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* Determine line size
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@ -186,17 +186,17 @@ LEAF(size_i_cache)
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*/
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*/
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multu v0, a0 /*multu is interlocked, so no need to insert nops */
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multu v0, a0 /*multu is interlocked, so no need to insert nops */
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mflo v0
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mflo v0
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b 1f
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b 1f
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nop
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nop
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no_i_cache:
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no_i_cache:
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move v0, zero
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move v0, zero
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move v1, zero
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move v1, zero
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1:
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1:
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jr ra
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jr ra
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nop
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nop
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.set reorder
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.set reorder
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END(size_i_cache)
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END(size_i_cache)
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@ -210,9 +210,9 @@ END(size_i_cache)
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*/
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*/
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LEAF(size_d_cache)
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LEAF(size_d_cache)
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.set noreorder
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.set noreorder
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mfc0 a0, CP0_CONFIG, 1
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mfc0 a0, CP0_CONFIG, 1
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move t0, a0
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move t0, a0
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/*
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/*
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@ -224,13 +224,13 @@ LEAF(size_d_cache)
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* vi) 0x5 - 0x7: Reserved.
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* vi) 0x5 - 0x7: Reserved.
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*/
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*/
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srl a0, a0, DS_SHIFT
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srl a0, a0, DS_SHIFT
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and a0, a0, DS_MASK
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and a0, a0, DS_MASK
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/* sets per way = (64<<IS) */
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/* sets per way = (64<<IS) */
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li v0, 0x40
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li v0, 0x40
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sllv v0, v0, a0
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sllv v0, v0, a0
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/*
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/*
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* Determine line size
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* Determine line size
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@ -277,18 +277,18 @@ LEAF(size_d_cache)
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*/
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*/
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multu v0, a0 /*multu is interlocked, so no need to insert nops */
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multu v0, a0 /*multu is interlocked, so no need to insert nops */
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mflo v0
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mflo v0
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b 1f
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b 1f
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nop
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nop
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no_d_cache:
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no_d_cache:
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move v0, zero
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move v0, zero
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move v1, zero
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move v1, zero
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1:
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1:
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jr ra
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jr ra
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nop
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nop
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.set reorder
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.set reorder
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END(size_d_cache)
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END(size_d_cache)
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@ -298,22 +298,22 @@ END(size_d_cache)
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* Arguments: None
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* Arguments: None
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* Returns: None
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* Returns: None
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* Description: Enable I and D caches, initialize I and D-caches, also set
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* Description: Enable I and D caches, initialize I and D-caches, also set
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* hardware delay for d-cache (TP0).
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* hardware delay for d-cache (TP0).
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* Trashes: t0
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* Trashes: t0
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*
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*
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*/
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*/
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.global enable_ID
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.global enable_ID
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.ent enable_ID
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.ent enable_ID
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.set noreorder
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.set noreorder
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enable_ID:
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enable_ID:
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mfc0 t0, CP0_BRCM_CONFIG0
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mfc0 t0, CP0_BRCM_CONFIG0
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or t0, t0, (ICE_MASK | DCE_MASK)
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or t0, t0, (ICE_MASK | DCE_MASK)
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mtc0 t0, CP0_BRCM_CONFIG0
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mtc0 t0, CP0_BRCM_CONFIG0
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jr ra
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jr ra
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nop
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nop
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.end enable_ID
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.end enable_ID
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.set reorder
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.set reorder
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/*
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/*
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@ -326,16 +326,16 @@ enable_ID:
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*/
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*/
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.globl l1_init
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.globl l1_init
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.ent l1_init
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.ent l1_init
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.set noreorder
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.set noreorder
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l1_init:
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l1_init:
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/* save return address */
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/* save return address */
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move t8, ra
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move t8, ra
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/* initialize I and D cache Data and Tag registers. */
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/* initialize I and D cache Data and Tag registers. */
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mtc0 zero, CP0_ICACHE_TAG_LO
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mtc0 zero, CP0_ICACHE_TAG_LO
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mtc0 zero, CP0_ICACHE_TAG_HI
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mtc0 zero, CP0_ICACHE_TAG_HI
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mtc0 zero, CP0_ICACHE_DATA_LO
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mtc0 zero, CP0_ICACHE_DATA_LO
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mtc0 zero, CP0_ICACHE_DATA_HI
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mtc0 zero, CP0_ICACHE_DATA_HI
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mtc0 zero, CP0_DCACHE_TAG_LO
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mtc0 zero, CP0_DCACHE_TAG_LO
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@ -363,13 +363,13 @@ l1_init:
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* set K0 cache mode
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* set K0 cache mode
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*/
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*/
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mfc0 t0, CP0_CONFIG
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mfc0 t0, CP0_CONFIG
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and t0, t0, ~CP0_CONFIG_K0_MASK
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and t0, t0, ~CP0_CONFIG_K0_MASK
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or t0, t0, 3 /* Write Back mode */
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or t0, t0, 3 /* Write Back mode */
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mtc0 t0, CP0_CONFIG
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mtc0 t0, CP0_CONFIG
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/*
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/*
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* Initialize instruction cache.
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* Initialize instruction cache.
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*/
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*/
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li a0, KSEG0
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li a0, KSEG0
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@ -386,21 +386,21 @@ l1_init:
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nop
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nop
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1:
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1:
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/*
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/*
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* Initialize data cache.
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* Initialize data cache.
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*/
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*/
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jal size_d_cache /* v0 = d-cache size, v1 = d-cache line size */
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jal size_d_cache /* v0 = d-cache size, v1 = d-cache line size */
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nop
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nop
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li a0, KSEG0
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li a0, KSEG0
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cacheop(a0, v0, v1, Index_Store_Tag_D)
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cacheop(a0, v0, v1, Index_Store_Tag_D)
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jr t8
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jr t8
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nop
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nop
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.end l1_init
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.end l1_init
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.set reorder
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.set reorder
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/*
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/*
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@ -416,23 +416,23 @@ l1_init:
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LEAF(set_other_config)
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LEAF(set_other_config)
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.set noreorder
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.set noreorder
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/* enable Bus error for I-fetch */
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/* enable Bus error for I-fetch */
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mfc0 t0, CP0_CACHEERR, 0
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mfc0 t0, CP0_CACHEERR, 0
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li t1, 0x4
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li t1, 0x4
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or t0, t1
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or t0, t1
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mtc0 t0, CP0_CACHEERR, 0
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mtc0 t0, CP0_CACHEERR, 0
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/* enable Bus error for Load */
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/* enable Bus error for Load */
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mfc0 t0, CP0_CACHEERR, 1
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mfc0 t0, CP0_CACHEERR, 1
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li t1, 0x4
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li t1, 0x4
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or t0, t1
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or t0, t1
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mtc0 t0, CP0_CACHEERR, 1
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mtc0 t0, CP0_CACHEERR, 1
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/* enable Bus Error for Store */
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/* enable Bus Error for Store */
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mfc0 t0, CP0_CACHEERR, 2
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mfc0 t0, CP0_CACHEERR, 2
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li t1, 0x4
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li t1, 0x4
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or t0, t1
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or t0, t1
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mtc0 t0, CP0_CACHEERR, 2
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mtc0 t0, CP0_CACHEERR, 2
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jr ra
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jr ra
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nop
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nop
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@ -452,7 +452,7 @@ END(set_other_config)
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LEAF(set_branch_pred)
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LEAF(set_branch_pred)
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.set noreorder
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.set noreorder
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mfc0 t0, CP0_BRCM_MODE
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mfc0 t0, CP0_BRCM_MODE
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li t1, ~(CP0_BRCM_MODE_BrPRED_MASK | CP0_BRCM_MODE_BrHIST_MASK )
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li t1, ~(CP0_BRCM_MODE_BrPRED_MASK | CP0_BRCM_MODE_BrHIST_MASK )
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and t0, t0, t1
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and t0, t0, t1
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@ -466,10 +466,10 @@ LEAF(set_branch_pred)
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sll t1, CP0_BRCM_MODE_BrHIST_SHIFT
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sll t1, CP0_BRCM_MODE_BrHIST_SHIFT
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or t0, t0, t1
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or t0, t0, t1
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mtc0 t0, CP0_BRCM_MODE
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mtc0 t0, CP0_BRCM_MODE
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jr ra
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jr ra
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nop
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nop
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.set reorder
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.set reorder
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END(set_branch_pred)
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END(set_branch_pred)
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@ -483,17 +483,17 @@ END(set_branch_pred)
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*/
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*/
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LEAF(set_luc)
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LEAF(set_luc)
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.set noreorder
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.set noreorder
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mfc0 t0, CP0_BRCM_MODE
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mfc0 t0, CP0_BRCM_MODE
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li t1, ~(CP0_BRCM_MODE_Luc_MASK)
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li t1, ~(CP0_BRCM_MODE_Luc_MASK)
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and t0, t0, t1
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and t0, t0, t1
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/* set Luc */
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/* set Luc */
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ori t0, t0, CP0_BRCM_MODE_Luc_MASK
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ori t0, t0, CP0_BRCM_MODE_Luc_MASK
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mtc0 t0, CP0_BRCM_MODE
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mtc0 t0, CP0_BRCM_MODE
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jr ra
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jr ra
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nop
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nop
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.set reorder
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.set reorder
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END(set_luc)
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END(set_luc)
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/*
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/*
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@ -506,19 +506,19 @@ END(set_luc)
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*/
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*/
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LEAF(set_cwf_tse)
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LEAF(set_cwf_tse)
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.set noreorder
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.set noreorder
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mfc0 t0, CP0_BRCM_CONFIG0
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mfc0 t0, CP0_BRCM_CONFIG0
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li t1, (CP0_BRCM_CONFIG0_CWF_MASK | CP0_BRCM_CONFIG0_TSE_MASK)
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li t1, (CP0_BRCM_CONFIG0_CWF_MASK | CP0_BRCM_CONFIG0_TSE_MASK)
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or t0, t0, t1
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or t0, t0, t1
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mtc0 t0, CP0_BRCM_CONFIG0
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mtc0 t0, CP0_BRCM_CONFIG0
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jr ra
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jr ra
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nop
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nop
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.set reorder
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.set reorder
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END(set_cwf_tse)
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END(set_cwf_tse)
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/*
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/*
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* Function: set_clock_ratio
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* Function: set_clock_ratio
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* Arguments: set clock ratio specified by a0
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* Arguments: set clock ratio specified by a0
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* Returns: None
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* Returns: None
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* Description:
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* Description:
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* Trashes: v0, v1, a0, a1
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* Trashes: v0, v1, a0, a1
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@ -529,56 +529,56 @@ END(set_cwf_tse)
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LEAF(set_clock_ratio)
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LEAF(set_clock_ratio)
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.set noreorder
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.set noreorder
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mfc0 t0, CP0_BRCM_MODE
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mfc0 t0, CP0_BRCM_MODE
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li t1, ~(CP0_BRCM_MODE_SET_MASK | CP0_BRCM_MODE_ClkRATIO_MASK)
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li t1, ~(CP0_BRCM_MODE_SET_MASK | CP0_BRCM_MODE_ClkRATIO_MASK)
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and t0, t0, t1
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and t0, t0, t1
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li t1, CP0_BRCM_MODE_SET_MASK
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li t1, CP0_BRCM_MODE_SET_MASK
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or t0, t0, t1
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or t0, t0, t1
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or t0, t0, a0
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or t0, t0, a0
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mtc0 t0, CP0_BRCM_MODE
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mtc0 t0, CP0_BRCM_MODE
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jr ra
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jr ra
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nop
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nop
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.set reorder
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.set reorder
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END(set_clock_ratio)
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END(set_clock_ratio)
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/*
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/*
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* Function: set_zephyr
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* Function: set_zephyr
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* Arguments: None
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* Arguments: None
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* Returns: None
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* Returns: None
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* Description: Set any zephyr bits
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* Description: Set any zephyr bits
|
||||||
* Trashes: t0 & t1
|
* Trashes: t0 & t1
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
LEAF(set_zephyr)
|
LEAF(set_zephyr)
|
||||||
.set noreorder
|
.set noreorder
|
||||||
|
|
||||||
/* enable read/write of CP0 #22 sel. 8 */
|
/* enable read/write of CP0 #22 sel. 8 */
|
||||||
li t0, 0x5a455048
|
li t0, 0x5a455048
|
||||||
.word 0x4088b00f /* mtc0 t0, $22, 15 */
|
.word 0x4088b00f /* mtc0 t0, $22, 15 */
|
||||||
|
|
||||||
.word 0x4008b008 /* mfc0 t0, $22, 8 */
|
.word 0x4008b008 /* mfc0 t0, $22, 8 */
|
||||||
li t1, 0x09008000 /* turn off pref, jtb */
|
li t1, 0x09008000 /* turn off pref, jtb */
|
||||||
or t0, t0, t1
|
or t0, t0, t1
|
||||||
.word 0x4088b008 /* mtc0 t0, $22, 8 */
|
.word 0x4088b008 /* mtc0 t0, $22, 8 */
|
||||||
sync
|
sync
|
||||||
|
|
||||||
/* disable read/write of CP0 #22 sel 8 */
|
/* disable read/write of CP0 #22 sel 8 */
|
||||||
li t0, 0x0
|
li t0, 0x0
|
||||||
.word 0x4088b00f /* mtc0 t0, $22, 15 */
|
.word 0x4088b00f /* mtc0 t0, $22, 15 */
|
||||||
|
|
||||||
|
|
||||||
jr ra
|
jr ra
|
||||||
nop
|
nop
|
||||||
.set reorder
|
.set reorder
|
||||||
|
|
||||||
END(set_zephyr)
|
END(set_zephyr)
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Function: set_llmb
|
* Function: set_llmb
|
||||||
* Arguments: a0=0 disable llmb, a0=1 enables llmb
|
* Arguments: a0=0 disable llmb, a0=1 enables llmb
|
||||||
* Returns: None
|
* Returns: None
|
||||||
* Description:
|
* Description:
|
||||||
* Trashes: t0, t1, t2
|
* Trashes: t0, t1, t2
|
||||||
*
|
*
|
||||||
* pseudo code:
|
* pseudo code:
|
||||||
*
|
*
|
||||||
|
@ -607,7 +607,7 @@ svlmb:
|
||||||
cache 0xb, 0x0(t2)
|
cache 0xb, 0x0(t2)
|
||||||
sync
|
sync
|
||||||
|
|
||||||
jr ra
|
jr ra
|
||||||
nop
|
nop
|
||||||
.set reorder
|
.set reorder
|
||||||
|
|
||||||
|
@ -623,7 +623,7 @@ END(set_llmb)
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
.globl core_init
|
.globl core_init
|
||||||
.ent core_init
|
.ent core_init
|
||||||
.set noreorder
|
.set noreorder
|
||||||
core_init:
|
core_init:
|
||||||
move t8, ra
|
move t8, ra
|
||||||
|
@ -639,8 +639,8 @@ core_init:
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* set low latency memory bus */
|
/* set low latency memory bus */
|
||||||
li a0, 1
|
li a0, 1
|
||||||
bal set_llmb
|
bal set_llmb
|
||||||
nop
|
nop
|
||||||
|
|
||||||
/* set branch prediction (TP0 only) */
|
/* set branch prediction (TP0 only) */
|
||||||
|
@ -652,7 +652,7 @@ core_init:
|
||||||
nop
|
nop
|
||||||
|
|
||||||
/* set CWF and TSE */
|
/* set CWF and TSE */
|
||||||
bal set_cwf_tse
|
bal set_cwf_tse
|
||||||
nop
|
nop
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -676,44 +676,44 @@ core_init:
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Function: clear_jump_target_buffer
|
* Function: clear_jump_target_buffer
|
||||||
* Arguments: None
|
* Arguments: None
|
||||||
* Returns: None
|
* Returns: None
|
||||||
* Description:
|
* Description:
|
||||||
* Trashes: t0, t1, t2
|
* Trashes: t0, t1, t2
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
#define RESET_CALL_RETURN_STACK_THIS_THREAD (0x06<<16)
|
#define RESET_CALL_RETURN_STACK_THIS_THREAD (0x06<<16)
|
||||||
#define RESET_JUMP_TARGET_BUFFER_THIS_THREAD (0x04<<16)
|
#define RESET_JUMP_TARGET_BUFFER_THIS_THREAD (0x04<<16)
|
||||||
#define JTB_CS_CNTL_MASK (0xFF<<16)
|
#define JTB_CS_CNTL_MASK (0xFF<<16)
|
||||||
|
|
||||||
.globl clear_jump_target_buffer
|
.globl clear_jump_target_buffer
|
||||||
.ent clear_jump_target_buffer
|
.ent clear_jump_target_buffer
|
||||||
.set noreorder
|
.set noreorder
|
||||||
clear_jump_target_buffer:
|
clear_jump_target_buffer:
|
||||||
|
|
||||||
mfc0 t0, $22, 2
|
mfc0 t0, $22, 2
|
||||||
nop
|
nop
|
||||||
nop
|
nop
|
||||||
|
|
||||||
li t1, ~JTB_CS_CNTL_MASK
|
li t1, ~JTB_CS_CNTL_MASK
|
||||||
and t0, t0, t1
|
and t0, t0, t1
|
||||||
li t2, RESET_CALL_RETURN_STACK_THIS_THREAD
|
li t2, RESET_CALL_RETURN_STACK_THIS_THREAD
|
||||||
or t0, t0, t2
|
or t0, t0, t2
|
||||||
mtc0 t0, $22, 2
|
mtc0 t0, $22, 2
|
||||||
nop
|
nop
|
||||||
nop
|
nop
|
||||||
|
|
||||||
and t0, t0, t1
|
and t0, t0, t1
|
||||||
li t2, RESET_JUMP_TARGET_BUFFER_THIS_THREAD
|
li t2, RESET_JUMP_TARGET_BUFFER_THIS_THREAD
|
||||||
or t0, t0, t2
|
or t0, t0, t2
|
||||||
mtc0 t0, $22, 2
|
mtc0 t0, $22, 2
|
||||||
nop
|
nop
|
||||||
nop
|
nop
|
||||||
jr ra
|
jr ra
|
||||||
nop
|
nop
|
||||||
|
|
||||||
.end clear_jump_target_buffer
|
.end clear_jump_target_buffer
|
||||||
.set reorder
|
.set reorder
|
||||||
/*
|
/*
|
||||||
* Function: bmips_cache_init
|
* Function: bmips_cache_init
|
||||||
* Arguments: None
|
* Arguments: None
|
||||||
|
@ -724,11 +724,11 @@ clear_jump_target_buffer:
|
||||||
*/
|
*/
|
||||||
.globl bmips_5xxx_init
|
.globl bmips_5xxx_init
|
||||||
.ent bmips_5xxx_init
|
.ent bmips_5xxx_init
|
||||||
.set noreorder
|
.set noreorder
|
||||||
bmips_5xxx_init:
|
bmips_5xxx_init:
|
||||||
|
|
||||||
/* save return address and A0 */
|
/* save return address and A0 */
|
||||||
move t7, ra
|
move t7, ra
|
||||||
move t5, a0
|
move t5, a0
|
||||||
|
|
||||||
jal l1_init
|
jal l1_init
|
||||||
|
@ -740,14 +740,14 @@ bmips_5xxx_init:
|
||||||
jal clear_jump_target_buffer
|
jal clear_jump_target_buffer
|
||||||
nop
|
nop
|
||||||
|
|
||||||
mtc0 zero, CP0_CAUSE
|
mtc0 zero, CP0_CAUSE
|
||||||
|
|
||||||
move a0, t5
|
move a0, t5
|
||||||
jr t7
|
jr t7
|
||||||
nop
|
nop
|
||||||
|
|
||||||
.end bmips_5xxx_init
|
.end bmips_5xxx_init
|
||||||
.set reorder
|
.set reorder
|
||||||
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
Loading…
Reference in New Issue