MIPS: New macro smp_mb__before_llsc.
Replace some instances of smp_llsc_mb() with a new macro smp_mb__before_llsc(). It is used before ll/sc sequences that are documented as needing write barrier semantics. The default implementation of smp_mb__before_llsc() is just smp_llsc_mb(), so there are no changes in semantics. Also simplify definition of smp_mb(), smp_rmb(), and smp_wmb() to be just barrier() in the non-SMP case. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/851/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -137,7 +137,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
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{
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int result;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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int temp;
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@ -189,7 +189,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
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{
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int result;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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int temp;
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@ -249,7 +249,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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{
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int result;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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int temp;
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@ -516,7 +516,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
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{
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long result;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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long temp;
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@ -568,7 +568,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
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{
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long result;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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long temp;
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@ -628,7 +628,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
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{
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long result;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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long temp;
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@ -788,9 +788,9 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
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* atomic*_return operations are serializing but not the non-*_return
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* versions.
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*/
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#define smp_mb__before_atomic_dec() smp_llsc_mb()
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#define smp_mb__before_atomic_dec() smp_mb__before_llsc()
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#define smp_mb__after_atomic_dec() smp_llsc_mb()
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#define smp_mb__before_atomic_inc() smp_llsc_mb()
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#define smp_mb__before_atomic_inc() smp_mb__before_llsc()
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#define smp_mb__after_atomic_inc() smp_llsc_mb()
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#include <asm-generic/atomic-long.h>
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@ -131,23 +131,26 @@
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#endif /* !CONFIG_CPU_HAS_WB */
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#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
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#define __WEAK_ORDERING_MB " sync \n"
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#define smp_mb() __asm__ __volatile__("sync" : : :"memory")
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#define smp_rmb() __asm__ __volatile__("sync" : : :"memory")
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#define smp_wmb() __asm__ __volatile__("sync" : : :"memory")
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#else
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#define __WEAK_ORDERING_MB " \n"
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#endif
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#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
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#define __WEAK_LLSC_MB " sync \n"
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#else
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#define __WEAK_LLSC_MB " \n"
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#endif
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#define smp_mb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
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#define smp_rmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
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#define smp_wmb() __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
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#define set_mb(var, value) \
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do { var = value; smp_mb(); } while (0)
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#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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#define smp_mb__before_llsc() smp_llsc_mb()
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#endif /* __ASM_BARRIER_H */
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@ -42,7 +42,7 @@
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/*
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* clear_bit() doesn't provide any barrier for the compiler.
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*/
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#define smp_mb__before_clear_bit() smp_llsc_mb()
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#define smp_mb__before_clear_bit() smp_mb__before_llsc()
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#define smp_mb__after_clear_bit() smp_llsc_mb()
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/*
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@ -258,7 +258,7 @@ static inline int test_and_set_bit(unsigned long nr,
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unsigned short bit = nr & SZLONG_MASK;
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unsigned long res;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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@ -395,7 +395,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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unsigned short bit = nr & SZLONG_MASK;
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unsigned long res;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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@ -485,7 +485,7 @@ static inline int test_and_change_bit(unsigned long nr,
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unsigned short bit = nr & SZLONG_MASK;
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unsigned long res;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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@ -72,14 +72,14 @@
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*/
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extern void __cmpxchg_called_with_bad_pointer(void);
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#define __cmpxchg(ptr, old, new, barrier) \
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#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier) \
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({ \
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__typeof__(ptr) __ptr = (ptr); \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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__typeof__(*(ptr)) __res = 0; \
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\
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barrier; \
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pre_barrier; \
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\
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switch (sizeof(*(__ptr))) { \
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case 4: \
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@ -96,13 +96,13 @@ extern void __cmpxchg_called_with_bad_pointer(void);
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break; \
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} \
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\
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barrier; \
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post_barrier; \
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\
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__res; \
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})
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#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
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#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, )
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#define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
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#define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new, , )
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#define cmpxchg64(ptr, o, n) \
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({ \
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@ -138,7 +138,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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int tmp;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__ (
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@ -305,7 +305,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned int tmp;
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smp_llsc_mb();
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smp_mb__before_llsc();
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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@ -95,6 +95,8 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
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{
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__u32 retval;
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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unsigned long dummy;
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@ -147,6 +149,8 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
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{
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__u64 retval;
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smp_mb__before_llsc();
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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unsigned long dummy;
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