clk: sunxi-ng: a83t: Fix audio PLL divider offset
The divider of the audio PLL has an offset of 1. Fix this in the driver. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -80,7 +80,7 @@ static struct ccu_nm pll_audio_clk = {
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.enable = BIT(31),
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.lock = BIT(2),
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.n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
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.m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0),
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.m = _SUNXI_CCU_DIV(0, 6),
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.common = {
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.reg = SUN8I_A83T_PLL_AUDIO_REG,
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.lock_reg = CCU_SUN8I_A83T_LOCK_REG,
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