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ARM: clean up cache handling in platform code 

We have a handy macro to replace open coded __cpuc_flush_dcache_area(()
and outer_clean_range() sequences. Let's use it. No functional change.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Nicolas Pitre 2013-12-05 14:26:16 -05:00 committed by Olof Johansson
parent bc34eb53ab
commit f45913fde0
7 changed files with 7 additions and 14 deletions
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3
arch/arm/mach-exynos/platsmp.c
View File

@ -64,8 +64,7 @@ static void write_pen_release(int val)
{
pen_release = val;
smp_wmb();
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
sync_cache_w(&pen_release);
}
static void __iomem *scu_base_addr(void)

3
arch/arm/mach-imx/platsmp.c
View File

@ -92,8 +92,7 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
* secondary cores when booting them.
*/
asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
__cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg));
outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1));
sync_cache_w(&g_diag_reg);
}
struct smp_operations imx_smp_ops __initdata = {

3
arch/arm/mach-msm/platsmp.c
View File

@ -99,8 +99,7 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
* "cpu" is Linux's internal ID.
*/
pen_release = cpu_logical_map(cpu);
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
sync_cache_w(&pen_release);
/*
* Send the secondary CPU a soft interrupt, thereby causing

3
arch/arm/mach-prima2/platsmp.c
View File

@ -106,8 +106,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
* "cpu" is Linux's internal ID.
*/
pen_release = cpu_logical_map(cpu);
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
sync_cache_w(&pen_release);
/*
* Send the secondary CPU SEV, thereby causing the boot monitor to read

3
arch/arm/mach-sti/platsmp.c
View File

@ -31,8 +31,7 @@ static void write_pen_release(int val)
{
pen_release = val;
smp_wmb();
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
sync_cache_w(&pen_release);
}
static DEFINE_SPINLOCK(boot_lock);

3
arch/arm/mach-ux500/platsmp.c
View File

@ -38,8 +38,7 @@ static void write_pen_release(int val)
{
pen_release = val;
smp_wmb();
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
sync_cache_w(&pen_release);
}
static void __iomem *scu_base_addr(void)

3
arch/arm/plat-versatile/platsmp.c
View File

@ -27,8 +27,7 @@ static void write_pen_release(int val)
{
pen_release = val;
smp_wmb();
__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
sync_cache_w(&pen_release);
}
static DEFINE_SPINLOCK(boot_lock);