serial: sh-sci: Prepare for multiple sampling clock sources
Refactor the clock and baud rate parameter code to ease adding support for multiple sampling clock sources. sci_scbrr_calc() now returns the bit rate error, so it can be compared to the bit rate error using other sampling clock sources. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Geert Uytterhoeven
parent
9ed44bb209
commit
f4998e55b8
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@ -2,6 +2,7 @@
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* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
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*
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* Copyright (C) 2002 - 2011 Paul Mundt
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* Copyright (C) 2015 Glider bvba
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* Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
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*
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* based off of the old drivers/char/sh-sci.c by:
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@ -76,6 +77,11 @@ enum {
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((port)->irqs[SCIx_ERI_IRQ] && \
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((port)->irqs[SCIx_RXI_IRQ] < 0))
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enum SCI_CLKS {
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SCI_FCK, /* Functional Clock */
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SCI_NUM_CLKS
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};
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struct sci_port {
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struct uart_port port;
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@ -92,8 +98,9 @@ struct sci_port {
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struct timer_list break_timer;
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int break_flag;
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/* Function clock */
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struct clk *fclk;
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/* Clocks */
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struct clk *clks[SCI_NUM_CLKS];
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unsigned long clk_rates[SCI_NUM_CLKS];
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int irqs[SCIx_NR_IRQS];
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char *irqstr[SCIx_NR_IRQS];
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@ -496,17 +503,24 @@ static int sci_probe_regmap(struct plat_sci_port *cfg)
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static void sci_port_enable(struct sci_port *sci_port)
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{
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unsigned int i;
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if (!sci_port->port.dev)
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return;
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pm_runtime_get_sync(sci_port->port.dev);
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clk_prepare_enable(sci_port->fclk);
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sci_port->port.uartclk = clk_get_rate(sci_port->fclk);
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for (i = 0; i < SCI_NUM_CLKS; i++) {
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clk_prepare_enable(sci_port->clks[i]);
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sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
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}
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sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
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}
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static void sci_port_disable(struct sci_port *sci_port)
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{
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unsigned int i;
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if (!sci_port->port.dev)
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return;
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@ -518,7 +532,8 @@ static void sci_port_disable(struct sci_port *sci_port)
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del_timer_sync(&sci_port->break_timer);
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sci_port->break_flag = 0;
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clk_disable_unprepare(sci_port->fclk);
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for (i = SCI_NUM_CLKS; i-- > 0; )
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clk_disable_unprepare(sci_port->clks[i]);
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pm_runtime_put_sync(sci_port->port.dev);
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}
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@ -1657,6 +1672,7 @@ static int sci_notifier(struct notifier_block *self,
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{
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struct sci_port *sci_port;
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unsigned long flags;
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unsigned int i;
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sci_port = container_of(self, struct sci_port, freq_transition);
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@ -1664,7 +1680,9 @@ static int sci_notifier(struct notifier_block *self,
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struct uart_port *port = &sci_port->port;
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spin_lock_irqsave(&port->lock, flags);
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port->uartclk = clk_get_rate(sci_port->fclk);
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for (i = 0; i < SCI_NUM_CLKS; i++)
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sci_port->clk_rates[i] =
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clk_get_rate(sci_port->clks[i]);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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@ -1907,11 +1925,12 @@ static void sci_shutdown(struct uart_port *port)
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}
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/* calculate sample rate, BRR, and clock select */
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static void sci_scbrr_calc(struct sci_port *s, unsigned int bps,
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unsigned long freq, int *brr, unsigned int *srr,
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unsigned int *cks)
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static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
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unsigned int *brr, unsigned int *srr,
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unsigned int *cks)
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{
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unsigned int min_sr, max_sr, shift, sr, br, prediv, scrate, c;
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unsigned long freq = s->clk_rates[SCI_FCK];
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int err, min_err = INT_MAX;
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if (s->sampling_rate) {
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@ -1977,6 +1996,7 @@ static void sci_scbrr_calc(struct sci_port *s, unsigned int bps,
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found:
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dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
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min_err, *brr, *srr + 1, *cks);
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return min_err;
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}
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static void sci_reset(struct uart_port *port)
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@ -1998,11 +2018,14 @@ static void sci_reset(struct uart_port *port)
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static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int baud, smr_val = 0, scr_val = 0, i;
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unsigned int brr = 255, cks = 0, srr = 15;
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unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
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struct sci_port *s = to_sci_port(port);
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const struct plat_sci_reg *reg;
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unsigned int baud, smr_val = 0, max_baud, cks = 0;
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int t = -1;
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unsigned int srr = 15;
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int min_err = INT_MAX, err;
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unsigned long max_freq = 0;
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int best_clk = -1;
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if ((termios->c_cflag & CSIZE) == CS7)
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smr_val |= SCSMR_CHR;
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@ -2021,35 +2044,64 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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* that the previous boot loader has enabled required clocks and
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* setup the baud rate generator hardware for us already.
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*/
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if (port->uartclk)
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max_baud = port->uartclk / max(s->sampling_rate, 8U);
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else
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max_baud = 115200;
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if (!port->uartclk) {
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baud = uart_get_baud_rate(port, termios, old, 0, 115200);
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goto done;
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}
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baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
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if (likely(baud && port->uartclk))
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sci_scbrr_calc(s, baud, port->uartclk, &t, &srr, &cks);
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for (i = 0; i < SCI_NUM_CLKS; i++)
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max_freq = max(max_freq, s->clk_rates[i]);
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baud = uart_get_baud_rate(port, termios, old, 0,
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max_freq / max(s->sampling_rate, 8U));
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if (!baud)
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goto done;
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/*
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* There can be multiple sources for the sampling clock. Find the one
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* that gives us the smallest deviation from the desired baud rate.
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*/
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/* Divided Functional Clock using standard Bit Rate Register */
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err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
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if (abs(err) < abs(min_err)) {
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best_clk = SCI_FCK;
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min_err = err;
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brr = brr1;
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srr = srr1;
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cks = cks1;
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}
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done:
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if (best_clk >= 0)
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dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
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s->clks[best_clk], baud, min_err);
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sci_port_enable(s);
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sci_reset(port);
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smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
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uart_update_timeout(port, termios->c_cflag, baud);
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dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
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__func__, smr_val, cks, t, s->cfg->scscr);
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if (t >= 0) {
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serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
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serial_port_out(port, SCBRR, t);
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reg = sci_getreg(port, HSSRR);
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if (reg->size)
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serial_port_out(port, HSSRR, srr | HSCIF_SRE);
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udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
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} else
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if (best_clk >= 0) {
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smr_val |= cks;
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dev_dbg(port->dev, "SMR 0x%x BRR %u SRR %u\n", smr_val, brr,
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srr);
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serial_port_out(port, SCSMR, smr_val);
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serial_port_out(port, SCBRR, brr);
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if (sci_getreg(port, HSSRR)->size)
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serial_port_out(port, HSSRR, srr | HSCIF_SRE);
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/* Wait one bit interval */
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udelay((1000000 + (baud - 1)) / baud);
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} else {
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/* Don't touch the bit rate configuration */
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scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
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smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
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dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
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serial_port_out(port, SCSCR, scr_val);
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serial_port_out(port, SCSMR, smr_val);
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}
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sci_init_pins(port, termios->c_cflag);
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@ -2074,7 +2126,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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serial_port_out(port, SCFCR, ctrl);
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}
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serial_port_out(port, SCSCR, s->cfg->scscr);
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scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
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dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
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serial_port_out(port, SCSCR, scr_val);
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#ifdef CONFIG_SERIAL_SH_SCI_DMA
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/*
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@ -2266,38 +2320,58 @@ static struct uart_ops sci_uart_ops = {
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static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
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{
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/* Get the SCI functional clock. It's called "fck" on ARM. */
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sci_port->fclk = devm_clk_get(dev, "fck");
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if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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if (!IS_ERR(sci_port->fclk))
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return 0;
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const char *clk_names[] = {
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[SCI_FCK] = "fck",
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};
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struct clk *clk;
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unsigned int i;
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/*
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* But it used to be called "sci_ick", and we need to maintain DT
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* backward compatibility.
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*/
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sci_port->fclk = devm_clk_get(dev, "sci_ick");
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if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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if (!IS_ERR(sci_port->fclk))
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return 0;
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for (i = 0; i < SCI_NUM_CLKS; i++) {
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clk = devm_clk_get(dev, clk_names[i]);
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if (PTR_ERR(clk) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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/* SH has historically named the clock "sci_fck". */
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sci_port->fclk = devm_clk_get(dev, "sci_fck");
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if (!IS_ERR(sci_port->fclk))
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return 0;
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if (IS_ERR(clk) && i == SCI_FCK) {
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/*
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* "fck" used to be called "sci_ick", and we need to
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* maintain DT backward compatibility.
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*/
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clk = devm_clk_get(dev, "sci_ick");
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if (PTR_ERR(clk) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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/*
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* Not all SH platforms declare a clock lookup entry for SCI devices,
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* in which case we need to get the global "peripheral_clk" clock.
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*/
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sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
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if (!IS_ERR(sci_port->fclk))
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return 0;
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if (!IS_ERR(clk))
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goto found;
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dev_err(dev, "failed to get functional clock\n");
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return PTR_ERR(sci_port->fclk);
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/* SH has historically named the clock "sci_fck". */
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clk = devm_clk_get(dev, "sci_fck");
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if (!IS_ERR(clk))
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goto found;
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/*
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* Not all SH platforms declare a clock lookup entry
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* for SCI devices, in which case we need to get the
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* global "peripheral_clk" clock.
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*/
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clk = devm_clk_get(dev, "peripheral_clk");
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if (!IS_ERR(clk))
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goto found;
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dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
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PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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found:
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if (IS_ERR(clk))
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dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
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PTR_ERR(clk));
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else
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dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
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clk, clk);
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sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
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}
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return 0;
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}
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static int sci_init_single(struct platform_device *dev,
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