Staging: agnx: Fixup pci.c checkpatch warnings
Signed-off-by: Erik Andrén <erik.andren@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Erik Andrén
Greg Kroah-Hartman
parent
b6da26e017
commit
f58e12e4f8
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@ -39,34 +39,34 @@ static inline void agnx_interrupt_ack(struct agnx_priv *priv, u32 *reason)
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void __iomem *ctl = priv->ctl;
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u32 reg;
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if ( *reason & AGNX_STAT_RX ) {
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if (*reason & AGNX_STAT_RX) {
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/* Mark complete RX */
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reg = ioread32(ctl + AGNX_CIR_RXCTL);
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reg |= 0x4;
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iowrite32(reg, ctl + AGNX_CIR_RXCTL);
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/* disable Rx interrupt */
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}
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if ( *reason & AGNX_STAT_TX ) {
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if (*reason & AGNX_STAT_TX) {
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reg = ioread32(ctl + AGNX_CIR_TXDCTL);
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if (reg & 0x4) {
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iowrite32(reg, ctl + AGNX_CIR_TXDCTL);
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*reason |= AGNX_STAT_TXD;
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}
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reg = ioread32(ctl + AGNX_CIR_TXMCTL);
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reg = ioread32(ctl + AGNX_CIR_TXMCTL);
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if (reg & 0x4) {
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iowrite32(reg, ctl + AGNX_CIR_TXMCTL);
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*reason |= AGNX_STAT_TXM;
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}
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}
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if ( *reason & AGNX_STAT_X ) {
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/* reg = ioread32(ctl + AGNX_INT_STAT); */
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/* iowrite32(reg, ctl + AGNX_INT_STAT); */
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/* /\* FIXME reinit interrupt mask *\/ */
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/* reg = 0xc390bf9 & ~IRQ_TX_BEACON; */
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/* reg &= ~IRQ_TX_DISABLE; */
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/* iowrite32(reg, ctl + AGNX_INT_MASK); */
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/* iowrite32(0x800, ctl + AGNX_CIR_BLKCTL); */
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}
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/* if (*reason & AGNX_STAT_X) {
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reg = ioread32(ctl + AGNX_INT_STAT);
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iowrite32(reg, ctl + AGNX_INT_STAT);
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/* FIXME reinit interrupt mask *\/
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reg = 0xc390bf9 & ~IRQ_TX_BEACON;
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reg &= ~IRQ_TX_DISABLE;
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iowrite32(reg, ctl + AGNX_INT_MASK);
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iowrite32(0x800, ctl + AGNX_CIR_BLKCTL);
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} */
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} /* agnx_interrupt_ack */
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static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
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@ -79,7 +79,7 @@ static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
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spin_lock(&priv->lock);
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// printk(KERN_ERR PFX "Get a interrupt %s\n", __func__);
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/* printk(KERN_ERR PFX "Get a interrupt %s\n", __func__); */
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if (priv->init_status != AGNX_START)
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goto out;
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@ -92,7 +92,7 @@ static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
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ret = IRQ_HANDLED;
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priv->irq_status = ioread32(ctl + AGNX_INT_STAT);
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// printk(PFX "Interrupt reason is 0x%x\n", irq_reason);
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/* printk(PFX "Interrupt reason is 0x%x\n", irq_reason); */
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/* Make sure the txm and txd flags don't conflict with other unknown
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interrupt flag, maybe is not necessary */
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irq_reason &= 0xF;
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@ -101,13 +101,13 @@ static irqreturn_t agnx_interrupt_handler(int irq, void *dev_id)
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/* TODO Make sure the card finished initialized */
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agnx_interrupt_ack(priv, &irq_reason);
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if ( irq_reason & AGNX_STAT_RX )
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if (irq_reason & AGNX_STAT_RX)
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handle_rx_irq(priv);
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if ( irq_reason & AGNX_STAT_TXD )
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if (irq_reason & AGNX_STAT_TXD)
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handle_txd_irq(priv);
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if ( irq_reason & AGNX_STAT_TXM )
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if (irq_reason & AGNX_STAT_TXM)
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handle_txm_irq(priv);
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if ( irq_reason & AGNX_STAT_X )
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if (irq_reason & AGNX_STAT_X)
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handle_other_irq(priv);
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enable_rx_interrupt(priv);
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@ -171,7 +171,7 @@ static int agnx_alloc_rings(struct agnx_priv *priv)
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len = priv->rx.size + priv->txm.size + priv->txd.size;
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// priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_KERNEL);
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/* priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_KERNEL); */
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priv->rx.info = kzalloc(sizeof(struct agnx_info) * len, GFP_ATOMIC);
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if (!priv->rx.info)
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return -ENOMEM;
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@ -210,28 +210,27 @@ static void rings_free(struct agnx_priv *priv)
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#if 0
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static void agnx_periodic_work_handler(struct work_struct *work)
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{
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struct agnx_priv *priv = container_of(work, struct agnx_priv,
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periodic_work.work);
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// unsigned long flags;
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struct agnx_priv *priv = container_of(work, struct agnx_priv, periodic_work.work);
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/* unsigned long flags; */
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unsigned long delay;
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/* fixme: using mutex?? */
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// spin_lock_irqsave(&priv->lock, flags);
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/* spin_lock_irqsave(&priv->lock, flags); */
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/* TODO Recalibrate*/
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// calibrate_oscillator(priv);
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// antenna_calibrate(priv);
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// agnx_send_packet(priv, 997);
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/* calibrate_oscillator(priv); */
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/* antenna_calibrate(priv); */
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/* agnx_send_packet(priv, 997); /
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/* FIXME */
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/* if (debug == 3) */
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/* delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY); */
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/* else */
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delay = msecs_to_jiffies(AGNX_PERIODIC_DELAY);
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// delay = round_jiffies(HZ * 15);
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/* delay = round_jiffies(HZ * 15); */
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queue_delayed_work(priv->hw->workqueue, &priv->periodic_work, delay);
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// spin_unlock_irqrestore(&priv->lock, flags);
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/* spin_unlock_irqrestore(&priv->lock, flags); */
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}
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#endif
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@ -255,12 +254,12 @@ static int agnx_start(struct ieee80211_hw *dev)
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goto out;
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}
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// mdelay(500);
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/* mdelay(500); */
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might_sleep();
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agnx_hw_init(priv);
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// mdelay(500);
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/* mdelay(500); */
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might_sleep();
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priv->init_status = AGNX_START;
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@ -280,8 +279,8 @@ static void agnx_stop(struct ieee80211_hw *dev)
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/* make sure hardware will not generate irq */
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agnx_hw_reset(priv);
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free_irq(priv->pdev->irq, dev);
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flush_workqueue(priv->hw->workqueue);
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// cancel_delayed_work_sync(&priv->periodic_work);
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flush_workqueue(priv->hw->workqueue);
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/* cancel_delayed_work_sync(&priv->periodic_work); */
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unfill_rings(priv);
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rings_free(priv);
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}
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@ -315,7 +314,6 @@ static int agnx_config_interface(struct ieee80211_hw *dev,
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spin_lock(&priv->lock);
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if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
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// u32 reghi, reglo;
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agnx_set_bssid(priv, conf->bssid);
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memcpy(priv->bssid, conf->bssid, ETH_ALEN);
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hash_write(priv, conf->bssid, BSSID_STAID);
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@ -425,7 +423,7 @@ static struct ieee80211_ops agnx_ops = {
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.remove_interface = agnx_remove_interface,
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.config = agnx_config,
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.config_interface = agnx_config_interface,
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.configure_filter = agnx_configure_filter,
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.configure_filter = agnx_configure_filter,
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.get_stats = agnx_get_stats,
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.get_tx_stats = agnx_get_tx_stats,
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.get_tsf = agnx_get_tsft
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@ -505,7 +503,7 @@ static int __devinit agnx_pci_probe(struct pci_dev *pdev,
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/* Map mem #1 and #2 */
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priv->ctl = pci_iomap(pdev, 0, mem_len0);
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// printk(KERN_DEBUG PFX"MEM1 mapped address is 0x%p\n", priv->ctl);
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/* printk(KERN_DEBUG PFX"MEM1 mapped address is 0x%p\n", priv->ctl); */
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if (!priv->ctl) {
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printk(KERN_ERR PFX "Can't map device memory\n");
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goto err_free_dev;
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