spi: lpspi: Add i.MX8 boards support for lpspi
Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards. Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -84,7 +84,8 @@ struct lpspi_config {
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struct fsl_lpspi_data {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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struct clk *clk_ipg;
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struct clk *clk_per;
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bool is_slave;
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void *rx_buf;
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@ -151,8 +152,19 @@ static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
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{
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struct fsl_lpspi_data *fsl_lpspi =
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spi_controller_get_devdata(controller);
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int ret;
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return clk_prepare_enable(fsl_lpspi->clk);
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ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
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if (ret)
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return ret;
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ret = clk_prepare_enable(fsl_lpspi->clk_per);
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if (ret) {
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clk_disable_unprepare(fsl_lpspi->clk_ipg);
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return ret;
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}
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return 0;
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}
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static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
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@ -160,7 +172,8 @@ static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
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struct fsl_lpspi_data *fsl_lpspi =
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spi_controller_get_devdata(controller);
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clk_disable_unprepare(fsl_lpspi->clk);
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clk_disable_unprepare(fsl_lpspi->clk_ipg);
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clk_disable_unprepare(fsl_lpspi->clk_per);
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return 0;
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}
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@ -241,7 +254,7 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
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unsigned int perclk_rate, scldiv;
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u8 prescale;
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perclk_rate = clk_get_rate(fsl_lpspi->clk);
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perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
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for (prescale = 0; prescale < 8; prescale++) {
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scldiv = perclk_rate /
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(clkdivs[prescale] * config.speed_hz) - 2;
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@ -526,15 +539,30 @@ static int fsl_lpspi_probe(struct platform_device *pdev)
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goto out_controller_put;
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}
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fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg");
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if (IS_ERR(fsl_lpspi->clk)) {
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ret = PTR_ERR(fsl_lpspi->clk);
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fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
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if (IS_ERR(fsl_lpspi->clk_per)) {
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ret = PTR_ERR(fsl_lpspi->clk_per);
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goto out_controller_put;
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}
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ret = clk_prepare_enable(fsl_lpspi->clk);
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fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
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if (IS_ERR(fsl_lpspi->clk_ipg)) {
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ret = PTR_ERR(fsl_lpspi->clk_ipg);
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goto out_controller_put;
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}
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ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
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if (ret) {
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dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret);
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dev_err(&pdev->dev,
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"can't enable lpspi ipg clock, ret=%d\n", ret);
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goto out_controller_put;
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}
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ret = clk_prepare_enable(fsl_lpspi->clk_per);
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if (ret) {
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dev_err(&pdev->dev,
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"can't enable lpspi per clock, ret=%d\n", ret);
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clk_disable_unprepare(fsl_lpspi->clk_ipg);
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goto out_controller_put;
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}
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@ -542,7 +570,8 @@ static int fsl_lpspi_probe(struct platform_device *pdev)
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fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
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fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
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clk_disable_unprepare(fsl_lpspi->clk);
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clk_disable_unprepare(fsl_lpspi->clk_per);
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clk_disable_unprepare(fsl_lpspi->clk_ipg);
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ret = devm_spi_register_controller(&pdev->dev, controller);
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if (ret < 0) {
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@ -564,7 +593,8 @@ static int fsl_lpspi_remove(struct platform_device *pdev)
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struct fsl_lpspi_data *fsl_lpspi =
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spi_controller_get_devdata(controller);
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clk_disable_unprepare(fsl_lpspi->clk);
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clk_disable_unprepare(fsl_lpspi->clk_per);
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clk_disable_unprepare(fsl_lpspi->clk_ipg);
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return 0;
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}
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