IOMMU Fixes for Linux v4.5-rc1
Five patches queued up: * Two patches for the AMD and Intel IOMMU drivers to fix alias handling and ATS handling. * Fix build error with arm io-pgtable code * Two documentation fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJWq3QjAAoJECvwRC2XARrjmlgP/05Yb+diQvFxq1ivTOY4FIcS 5m1eOt3HyWcCI46rvWF+9yWVUQIVdqfGCo6PKg6rsPJWaJGuSEd6Chdb8JappN3V kt29fsuBY6BDvp44+L04pbkyzuDlBGJBN8S8Fdg3NSTP2qSmA0f9AzT6J7ZXB7xd CnnTMj4Uxqvtd9eqql1kZgk7/hEL61QVJVzoo0rGxZcFbOIY8dx/pPHdY2eP6tW1 AxXIHiWgIN+YL/mOSL3crYc7PbktntRgiIoRKFXdQMcDafckP7icLVa/PGNqS49t Et+X43mYniuqA3pbxyFVkcfL9hrUXaj+tC4S5TBHWi7ub10BjWvXgqFBG15+7cgo HR9HgBQnMdMybdsKhiprhINpU+HihvOPfSKjDk+9S/EhUIz0kUWx/2fXWzFcMtLq oZRu16rCZYLfd68rnytCqMO1IBIGCcoiJCow1pT5UJOfZ9pnpacvcyvm0YeELdeS ZuRC80kSrOsT+84cDJYDHeGPVZev4oyAQYZo9olQzzZLkPQefAbJVux2dESCscd0 pcY5ICvJ82Ixf8+c69DRUmQpVrRBOrrEsJTuIGS9aTaj99lXGFseFh0BhQrZ3ZI0 ceStkOBwiNCZ9XWavkxbU8ZrbQ8NnUBmP62M/JaMZpSwsNWsPaBSAMSJ6i3mC5fq /aTJ0++hgwSfjNCiRNme =SFdA -----END PGP SIGNATURE----- Merge tag 'iommu-fixes-v4.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull IOMMU fixes from Joerg Roedel: "Five patches queued up: - Two patches for the AMD and Intel IOMMU drivers to fix alias handling and ATS handling. - Fix build error with arm io-pgtable code - Two documentation fixes" * tag 'iommu-fixes-v4.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu: Update struct iommu_ops comments iommu/vt-d: Fix link to Intel IOMMU Specification iommu/amd: Correct the wrong setting of alias DTE in do_attach iommu/vt-d: Don't skip PCI devices when disabling IOTLB iommu/io-pgtable-arm: Fix io-pgtable-arm build failure
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f6a239a927
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@ -3,7 +3,7 @@ Linux IOMMU Support
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The architecture spec can be obtained from the below location.
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The architecture spec can be obtained from the below location.
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http://www.intel.com/technology/virtualization/
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http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
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This guide gives a quick cheat sheet for some basic understanding.
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This guide gives a quick cheat sheet for some basic understanding.
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@ -2049,7 +2049,7 @@ static void do_attach(struct iommu_dev_data *dev_data,
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/* Update device table */
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/* Update device table */
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set_dte_entry(dev_data->devid, domain, ats);
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set_dte_entry(dev_data->devid, domain, ats);
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if (alias != dev_data->devid)
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if (alias != dev_data->devid)
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set_dte_entry(dev_data->devid, domain, ats);
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set_dte_entry(alias, domain, ats);
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device_flush_dte(dev_data);
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device_flush_dte(dev_data);
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}
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}
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@ -1489,7 +1489,7 @@ static void iommu_disable_dev_iotlb(struct device_domain_info *info)
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{
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{
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struct pci_dev *pdev;
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struct pci_dev *pdev;
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if (dev_is_pci(info->dev))
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if (!dev_is_pci(info->dev))
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return;
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return;
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pdev = to_pci_dev(info->dev);
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pdev = to_pci_dev(info->dev);
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@ -25,6 +25,7 @@
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#include <linux/sizes.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/types.h>
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#include <linux/dma-mapping.h>
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#include <asm/barrier.h>
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#include <asm/barrier.h>
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@ -133,8 +133,9 @@ struct iommu_dm_region {
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/**
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/**
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* struct iommu_ops - iommu ops and capabilities
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* struct iommu_ops - iommu ops and capabilities
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* @domain_init: init iommu domain
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* @capable: check capability
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* @domain_destroy: destroy iommu domain
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* @domain_alloc: allocate iommu domain
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* @domain_free: free iommu domain
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* @attach_dev: attach device to an iommu domain
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* @attach_dev: attach device to an iommu domain
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* @detach_dev: detach device from an iommu domain
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* @detach_dev: detach device from an iommu domain
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* @map: map a physically contiguous memory region to an iommu domain
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* @map: map a physically contiguous memory region to an iommu domain
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@ -144,8 +145,15 @@ struct iommu_dm_region {
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* @iova_to_phys: translate iova to physical address
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* @iova_to_phys: translate iova to physical address
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* @add_device: add device to iommu grouping
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* @add_device: add device to iommu grouping
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* @remove_device: remove device from iommu grouping
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* @remove_device: remove device from iommu grouping
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* @device_group: find iommu group for a particular device
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* @domain_get_attr: Query domain attributes
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* @domain_get_attr: Query domain attributes
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* @domain_set_attr: Change domain attributes
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* @domain_set_attr: Change domain attributes
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* @get_dm_regions: Request list of direct mapping requirements for a device
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* @put_dm_regions: Free list of direct mapping requirements for a device
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* @domain_window_enable: Configure and enable a particular window for a domain
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* @domain_window_disable: Disable a particular window for a domain
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* @domain_set_windows: Set the number of windows for a domain
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* @domain_get_windows: Return the number of windows for a domain
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* @of_xlate: add OF master IDs to iommu grouping
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* @of_xlate: add OF master IDs to iommu grouping
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* @pgsize_bitmap: bitmap of supported page sizes
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* @pgsize_bitmap: bitmap of supported page sizes
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* @priv: per-instance data private to the iommu driver
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* @priv: per-instance data private to the iommu driver
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@ -182,9 +190,9 @@ struct iommu_ops {
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int (*domain_window_enable)(struct iommu_domain *domain, u32 wnd_nr,
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int (*domain_window_enable)(struct iommu_domain *domain, u32 wnd_nr,
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phys_addr_t paddr, u64 size, int prot);
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phys_addr_t paddr, u64 size, int prot);
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void (*domain_window_disable)(struct iommu_domain *domain, u32 wnd_nr);
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void (*domain_window_disable)(struct iommu_domain *domain, u32 wnd_nr);
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/* Set the numer of window per domain */
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/* Set the number of windows per domain */
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int (*domain_set_windows)(struct iommu_domain *domain, u32 w_count);
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int (*domain_set_windows)(struct iommu_domain *domain, u32 w_count);
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/* Get the numer of window per domain */
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/* Get the number of windows per domain */
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u32 (*domain_get_windows)(struct iommu_domain *domain);
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u32 (*domain_get_windows)(struct iommu_domain *domain);
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#ifdef CONFIG_OF_IOMMU
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#ifdef CONFIG_OF_IOMMU
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