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ARM: shmobile: r8a7790: add MLB+ clock 

Add MLB+ clock to R8A7790 device tree.

Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
[Sergei: rebased, renamed, added changelog]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Andrey Gusakov 2014-12-18 23:41:52 +03:00 committed by Simon Horman
parent 09ee81da85
commit f6b5dd4088
2 changed files with 8 additions and 6 deletions
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13
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -1149,16 +1149,17 @@
mstp8_clks: mstp8_clks@e6150990 {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
<&zs_clk>, <&zs_clk>;
clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
<&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
R8A7790_CLK_SATA0
R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
>;
clock-output-names =
"vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
"mlb", "vin3", "vin2", "vin1", "vin0", "ether",
"sata1", "sata0";
};
mstp9_clks: mstp9_clks@e6150994 {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";

1
include/dt-bindings/clock/r8a7790-clock.h
View File

@ -97,6 +97,7 @@
#define R8A7790_CLK_LVDS0 26
/* MSTP8 */
#define R8A7790_CLK_MLB 2
#define R8A7790_CLK_VIN3 8
#define R8A7790_CLK_VIN2 9
#define R8A7790_CLK_VIN1 10