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mlx4_core: Add ethernet fields to CQE struct 

Add ethernet-related fields to struct mlx4_cqe so that the mlx4_en
ethernet NIC driver can share the same definition.

Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
This commit is contained in:
Yevgeny Petrilin 2008-08-06 20:14:06 -07:00 committed by Roland Dreier
parent 6e86841d05
commit f780a9f119
2 changed files with 40 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
drivers/infiniband/hw/mlx4/cq.c
View File

@ -515,17 +515,17 @@ static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
wc->vendor_err = cqe->vendor_err_syndrome;
}
static int mlx4_ib_ipoib_csum_ok(__be32 status, __be16 checksum)
static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
{
return ((status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 |
MLX4_CQE_IPOIB_STATUS_IPV4F |
MLX4_CQE_IPOIB_STATUS_IPV4OPT |
MLX4_CQE_IPOIB_STATUS_IPV6 |
MLX4_CQE_IPOIB_STATUS_IPOK)) ==
cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 |
MLX4_CQE_IPOIB_STATUS_IPOK)) &&
(status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_UDP |
MLX4_CQE_IPOIB_STATUS_TCP)) &&
return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
MLX4_CQE_STATUS_IPV4F |
MLX4_CQE_STATUS_IPV4OPT |
MLX4_CQE_STATUS_IPV6 |
MLX4_CQE_STATUS_IPOK)) ==
cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
MLX4_CQE_STATUS_IPOK)) &&
(status & cpu_to_be16(MLX4_CQE_STATUS_UDP |
MLX4_CQE_STATUS_TCP)) &&
checksum == cpu_to_be16(0xffff);
}
@ -582,17 +582,17 @@ repoll:
}
if (!*cur_qp ||
(be32_to_cpu(cqe->my_qpn) & 0xffffff) != (*cur_qp)->mqp.qpn) {
(be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
/*
* We do not have to take the QP table lock here,
* because CQs will be locked while QPs are removed
* from the table.
*/
mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
be32_to_cpu(cqe->my_qpn));
be32_to_cpu(cqe->vlan_my_qpn));
if (unlikely(!mqp)) {
printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n",
cq->mcq.cqn, be32_to_cpu(cqe->my_qpn) & 0xffffff);
cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
return -EINVAL;
}
@ -692,14 +692,13 @@ repoll:
}
wc->slid = be16_to_cpu(cqe->rlid);
wc->sl = cqe->sl >> 4;
wc->sl = be16_to_cpu(cqe->sl_vid >> 12);
g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
wc->src_qp = g_mlpath_rqpn & 0xffffff;
wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->ipoib_status,
cqe->checksum);
wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->status, cqe->checksum);
}
return 0;
@ -767,7 +766,7 @@ void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
*/
while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
if ((be32_to_cpu(cqe->my_qpn) & 0xffffff) == qpn) {
if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
++nfreed;

36
include/linux/mlx4/cq.h
View File

@ -39,17 +39,18 @@
#include <linux/mlx4/doorbell.h>
struct mlx4_cqe {
__be32 my_qpn;
__be32 vlan_my_qpn;
__be32 immed_rss_invalid;
__be32 g_mlpath_rqpn;
u8 sl;
u8 reserved1;
__be16 sl_vid;
__be16 rlid;
__be32 ipoib_status;
__be16 status;
u8 ipv6_ext_mask;
u8 badfcs_enc;
__be32 byte_cnt;
__be16 wqe_index;
__be16 checksum;
u8 reserved2[3];
u8 reserved[3];
u8 owner_sr_opcode;
};
@ -63,6 +64,11 @@ struct mlx4_err_cqe {
u8 owner_sr_opcode;
};
enum {
MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29,
MLX4_CQE_QPN_MASK = 0xffffff,
};
enum {
MLX4_CQE_OWNER_MASK = 0x80,
MLX4_CQE_IS_SEND_MASK = 0x40,
@ -86,13 +92,19 @@ enum {
};
enum {
MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22,
MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23,
MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24,
MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25,
MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26,
MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27,
MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28,
MLX4_CQE_STATUS_IPV4 = 1 << 6,
MLX4_CQE_STATUS_IPV4F = 1 << 7,
MLX4_CQE_STATUS_IPV6 = 1 << 8,
MLX4_CQE_STATUS_IPV4OPT = 1 << 9,
MLX4_CQE_STATUS_TCP = 1 << 10,
MLX4_CQE_STATUS_UDP = 1 << 11,
MLX4_CQE_STATUS_IPOK = 1 << 12,
};
enum {
MLX4_CQE_LLC = 1,
MLX4_CQE_SNAP = 1 << 1,
MLX4_CQE_BAD_FCS = 1 << 4,
};
static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,