Revert "xhci: replace xhci_read_64() with readq()"
This reverts commit e8b373326d. Many xHCI
host controllers can only handle 32-bit addresses, and writing 64-bits
at a time causes them to fail. Reading 64-bits at a time may also cause
them to return 0xffffffff, so revert this commit as well.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
This commit is contained in:
Sarah Sharp
parent
477632dff5
commit
f7b2e4032d
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@ -203,12 +203,12 @@ void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
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addr, (unsigned int)temp);
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addr = &ir_set->erst_base;
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temp_64 = readq(addr);
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temp_64 = xhci_read_64(xhci, addr);
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xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n",
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addr, temp_64);
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addr = &ir_set->erst_dequeue;
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temp_64 = readq(addr);
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temp_64 = xhci_read_64(xhci, addr);
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xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n",
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addr, temp_64);
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}
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@ -412,7 +412,7 @@ void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
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{
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u64 val;
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val = readq(&xhci->op_regs->cmd_ring);
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val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
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xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
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lower_32_bits(val));
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xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
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@ -1958,7 +1958,7 @@ static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
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xhci_warn(xhci, "WARN something wrong with SW event ring "
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"dequeue ptr.\n");
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/* Update HC event ring dequeue pointer */
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temp = readq(&xhci->ir_set->erst_dequeue);
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temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
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temp &= ERST_PTR_MASK;
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/* Don't clear the EHB bit (which is RW1C) because
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* there might be more events to service.
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@ -2312,7 +2312,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
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(unsigned long long)xhci->cmd_ring->first_seg->dma);
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/* Set the address in the Command Ring Control register */
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val_64 = readq(&xhci->op_regs->cmd_ring);
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val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
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val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
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(xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
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xhci->cmd_ring->cycle_state;
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@ -2396,7 +2396,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
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xhci_dbg_trace(xhci, trace_xhci_dbg_init,
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"// Set ERST base address for ir_set 0 = 0x%llx",
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(unsigned long long)xhci->erst.erst_dma_addr);
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val_64 = readq(&xhci->ir_set->erst_base);
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val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
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val_64 &= ERST_PTR_MASK;
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val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
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xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
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@ -307,7 +307,7 @@ static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
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return 0;
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}
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temp_64 = readq(&xhci->op_regs->cmd_ring);
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temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
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if (!(temp_64 & CMD_RING_RUNNING)) {
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xhci_dbg(xhci, "Command ring had been stopped\n");
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return 0;
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@ -2865,7 +2865,7 @@ hw_died:
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/* Clear the event handler busy flag (RW1C);
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* the event ring should be empty.
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*/
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temp_64 = readq(&xhci->ir_set->erst_dequeue);
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temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
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xhci_write_64(xhci, temp_64 | ERST_EHB,
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&xhci->ir_set->erst_dequeue);
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spin_unlock(&xhci->lock);
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@ -2879,7 +2879,7 @@ hw_died:
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*/
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while (xhci_handle_event(xhci) > 0) {}
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temp_64 = readq(&xhci->ir_set->erst_dequeue);
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temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
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/* If necessary, update the HW's version of the event ring deq ptr. */
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if (event_ring_deq != xhci->event_ring->dequeue) {
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deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
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@ -611,7 +611,7 @@ int xhci_run(struct usb_hcd *hcd)
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xhci_dbg(xhci, "Event ring:\n");
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xhci_debug_ring(xhci, xhci->event_ring);
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xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
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temp_64 = readq(&xhci->ir_set->erst_dequeue);
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temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
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temp_64 &= ~ERST_PTR_MASK;
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xhci_dbg_trace(xhci, trace_xhci_dbg_init,
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"ERST deq = 64'h%0lx", (long unsigned int) temp_64);
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@ -756,11 +756,11 @@ static void xhci_save_registers(struct xhci_hcd *xhci)
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{
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xhci->s3.command = readl(&xhci->op_regs->command);
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xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
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xhci->s3.dcbaa_ptr = readq(&xhci->op_regs->dcbaa_ptr);
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xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
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xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
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xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
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xhci->s3.erst_base = readq(&xhci->ir_set->erst_base);
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xhci->s3.erst_dequeue = readq(&xhci->ir_set->erst_dequeue);
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xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
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xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
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xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
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xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
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}
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@ -783,7 +783,7 @@ static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
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u64 val_64;
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/* step 2: initialize command ring buffer */
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val_64 = readq(&xhci->op_regs->cmd_ring);
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val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
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val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
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(xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
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xhci->cmd_ring->dequeue) &
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@ -3842,7 +3842,7 @@ static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
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if (ret) {
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return ret;
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}
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temp_64 = readq(&xhci->op_regs->dcbaa_ptr);
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temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
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xhci_dbg_trace(xhci, trace_xhci_dbg_address,
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"Op regs DCBAA ptr = %#016llx", temp_64);
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xhci_dbg_trace(xhci, trace_xhci_dbg_address,
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@ -28,8 +28,6 @@
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#include <linux/kernel.h>
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#include <linux/usb/hcd.h>
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#include <asm-generic/io-64-nonatomic-lo-hi.h>
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/* Code sharing between pci-quirks and xhci hcd */
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#include "xhci-ext-caps.h"
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#include "pci-quirks.h"
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@ -1614,6 +1612,14 @@ static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
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* xHCI implementations that do not support 64-bit address pointers will ignore
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* the high dword, and write order is irrelevant.
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*/
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static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
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__le64 __iomem *regs)
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{
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__u32 __iomem *ptr = (__u32 __iomem *) regs;
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u64 val_lo = readl(ptr);
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u64 val_hi = readl(ptr + 1);
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return val_lo + (val_hi << 32);
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}
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static inline void xhci_write_64(struct xhci_hcd *xhci,
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const u64 val, __le64 __iomem *regs)
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{
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