Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6: (21 commits) [SCSI] sd: fix computation of the full size of the device [SCSI] lib: string_get_size(): don't hang on zero; no decimals on exact [SCSI] sun3x_esp: Convert && to || [SCSI] sd: remove command-size switching code [SCSI] 3w-9xxx: remove unnecessary local_irq_save/restore for scsi sg copy API [SCSI] 3w-xxxx: remove unnecessary local_irq_save/restore for scsi sg copy API [SCSI] fix netlink kernel-doc [SCSI] sd: Fix handling of NO_SENSE check condition [SCSI] export busy state via q->lld_busy_fn() [SCSI] refactor sdev/starget/shost busy checking [SCSI] mptfusion: Increase scsi-timeouts, similariy to the LSI 4.x driver. [SCSI] aic7xxx: Take the LED out of diagnostic mode on PM resume [SCSI] aic79xx: user visible misuse wrong SI units (not disk size!) [SCSI] ipr: use memory_read_from_buffer() [SCSI] aic79xx: fix shadowed variables [SCSI] aic79xx: fix shadowed variables, add statics [SCSI] aic7xxx: update *_shipped files [SCSI] aic7xxx: update .reg files [SCSI] aic7xxx: introduce "dont_generate_debug_code" keyword in aicasm parser [SCSI] scsi_dh: Initialize path state to be passive when path is not owned ...
This commit is contained in:
commit
f8aea20018
|
@ -1760,10 +1760,9 @@ mptscsih_get_tm_timeout(MPT_ADAPTER *ioc)
|
||||||
case FC:
|
case FC:
|
||||||
return 40;
|
return 40;
|
||||||
case SAS:
|
case SAS:
|
||||||
return 10;
|
|
||||||
case SPI:
|
case SPI:
|
||||||
default:
|
default:
|
||||||
return 2;
|
return 10;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -1924,12 +1924,9 @@ static void twa_scsiop_execute_scsi_complete(TW_Device_Extension *tw_dev, int re
|
||||||
(cmd->sc_data_direction == DMA_FROM_DEVICE ||
|
(cmd->sc_data_direction == DMA_FROM_DEVICE ||
|
||||||
cmd->sc_data_direction == DMA_BIDIRECTIONAL)) {
|
cmd->sc_data_direction == DMA_BIDIRECTIONAL)) {
|
||||||
if (scsi_sg_count(cmd) == 1) {
|
if (scsi_sg_count(cmd) == 1) {
|
||||||
unsigned long flags;
|
|
||||||
void *buf = tw_dev->generic_buffer_virt[request_id];
|
void *buf = tw_dev->generic_buffer_virt[request_id];
|
||||||
|
|
||||||
local_irq_save(flags);
|
|
||||||
scsi_sg_copy_from_buffer(cmd, buf, TW_SECTOR_SIZE);
|
scsi_sg_copy_from_buffer(cmd, buf, TW_SECTOR_SIZE);
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} /* End twa_scsiop_execute_scsi_complete() */
|
} /* End twa_scsiop_execute_scsi_complete() */
|
||||||
|
|
|
@ -1466,12 +1466,7 @@ static int tw_scsiop_inquiry(TW_Device_Extension *tw_dev, int request_id)
|
||||||
static void tw_transfer_internal(TW_Device_Extension *tw_dev, int request_id,
|
static void tw_transfer_internal(TW_Device_Extension *tw_dev, int request_id,
|
||||||
void *data, unsigned int len)
|
void *data, unsigned int len)
|
||||||
{
|
{
|
||||||
struct scsi_cmnd *cmd = tw_dev->srb[request_id];
|
scsi_sg_copy_from_buffer(tw_dev->srb[request_id], data, len);
|
||||||
unsigned long flags;
|
|
||||||
|
|
||||||
local_irq_save(flags);
|
|
||||||
scsi_sg_copy_from_buffer(cmd, data, len);
|
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* This function is called by the isr to complete an inquiry command */
|
/* This function is called by the isr to complete an inquiry command */
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -2472,8 +2472,6 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
|
||||||
if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
|
if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
|
||||||
ahd_outb(ahd, CLRLQOINT1, 0);
|
ahd_outb(ahd, CLRLQOINT1, 0);
|
||||||
} else if ((status & SELTO) != 0) {
|
} else if ((status & SELTO) != 0) {
|
||||||
u_int scbid;
|
|
||||||
|
|
||||||
/* Stop the selection */
|
/* Stop the selection */
|
||||||
ahd_outb(ahd, SCSISEQ0, 0);
|
ahd_outb(ahd, SCSISEQ0, 0);
|
||||||
|
|
||||||
|
@ -2583,9 +2581,6 @@ ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
|
||||||
case BUSFREE_DFF0:
|
case BUSFREE_DFF0:
|
||||||
case BUSFREE_DFF1:
|
case BUSFREE_DFF1:
|
||||||
{
|
{
|
||||||
u_int scbid;
|
|
||||||
struct scb *scb;
|
|
||||||
|
|
||||||
mode = busfreetime == BUSFREE_DFF0
|
mode = busfreetime == BUSFREE_DFF0
|
||||||
? AHD_MODE_DFF0 : AHD_MODE_DFF1;
|
? AHD_MODE_DFF0 : AHD_MODE_DFF1;
|
||||||
ahd_set_modes(ahd, mode, mode);
|
ahd_set_modes(ahd, mode, mode);
|
||||||
|
@ -3689,7 +3684,7 @@ ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
|
||||||
* by the capabilities of the bus connectivity of and sync settings for
|
* by the capabilities of the bus connectivity of and sync settings for
|
||||||
* the target.
|
* the target.
|
||||||
*/
|
*/
|
||||||
void
|
static void
|
||||||
ahd_devlimited_syncrate(struct ahd_softc *ahd,
|
ahd_devlimited_syncrate(struct ahd_softc *ahd,
|
||||||
struct ahd_initiator_tinfo *tinfo,
|
struct ahd_initiator_tinfo *tinfo,
|
||||||
u_int *period, u_int *ppr_options, role_t role)
|
u_int *period, u_int *ppr_options, role_t role)
|
||||||
|
@ -4136,7 +4131,7 @@ ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Harpoon2A assumed that there would be a
|
* Harpoon2A assumed that there would be a
|
||||||
* fallback rate between 160MHz and 80Mhz,
|
* fallback rate between 160MHz and 80MHz,
|
||||||
* so 7 is used as the period factor rather
|
* so 7 is used as the period factor rather
|
||||||
* than 8 for 160MHz.
|
* than 8 for 160MHz.
|
||||||
*/
|
*/
|
||||||
|
@ -8708,7 +8703,7 @@ ahd_reset_current_bus(struct ahd_softc *ahd)
|
||||||
int
|
int
|
||||||
ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
|
ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
|
||||||
{
|
{
|
||||||
struct ahd_devinfo devinfo;
|
struct ahd_devinfo caminfo;
|
||||||
u_int initiator;
|
u_int initiator;
|
||||||
u_int target;
|
u_int target;
|
||||||
u_int max_scsiid;
|
u_int max_scsiid;
|
||||||
|
@ -8729,7 +8724,7 @@ ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
|
||||||
|
|
||||||
ahd->pending_device = NULL;
|
ahd->pending_device = NULL;
|
||||||
|
|
||||||
ahd_compile_devinfo(&devinfo,
|
ahd_compile_devinfo(&caminfo,
|
||||||
CAM_TARGET_WILDCARD,
|
CAM_TARGET_WILDCARD,
|
||||||
CAM_TARGET_WILDCARD,
|
CAM_TARGET_WILDCARD,
|
||||||
CAM_LUN_WILDCARD,
|
CAM_LUN_WILDCARD,
|
||||||
|
@ -8868,7 +8863,7 @@ ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Notify the XPT that a bus reset occurred */
|
/* Notify the XPT that a bus reset occurred */
|
||||||
ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
|
ahd_send_async(ahd, caminfo.channel, CAM_TARGET_WILDCARD,
|
||||||
CAM_LUN_WILDCARD, AC_BUS_RESET);
|
CAM_LUN_WILDCARD, AC_BUS_RESET);
|
||||||
|
|
||||||
ahd_restart(ahd);
|
ahd_restart(ahd);
|
||||||
|
|
|
@ -223,10 +223,10 @@ static const char *pci_bus_modes[] =
|
||||||
"PCI bus mode unknown",
|
"PCI bus mode unknown",
|
||||||
"PCI bus mode unknown",
|
"PCI bus mode unknown",
|
||||||
"PCI bus mode unknown",
|
"PCI bus mode unknown",
|
||||||
"PCI-X 101-133Mhz",
|
"PCI-X 101-133MHz",
|
||||||
"PCI-X 67-100Mhz",
|
"PCI-X 67-100MHz",
|
||||||
"PCI-X 50-66Mhz",
|
"PCI-X 50-66MHz",
|
||||||
"PCI 33 or 66Mhz"
|
"PCI 33 or 66MHz"
|
||||||
};
|
};
|
||||||
|
|
||||||
#define TESTMODE 0x00000800ul
|
#define TESTMODE 0x00000800ul
|
||||||
|
@ -337,8 +337,6 @@ ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry)
|
||||||
* 64bit bus (PCI64BIT set in devconfig).
|
* 64bit bus (PCI64BIT set in devconfig).
|
||||||
*/
|
*/
|
||||||
if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
|
if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
|
||||||
uint32_t devconfig;
|
|
||||||
|
|
||||||
if (bootverbose)
|
if (bootverbose)
|
||||||
printf("%s: Enabling 39Bit Addressing\n",
|
printf("%s: Enabling 39Bit Addressing\n",
|
||||||
ahd_name(ahd));
|
ahd_name(ahd));
|
||||||
|
@ -483,8 +481,6 @@ ahd_pci_test_register_access(struct ahd_softc *ahd)
|
||||||
goto fail;
|
goto fail;
|
||||||
|
|
||||||
if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
|
if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
|
||||||
u_int targpcistat;
|
|
||||||
|
|
||||||
ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
|
ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
|
||||||
targpcistat = ahd_inb(ahd, TARGPCISTAT);
|
targpcistat = ahd_inb(ahd, TARGPCISTAT);
|
||||||
if ((targpcistat & STA) != 0)
|
if ((targpcistat & STA) != 0)
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -50,6 +50,17 @@ VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $"
|
||||||
* Adaptec's Technical Documents Department 1-800-934-2766
|
* Adaptec's Technical Documents Department 1-800-934-2766
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Registers marked "dont_generate_debug_code" are not (yet) referenced
|
||||||
|
* from the driver code, and this keyword inhibit generation
|
||||||
|
* of debug code for them.
|
||||||
|
*
|
||||||
|
* REG_PRETTY_PRINT config will complain if dont_generate_debug_code
|
||||||
|
* is added to the register which is referenced in the driver.
|
||||||
|
* Unreferenced register with no dont_generate_debug_code will result
|
||||||
|
* in dead code. No warning is issued.
|
||||||
|
*/
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* SCSI Sequence Control (p. 3-11).
|
* SCSI Sequence Control (p. 3-11).
|
||||||
* Each bit, when set starts a specific SCSI sequence on the bus
|
* Each bit, when set starts a specific SCSI sequence on the bus
|
||||||
|
@ -97,6 +108,7 @@ register SXFRCTL1 {
|
||||||
field ENSTIMER 0x04
|
field ENSTIMER 0x04
|
||||||
field ACTNEGEN 0x02
|
field ACTNEGEN 0x02
|
||||||
field STPWEN 0x01 /* Powered Termination */
|
field STPWEN 0x01 /* Powered Termination */
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -155,6 +167,7 @@ register SCSISIGO {
|
||||||
mask P_MESGOUT CDI|MSGI
|
mask P_MESGOUT CDI|MSGI
|
||||||
mask P_STATUS CDI|IOI
|
mask P_STATUS CDI|IOI
|
||||||
mask P_MESGIN CDI|IOI|MSGI
|
mask P_MESGIN CDI|IOI|MSGI
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -194,6 +207,7 @@ register SCSIID {
|
||||||
*/
|
*/
|
||||||
alias SCSIOFFSET
|
alias SCSIOFFSET
|
||||||
mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */
|
mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -205,6 +219,7 @@ register SCSIID {
|
||||||
register SCSIDATL {
|
register SCSIDATL {
|
||||||
address 0x006
|
address 0x006
|
||||||
access_mode RW
|
access_mode RW
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register SCSIDATH {
|
register SCSIDATH {
|
||||||
|
@ -223,6 +238,7 @@ register STCNT {
|
||||||
address 0x008
|
address 0x008
|
||||||
size 3
|
size 3
|
||||||
access_mode RW
|
access_mode RW
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ALT_MODE registers (Ultra2 and Ultra160 chips) */
|
/* ALT_MODE registers (Ultra2 and Ultra160 chips) */
|
||||||
|
@ -248,6 +264,7 @@ register OPTIONMODE {
|
||||||
field AUTO_MSGOUT_DE 0x02
|
field AUTO_MSGOUT_DE 0x02
|
||||||
field DIS_MSGIN_DUALEDGE 0x01
|
field DIS_MSGIN_DUALEDGE 0x01
|
||||||
mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
|
mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ALT_MODE register on Ultra160 chips */
|
/* ALT_MODE register on Ultra160 chips */
|
||||||
|
@ -256,6 +273,7 @@ register TARGCRCCNT {
|
||||||
size 2
|
size 2
|
||||||
access_mode RW
|
access_mode RW
|
||||||
count 2
|
count 2
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -271,6 +289,7 @@ register CLRSINT0 {
|
||||||
field CLRSWRAP 0x08
|
field CLRSWRAP 0x08
|
||||||
field CLRIOERR 0x08 /* Ultra2 Only */
|
field CLRIOERR 0x08 /* Ultra2 Only */
|
||||||
field CLRSPIORDY 0x02
|
field CLRSPIORDY 0x02
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -306,6 +325,7 @@ register CLRSINT1 {
|
||||||
field CLRSCSIPERR 0x04
|
field CLRSCSIPERR 0x04
|
||||||
field CLRPHASECHG 0x02
|
field CLRPHASECHG 0x02
|
||||||
field CLRREQINIT 0x01
|
field CLRREQINIT 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -360,6 +380,7 @@ register SCSIID_ULTRA2 {
|
||||||
access_mode RW
|
access_mode RW
|
||||||
mask TID 0xf0 /* Target ID mask */
|
mask TID 0xf0 /* Target ID mask */
|
||||||
mask OID 0x0f /* Our ID mask */
|
mask OID 0x0f /* Our ID mask */
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -425,6 +446,7 @@ register SHADDR {
|
||||||
address 0x014
|
address 0x014
|
||||||
size 4
|
size 4
|
||||||
access_mode RO
|
access_mode RO
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -441,6 +463,7 @@ register SELTIMER {
|
||||||
field STAGE2 0x02
|
field STAGE2 0x02
|
||||||
field STAGE1 0x01
|
field STAGE1 0x01
|
||||||
alias TARGIDIN
|
alias TARGIDIN
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -453,6 +476,7 @@ register SELID {
|
||||||
access_mode RW
|
access_mode RW
|
||||||
mask SELID_MASK 0xf0
|
mask SELID_MASK 0xf0
|
||||||
field ONEBIT 0x08
|
field ONEBIT 0x08
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register SCAMCTL {
|
register SCAMCTL {
|
||||||
|
@ -473,6 +497,7 @@ register TARGID {
|
||||||
size 2
|
size 2
|
||||||
access_mode RW
|
access_mode RW
|
||||||
count 14
|
count 14
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -495,6 +520,7 @@ register SPIOCAP {
|
||||||
field EEPROM 0x04 /* Writable external BIOS ROM */
|
field EEPROM 0x04 /* Writable external BIOS ROM */
|
||||||
field ROM 0x02 /* Logic for accessing external ROM */
|
field ROM 0x02 /* Logic for accessing external ROM */
|
||||||
field SSPIOCPS 0x01 /* Termination and cable detection */
|
field SSPIOCPS 0x01 /* Termination and cable detection */
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register BRDCTL {
|
register BRDCTL {
|
||||||
|
@ -514,6 +540,7 @@ register BRDCTL {
|
||||||
field BRDDAT2 0x04
|
field BRDDAT2 0x04
|
||||||
field BRDRW_ULTRA2 0x02
|
field BRDRW_ULTRA2 0x02
|
||||||
field BRDSTB_ULTRA2 0x01
|
field BRDSTB_ULTRA2 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -551,6 +578,7 @@ register SEECTL {
|
||||||
field SEECK 0x04
|
field SEECK 0x04
|
||||||
field SEEDO 0x02
|
field SEEDO 0x02
|
||||||
field SEEDI 0x01
|
field SEEDI 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* SCSI Block Control (p. 3-32)
|
* SCSI Block Control (p. 3-32)
|
||||||
|
@ -601,6 +629,7 @@ register SEQRAM {
|
||||||
address 0x061
|
address 0x061
|
||||||
access_mode RW
|
access_mode RW
|
||||||
count 2
|
count 2
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -610,6 +639,7 @@ register SEQRAM {
|
||||||
register SEQADDR0 {
|
register SEQADDR0 {
|
||||||
address 0x062
|
address 0x062
|
||||||
access_mode RW
|
access_mode RW
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register SEQADDR1 {
|
register SEQADDR1 {
|
||||||
|
@ -617,6 +647,7 @@ register SEQADDR1 {
|
||||||
access_mode RW
|
access_mode RW
|
||||||
count 8
|
count 8
|
||||||
mask SEQADDR1_MASK 0x01
|
mask SEQADDR1_MASK 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -627,35 +658,41 @@ register ACCUM {
|
||||||
address 0x064
|
address 0x064
|
||||||
access_mode RW
|
access_mode RW
|
||||||
accumulator
|
accumulator
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register SINDEX {
|
register SINDEX {
|
||||||
address 0x065
|
address 0x065
|
||||||
access_mode RW
|
access_mode RW
|
||||||
sindex
|
sindex
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register DINDEX {
|
register DINDEX {
|
||||||
address 0x066
|
address 0x066
|
||||||
access_mode RW
|
access_mode RW
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register ALLONES {
|
register ALLONES {
|
||||||
address 0x069
|
address 0x069
|
||||||
access_mode RO
|
access_mode RO
|
||||||
allones
|
allones
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register ALLZEROS {
|
register ALLZEROS {
|
||||||
address 0x06a
|
address 0x06a
|
||||||
access_mode RO
|
access_mode RO
|
||||||
allzeros
|
allzeros
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register NONE {
|
register NONE {
|
||||||
address 0x06a
|
address 0x06a
|
||||||
access_mode WO
|
access_mode WO
|
||||||
none
|
none
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register FLAGS {
|
register FLAGS {
|
||||||
|
@ -664,16 +701,19 @@ register FLAGS {
|
||||||
count 18
|
count 18
|
||||||
field ZERO 0x02
|
field ZERO 0x02
|
||||||
field CARRY 0x01
|
field CARRY 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register SINDIR {
|
register SINDIR {
|
||||||
address 0x06c
|
address 0x06c
|
||||||
access_mode RO
|
access_mode RO
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register DINDIR {
|
register DINDIR {
|
||||||
address 0x06d
|
address 0x06d
|
||||||
access_mode WO
|
access_mode WO
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register FUNCTION1 {
|
register FUNCTION1 {
|
||||||
|
@ -685,6 +725,7 @@ register STACK {
|
||||||
address 0x06f
|
address 0x06f
|
||||||
access_mode RO
|
access_mode RO
|
||||||
count 5
|
count 5
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
const STACK_SIZE 4
|
const STACK_SIZE 4
|
||||||
|
@ -716,6 +757,7 @@ register DSCOMMAND0 {
|
||||||
field RAMPS 0x04 /* External SCB RAM Present */
|
field RAMPS 0x04 /* External SCB RAM Present */
|
||||||
field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */
|
field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */
|
||||||
field CIOPARCKEN 0x01 /* Internal bus parity error enable */
|
field CIOPARCKEN 0x01 /* Internal bus parity error enable */
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register DSCOMMAND1 {
|
register DSCOMMAND1 {
|
||||||
|
@ -724,6 +766,7 @@ register DSCOMMAND1 {
|
||||||
mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */
|
mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */
|
||||||
field HADDLDSEL1 0x02 /* Host Address Load Select Bits */
|
field HADDLDSEL1 0x02 /* Host Address Load Select Bits */
|
||||||
field HADDLDSEL0 0x01
|
field HADDLDSEL0 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -735,6 +778,7 @@ register BUSTIME {
|
||||||
count 2
|
count 2
|
||||||
mask BOFF 0xf0
|
mask BOFF 0xf0
|
||||||
mask BON 0x0f
|
mask BON 0x0f
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -749,6 +793,7 @@ register BUSSPD {
|
||||||
mask STBON 0x07
|
mask STBON 0x07
|
||||||
mask DFTHRSH_100 0xc0
|
mask DFTHRSH_100 0xc0
|
||||||
mask DFTHRSH_75 0x80
|
mask DFTHRSH_75 0x80
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/* aic7850/55/60/70/80/95 only */
|
/* aic7850/55/60/70/80/95 only */
|
||||||
|
@ -756,6 +801,7 @@ register DSPCISTATUS {
|
||||||
address 0x086
|
address 0x086
|
||||||
count 4
|
count 4
|
||||||
mask DFTHRSH_100 0xc0
|
mask DFTHRSH_100 0xc0
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/* aic7890/91/96/97 only */
|
/* aic7890/91/96/97 only */
|
||||||
|
@ -764,6 +810,7 @@ register HS_MAILBOX {
|
||||||
mask HOST_MAILBOX 0xF0
|
mask HOST_MAILBOX 0xF0
|
||||||
mask SEQ_MAILBOX 0x0F
|
mask SEQ_MAILBOX 0x0F
|
||||||
mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
|
mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
const HOST_MAILBOX_SHIFT 4
|
const HOST_MAILBOX_SHIFT 4
|
||||||
|
@ -784,6 +831,7 @@ register HCNTRL {
|
||||||
field INTEN 0x02
|
field INTEN 0x02
|
||||||
field CHIPRST 0x01
|
field CHIPRST 0x01
|
||||||
field CHIPRSTACK 0x01
|
field CHIPRSTACK 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -795,12 +843,14 @@ register HADDR {
|
||||||
address 0x088
|
address 0x088
|
||||||
size 4
|
size 4
|
||||||
access_mode RW
|
access_mode RW
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register HCNT {
|
register HCNT {
|
||||||
address 0x08c
|
address 0x08c
|
||||||
size 3
|
size 3
|
||||||
access_mode RW
|
access_mode RW
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -810,6 +860,7 @@ register HCNT {
|
||||||
register SCBPTR {
|
register SCBPTR {
|
||||||
address 0x090
|
address 0x090
|
||||||
access_mode RW
|
access_mode RW
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -878,6 +929,7 @@ register INTSTAT {
|
||||||
|
|
||||||
mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
|
mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
|
||||||
mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
|
mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -911,6 +963,7 @@ register CLRINT {
|
||||||
field CLRSCSIINT 0x04
|
field CLRSCSIINT 0x04
|
||||||
field CLRCMDINT 0x02
|
field CLRCMDINT 0x02
|
||||||
field CLRSEQINT 0x01
|
field CLRSEQINT 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register DFCNTRL {
|
register DFCNTRL {
|
||||||
|
@ -944,6 +997,7 @@ register DFSTATUS {
|
||||||
register DFWADDR {
|
register DFWADDR {
|
||||||
address 0x95
|
address 0x95
|
||||||
access_mode RW
|
access_mode RW
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register DFRADDR {
|
register DFRADDR {
|
||||||
|
@ -954,6 +1008,7 @@ register DFRADDR {
|
||||||
register DFDAT {
|
register DFDAT {
|
||||||
address 0x099
|
address 0x099
|
||||||
access_mode RW
|
access_mode RW
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -967,6 +1022,7 @@ register SCBCNT {
|
||||||
count 1
|
count 1
|
||||||
field SCBAUTO 0x80
|
field SCBAUTO 0x80
|
||||||
mask SCBCNT_MASK 0x1f
|
mask SCBCNT_MASK 0x1f
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -977,6 +1033,7 @@ register QINFIFO {
|
||||||
address 0x09b
|
address 0x09b
|
||||||
access_mode RW
|
access_mode RW
|
||||||
count 12
|
count 12
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -996,6 +1053,7 @@ register QOUTFIFO {
|
||||||
address 0x09d
|
address 0x09d
|
||||||
access_mode WO
|
access_mode WO
|
||||||
count 7
|
count 7
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register CRCCONTROL1 {
|
register CRCCONTROL1 {
|
||||||
|
@ -1008,6 +1066,7 @@ register CRCCONTROL1 {
|
||||||
field CRCREQCHKEN 0x10
|
field CRCREQCHKEN 0x10
|
||||||
field TARGCRCENDEN 0x08
|
field TARGCRCENDEN 0x08
|
||||||
field TARGCRCCNTEN 0x04
|
field TARGCRCCNTEN 0x04
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -1040,6 +1099,7 @@ register SFUNCT {
|
||||||
access_mode RW
|
access_mode RW
|
||||||
count 4
|
count 4
|
||||||
field ALT_MODE 0x80
|
field ALT_MODE 0x80
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1053,24 +1113,31 @@ scb {
|
||||||
size 4
|
size 4
|
||||||
alias SCB_RESIDUAL_DATACNT
|
alias SCB_RESIDUAL_DATACNT
|
||||||
alias SCB_CDB_STORE
|
alias SCB_CDB_STORE
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_RESIDUAL_SGPTR {
|
SCB_RESIDUAL_SGPTR {
|
||||||
size 4
|
size 4
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_SCSI_STATUS {
|
SCB_SCSI_STATUS {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_TARGET_PHASES {
|
SCB_TARGET_PHASES {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_TARGET_DATA_DIR {
|
SCB_TARGET_DATA_DIR {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_TARGET_ITAG {
|
SCB_TARGET_ITAG {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_DATAPTR {
|
SCB_DATAPTR {
|
||||||
size 4
|
size 4
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_DATACNT {
|
SCB_DATACNT {
|
||||||
/*
|
/*
|
||||||
|
@ -1080,12 +1147,14 @@ scb {
|
||||||
size 4
|
size 4
|
||||||
field SG_LAST_SEG 0x80 /* In the fourth byte */
|
field SG_LAST_SEG 0x80 /* In the fourth byte */
|
||||||
mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
|
mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_SGPTR {
|
SCB_SGPTR {
|
||||||
size 4
|
size 4
|
||||||
field SG_RESID_VALID 0x04 /* In the first byte */
|
field SG_RESID_VALID 0x04 /* In the first byte */
|
||||||
field SG_FULL_RESID 0x02 /* In the first byte */
|
field SG_FULL_RESID 0x02 /* In the first byte */
|
||||||
field SG_LIST_NULL 0x01 /* In the first byte */
|
field SG_LIST_NULL 0x01 /* In the first byte */
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_CONTROL {
|
SCB_CONTROL {
|
||||||
size 1
|
size 1
|
||||||
|
@ -1115,22 +1184,27 @@ scb {
|
||||||
}
|
}
|
||||||
SCB_CDB_LEN {
|
SCB_CDB_LEN {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_SCSIRATE {
|
SCB_SCSIRATE {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_SCSIOFFSET {
|
SCB_SCSIOFFSET {
|
||||||
size 1
|
size 1
|
||||||
count 1
|
count 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_NEXT {
|
SCB_NEXT {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SCB_64_SPARE {
|
SCB_64_SPARE {
|
||||||
size 16
|
size 16
|
||||||
}
|
}
|
||||||
SCB_64_BTT {
|
SCB_64_BTT {
|
||||||
size 16
|
size 16
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1149,6 +1223,7 @@ register SEECTL_2840 {
|
||||||
field CS_2840 0x04
|
field CS_2840 0x04
|
||||||
field CK_2840 0x02
|
field CK_2840 0x02
|
||||||
field DO_2840 0x01
|
field DO_2840 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register STATUS_2840 {
|
register STATUS_2840 {
|
||||||
|
@ -1159,6 +1234,7 @@ register STATUS_2840 {
|
||||||
mask BIOS_SEL 0x60
|
mask BIOS_SEL 0x60
|
||||||
mask ADSEL 0x1e
|
mask ADSEL 0x1e
|
||||||
field DI_2840 0x01
|
field DI_2840 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/* --------------------- AIC-7870-only definitions -------------------- */
|
/* --------------------- AIC-7870-only definitions -------------------- */
|
||||||
|
@ -1166,18 +1242,22 @@ register STATUS_2840 {
|
||||||
register CCHADDR {
|
register CCHADDR {
|
||||||
address 0x0E0
|
address 0x0E0
|
||||||
size 8
|
size 8
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register CCHCNT {
|
register CCHCNT {
|
||||||
address 0x0E8
|
address 0x0E8
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register CCSGRAM {
|
register CCSGRAM {
|
||||||
address 0x0E9
|
address 0x0E9
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register CCSGADDR {
|
register CCSGADDR {
|
||||||
address 0x0EA
|
address 0x0EA
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register CCSGCTL {
|
register CCSGCTL {
|
||||||
|
@ -1186,11 +1266,13 @@ register CCSGCTL {
|
||||||
field CCSGEN 0x08
|
field CCSGEN 0x08
|
||||||
field SG_FETCH_NEEDED 0x02 /* Bit used for software state */
|
field SG_FETCH_NEEDED 0x02 /* Bit used for software state */
|
||||||
field CCSGRESET 0x01
|
field CCSGRESET 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register CCSCBCNT {
|
register CCSCBCNT {
|
||||||
address 0xEF
|
address 0xEF
|
||||||
count 1
|
count 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register CCSCBCTL {
|
register CCSCBCTL {
|
||||||
|
@ -1201,14 +1283,17 @@ register CCSCBCTL {
|
||||||
field CCSCBEN 0x08
|
field CCSCBEN 0x08
|
||||||
field CCSCBDIR 0x04
|
field CCSCBDIR 0x04
|
||||||
field CCSCBRESET 0x01
|
field CCSCBRESET 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register CCSCBADDR {
|
register CCSCBADDR {
|
||||||
address 0x0ED
|
address 0x0ED
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register CCSCBRAM {
|
register CCSCBRAM {
|
||||||
address 0xEC
|
address 0xEC
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1218,23 +1303,28 @@ register SCBBADDR {
|
||||||
address 0x0F0
|
address 0x0F0
|
||||||
access_mode RW
|
access_mode RW
|
||||||
count 3
|
count 3
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register CCSCBPTR {
|
register CCSCBPTR {
|
||||||
address 0x0F1
|
address 0x0F1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register HNSCB_QOFF {
|
register HNSCB_QOFF {
|
||||||
address 0x0F4
|
address 0x0F4
|
||||||
count 4
|
count 4
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register SNSCB_QOFF {
|
register SNSCB_QOFF {
|
||||||
address 0x0F6
|
address 0x0F6
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register SDSCB_QOFF {
|
register SDSCB_QOFF {
|
||||||
address 0x0F8
|
address 0x0F8
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register QOFF_CTLSTA {
|
register QOFF_CTLSTA {
|
||||||
|
@ -1244,6 +1334,7 @@ register QOFF_CTLSTA {
|
||||||
field SDSCB_ROLLOVER 0x10
|
field SDSCB_ROLLOVER 0x10
|
||||||
mask SCB_QSIZE 0x07
|
mask SCB_QSIZE 0x07
|
||||||
mask SCB_QSIZE_256 0x06
|
mask SCB_QSIZE_256 0x06
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register DFF_THRSH {
|
register DFF_THRSH {
|
||||||
|
@ -1267,6 +1358,7 @@ register DFF_THRSH {
|
||||||
mask WR_DFTHRSH_90 0x60
|
mask WR_DFTHRSH_90 0x60
|
||||||
mask WR_DFTHRSH_MAX 0x70
|
mask WR_DFTHRSH_MAX 0x70
|
||||||
count 4
|
count 4
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register SG_CACHE_PRE {
|
register SG_CACHE_PRE {
|
||||||
|
@ -1275,6 +1367,7 @@ register SG_CACHE_PRE {
|
||||||
mask SG_ADDR_MASK 0xf8
|
mask SG_ADDR_MASK 0xf8
|
||||||
field LAST_SEG 0x02
|
field LAST_SEG 0x02
|
||||||
field LAST_SEG_DONE 0x01
|
field LAST_SEG_DONE 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
register SG_CACHE_SHADOW {
|
register SG_CACHE_SHADOW {
|
||||||
|
@ -1283,6 +1376,7 @@ register SG_CACHE_SHADOW {
|
||||||
mask SG_ADDR_MASK 0xf8
|
mask SG_ADDR_MASK 0xf8
|
||||||
field LAST_SEG 0x02
|
field LAST_SEG 0x02
|
||||||
field LAST_SEG_DONE 0x01
|
field LAST_SEG_DONE 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/* ---------------------- Scratch RAM Offsets ------------------------- */
|
/* ---------------------- Scratch RAM Offsets ------------------------- */
|
||||||
/* These offsets are either to values that are initialized by the board's
|
/* These offsets are either to values that are initialized by the board's
|
||||||
|
@ -1309,6 +1403,7 @@ scratch_ram {
|
||||||
BUSY_TARGETS {
|
BUSY_TARGETS {
|
||||||
alias TARG_SCSIRATE
|
alias TARG_SCSIRATE
|
||||||
size 16
|
size 16
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* Bit vector of targets that have ULTRA enabled as set by
|
* Bit vector of targets that have ULTRA enabled as set by
|
||||||
|
@ -1321,6 +1416,7 @@ scratch_ram {
|
||||||
alias CMDSIZE_TABLE
|
alias CMDSIZE_TABLE
|
||||||
size 2
|
size 2
|
||||||
count 2
|
count 2
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* Bit vector of targets that have disconnection disabled as set by
|
* Bit vector of targets that have disconnection disabled as set by
|
||||||
|
@ -1331,6 +1427,7 @@ scratch_ram {
|
||||||
DISC_DSB {
|
DISC_DSB {
|
||||||
size 2
|
size 2
|
||||||
count 6
|
count 6
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
CMDSIZE_TABLE_TAIL {
|
CMDSIZE_TABLE_TAIL {
|
||||||
size 4
|
size 4
|
||||||
|
@ -1341,12 +1438,14 @@ scratch_ram {
|
||||||
*/
|
*/
|
||||||
MWI_RESIDUAL {
|
MWI_RESIDUAL {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* SCBID of the next SCB to be started by the controller.
|
* SCBID of the next SCB to be started by the controller.
|
||||||
*/
|
*/
|
||||||
NEXT_QUEUED_SCB {
|
NEXT_QUEUED_SCB {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* Single byte buffer used to designate the type or message
|
* Single byte buffer used to designate the type or message
|
||||||
|
@ -1354,6 +1453,7 @@ scratch_ram {
|
||||||
*/
|
*/
|
||||||
MSG_OUT {
|
MSG_OUT {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/* Parameters for DMA Logic */
|
/* Parameters for DMA Logic */
|
||||||
DMAPARAMS {
|
DMAPARAMS {
|
||||||
|
@ -1369,6 +1469,7 @@ scratch_ram {
|
||||||
field DIRECTION 0x04 /* Set indicates PCI->SCSI */
|
field DIRECTION 0x04 /* Set indicates PCI->SCSI */
|
||||||
field FIFOFLUSH 0x02
|
field FIFOFLUSH 0x02
|
||||||
field FIFORESET 0x01
|
field FIFORESET 0x01
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SEQ_FLAGS {
|
SEQ_FLAGS {
|
||||||
size 1
|
size 1
|
||||||
|
@ -1390,9 +1491,11 @@ scratch_ram {
|
||||||
*/
|
*/
|
||||||
SAVED_SCSIID {
|
SAVED_SCSIID {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
SAVED_LUN {
|
SAVED_LUN {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* The last bus phase as seen by the sequencer.
|
* The last bus phase as seen by the sequencer.
|
||||||
|
@ -1417,6 +1520,7 @@ scratch_ram {
|
||||||
*/
|
*/
|
||||||
WAITING_SCBH {
|
WAITING_SCBH {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* head of list of SCBs that are
|
* head of list of SCBs that are
|
||||||
|
@ -1425,6 +1529,7 @@ scratch_ram {
|
||||||
*/
|
*/
|
||||||
DISCONNECTED_SCBH {
|
DISCONNECTED_SCBH {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* head of list of SCBs that are
|
* head of list of SCBs that are
|
||||||
|
@ -1432,6 +1537,7 @@ scratch_ram {
|
||||||
*/
|
*/
|
||||||
FREE_SCBH {
|
FREE_SCBH {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* head of list of SCBs that have
|
* head of list of SCBs that have
|
||||||
|
@ -1446,6 +1552,7 @@ scratch_ram {
|
||||||
*/
|
*/
|
||||||
HSCB_ADDR {
|
HSCB_ADDR {
|
||||||
size 4
|
size 4
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* Base address of our shared data with the kernel driver in host
|
* Base address of our shared data with the kernel driver in host
|
||||||
|
@ -1454,15 +1561,19 @@ scratch_ram {
|
||||||
*/
|
*/
|
||||||
SHARED_DATA_ADDR {
|
SHARED_DATA_ADDR {
|
||||||
size 4
|
size 4
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
KERNEL_QINPOS {
|
KERNEL_QINPOS {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
QINPOS {
|
QINPOS {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
QOUTPOS {
|
QOUTPOS {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
/*
|
/*
|
||||||
* Kernel and sequencer offsets into the queue of
|
* Kernel and sequencer offsets into the queue of
|
||||||
|
@ -1471,9 +1582,11 @@ scratch_ram {
|
||||||
*/
|
*/
|
||||||
KERNEL_TQINPOS {
|
KERNEL_TQINPOS {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
TQINPOS {
|
TQINPOS {
|
||||||
size 1
|
size 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
ARG_1 {
|
ARG_1 {
|
||||||
size 1
|
size 1
|
||||||
|
@ -1486,10 +1599,12 @@ scratch_ram {
|
||||||
mask CONT_MSG_LOOP 0x04
|
mask CONT_MSG_LOOP 0x04
|
||||||
mask CONT_TARG_SESSION 0x02
|
mask CONT_TARG_SESSION 0x02
|
||||||
alias RETURN_1
|
alias RETURN_1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
ARG_2 {
|
ARG_2 {
|
||||||
size 1
|
size 1
|
||||||
alias RETURN_2
|
alias RETURN_2
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1498,6 +1613,7 @@ scratch_ram {
|
||||||
LAST_MSG {
|
LAST_MSG {
|
||||||
size 1
|
size 1
|
||||||
alias TARG_IMMEDIATE_SCB
|
alias TARG_IMMEDIATE_SCB
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1513,6 +1629,7 @@ scratch_ram {
|
||||||
field ENAUTOATNO 0x08
|
field ENAUTOATNO 0x08
|
||||||
field ENAUTOATNI 0x04
|
field ENAUTOATNI 0x04
|
||||||
field ENAUTOATNP 0x02
|
field ENAUTOATNP 0x02
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1533,12 +1650,14 @@ scratch_ram {
|
||||||
field HA_274_EXTENDED_TRANS 0x01
|
field HA_274_EXTENDED_TRANS 0x01
|
||||||
alias INITIATOR_TAG
|
alias INITIATOR_TAG
|
||||||
count 1
|
count 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
|
|
||||||
SEQ_FLAGS2 {
|
SEQ_FLAGS2 {
|
||||||
size 1
|
size 1
|
||||||
field SCB_DMA 0x01
|
field SCB_DMA 0x01
|
||||||
field TARGET_MSG_PENDING 0x02
|
field TARGET_MSG_PENDING 0x02
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1562,6 +1681,7 @@ scratch_ram {
|
||||||
field ENSPCHK 0x20
|
field ENSPCHK 0x20
|
||||||
mask HSCSIID 0x07 /* our SCSI ID */
|
mask HSCSIID 0x07 /* our SCSI ID */
|
||||||
mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
|
mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
INTDEF {
|
INTDEF {
|
||||||
address 0x05c
|
address 0x05c
|
||||||
|
@ -1569,11 +1689,13 @@ scratch_ram {
|
||||||
count 1
|
count 1
|
||||||
field EDGE_TRIG 0x80
|
field EDGE_TRIG 0x80
|
||||||
mask VECTOR 0x0f
|
mask VECTOR 0x0f
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
HOSTCONF {
|
HOSTCONF {
|
||||||
address 0x05d
|
address 0x05d
|
||||||
size 1
|
size 1
|
||||||
count 1
|
count 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
HA_274_BIOSCTRL {
|
HA_274_BIOSCTRL {
|
||||||
address 0x05f
|
address 0x05f
|
||||||
|
@ -1582,6 +1704,7 @@ scratch_ram {
|
||||||
mask BIOSMODE 0x30
|
mask BIOSMODE 0x30
|
||||||
mask BIOSDISABLED 0x30
|
mask BIOSDISABLED 0x30
|
||||||
field CHANNEL_B_PRIMARY 0x08
|
field CHANNEL_B_PRIMARY 0x08
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1595,6 +1718,7 @@ scratch_ram {
|
||||||
TARG_OFFSET {
|
TARG_OFFSET {
|
||||||
size 16
|
size 16
|
||||||
count 1
|
count 1
|
||||||
|
dont_generate_debug_code
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -814,6 +814,7 @@ ahc_intr(struct ahc_softc *ahc)
|
||||||
static void
|
static void
|
||||||
ahc_restart(struct ahc_softc *ahc)
|
ahc_restart(struct ahc_softc *ahc)
|
||||||
{
|
{
|
||||||
|
uint8_t sblkctl;
|
||||||
|
|
||||||
ahc_pause(ahc);
|
ahc_pause(ahc);
|
||||||
|
|
||||||
|
@ -868,6 +869,12 @@ ahc_restart(struct ahc_softc *ahc)
|
||||||
ahc_outb(ahc, SEQADDR0, 0);
|
ahc_outb(ahc, SEQADDR0, 0);
|
||||||
ahc_outb(ahc, SEQADDR1, 0);
|
ahc_outb(ahc, SEQADDR1, 0);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Take the LED out of diagnostic mode on PM resume, too
|
||||||
|
*/
|
||||||
|
sblkctl = ahc_inb(ahc, SBLKCTL);
|
||||||
|
ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
|
||||||
|
|
||||||
ahc_unpause(ahc);
|
ahc_unpause(ahc);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -26,20 +26,6 @@ ahc_reg_print_t ahc_sxfrctl0_print;
|
||||||
ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_sxfrctl1_print;
|
|
||||||
#else
|
|
||||||
#define ahc_sxfrctl1_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SXFRCTL1", 0x02, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scsisigo_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scsisigo_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCSISIGO", 0x03, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_scsisigi_print;
|
ahc_reg_print_t ahc_scsisigi_print;
|
||||||
#else
|
#else
|
||||||
|
@ -54,55 +40,6 @@ ahc_reg_print_t ahc_scsirate_print;
|
||||||
ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scsiid_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scsiid_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCSIID", 0x05, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scsidatl_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scsidatl_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCSIDATL", 0x06, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scsidath_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scsidath_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCSIDATH", 0x07, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_stcnt_print;
|
|
||||||
#else
|
|
||||||
#define ahc_stcnt_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "STCNT", 0x08, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_optionmode_print;
|
|
||||||
#else
|
|
||||||
#define ahc_optionmode_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "OPTIONMODE", 0x08, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_targcrccnt_print;
|
|
||||||
#else
|
|
||||||
#define ahc_targcrccnt_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "TARGCRCCNT", 0x0a, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_clrsint0_print;
|
|
||||||
#else
|
|
||||||
#define ahc_clrsint0_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CLRSINT0", 0x0b, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_sstat0_print;
|
ahc_reg_print_t ahc_sstat0_print;
|
||||||
#else
|
#else
|
||||||
|
@ -110,13 +47,6 @@ ahc_reg_print_t ahc_sstat0_print;
|
||||||
ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_clrsint1_print;
|
|
||||||
#else
|
|
||||||
#define ahc_clrsint1_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CLRSINT1", 0x0c, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_sstat1_print;
|
ahc_reg_print_t ahc_sstat1_print;
|
||||||
#else
|
#else
|
||||||
|
@ -138,13 +68,6 @@ ahc_reg_print_t ahc_sstat3_print;
|
||||||
ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scsiid_ultra2_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scsiid_ultra2_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCSIID_ULTRA2", 0x0f, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_simode0_print;
|
ahc_reg_print_t ahc_simode0_print;
|
||||||
#else
|
#else
|
||||||
|
@ -166,76 +89,6 @@ ahc_reg_print_t ahc_scsibusl_print;
|
||||||
ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SCSIBUSL", 0x12, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scsibush_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scsibush_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCSIBUSH", 0x13, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_sxfrctl2_print;
|
|
||||||
#else
|
|
||||||
#define ahc_sxfrctl2_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SXFRCTL2", 0x13, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_shaddr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_shaddr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SHADDR", 0x14, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_seltimer_print;
|
|
||||||
#else
|
|
||||||
#define ahc_seltimer_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SELTIMER", 0x18, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_selid_print;
|
|
||||||
#else
|
|
||||||
#define ahc_selid_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SELID", 0x19, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scamctl_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scamctl_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCAMCTL", 0x1a, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_targid_print;
|
|
||||||
#else
|
|
||||||
#define ahc_targid_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "TARGID", 0x1b, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_spiocap_print;
|
|
||||||
#else
|
|
||||||
#define ahc_spiocap_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SPIOCAP", 0x1b, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_brdctl_print;
|
|
||||||
#else
|
|
||||||
#define ahc_brdctl_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "BRDCTL", 0x1d, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_seectl_print;
|
|
||||||
#else
|
|
||||||
#define ahc_seectl_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SEECTL", 0x1e, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_sblkctl_print;
|
ahc_reg_print_t ahc_sblkctl_print;
|
||||||
#else
|
#else
|
||||||
|
@ -243,62 +96,6 @@ ahc_reg_print_t ahc_sblkctl_print;
|
||||||
ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SBLKCTL", 0x1f, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_busy_targets_print;
|
|
||||||
#else
|
|
||||||
#define ahc_busy_targets_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "BUSY_TARGETS", 0x20, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ultra_enb_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ultra_enb_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "ULTRA_ENB", 0x30, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_disc_dsb_print;
|
|
||||||
#else
|
|
||||||
#define ahc_disc_dsb_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DISC_DSB", 0x32, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_cmdsize_table_tail_print;
|
|
||||||
#else
|
|
||||||
#define ahc_cmdsize_table_tail_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CMDSIZE_TABLE_TAIL", 0x34, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_mwi_residual_print;
|
|
||||||
#else
|
|
||||||
#define ahc_mwi_residual_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "MWI_RESIDUAL", 0x38, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_next_queued_scb_print;
|
|
||||||
#else
|
|
||||||
#define ahc_next_queued_scb_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB", 0x39, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_msg_out_print;
|
|
||||||
#else
|
|
||||||
#define ahc_msg_out_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "MSG_OUT", 0x3a, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_dmaparams_print;
|
|
||||||
#else
|
|
||||||
#define ahc_dmaparams_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DMAPARAMS", 0x3b, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_seq_flags_print;
|
ahc_reg_print_t ahc_seq_flags_print;
|
||||||
#else
|
#else
|
||||||
|
@ -306,20 +103,6 @@ ahc_reg_print_t ahc_seq_flags_print;
|
||||||
ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SEQ_FLAGS", 0x3c, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_saved_scsiid_print;
|
|
||||||
#else
|
|
||||||
#define ahc_saved_scsiid_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SAVED_SCSIID", 0x3d, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_saved_lun_print;
|
|
||||||
#else
|
|
||||||
#define ahc_saved_lun_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SAVED_LUN", 0x3e, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_lastphase_print;
|
ahc_reg_print_t ahc_lastphase_print;
|
||||||
#else
|
#else
|
||||||
|
@ -327,153 +110,6 @@ ahc_reg_print_t ahc_lastphase_print;
|
||||||
ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "LASTPHASE", 0x3f, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_waiting_scbh_print;
|
|
||||||
#else
|
|
||||||
#define ahc_waiting_scbh_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "WAITING_SCBH", 0x40, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_disconnected_scbh_print;
|
|
||||||
#else
|
|
||||||
#define ahc_disconnected_scbh_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DISCONNECTED_SCBH", 0x41, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_free_scbh_print;
|
|
||||||
#else
|
|
||||||
#define ahc_free_scbh_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "FREE_SCBH", 0x42, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_complete_scbh_print;
|
|
||||||
#else
|
|
||||||
#define ahc_complete_scbh_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "COMPLETE_SCBH", 0x43, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_hscb_addr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_hscb_addr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "HSCB_ADDR", 0x44, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_shared_data_addr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_shared_data_addr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SHARED_DATA_ADDR", 0x48, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_kernel_qinpos_print;
|
|
||||||
#else
|
|
||||||
#define ahc_kernel_qinpos_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "KERNEL_QINPOS", 0x4c, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_qinpos_print;
|
|
||||||
#else
|
|
||||||
#define ahc_qinpos_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "QINPOS", 0x4d, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_qoutpos_print;
|
|
||||||
#else
|
|
||||||
#define ahc_qoutpos_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "QOUTPOS", 0x4e, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_kernel_tqinpos_print;
|
|
||||||
#else
|
|
||||||
#define ahc_kernel_tqinpos_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "KERNEL_TQINPOS", 0x4f, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_tqinpos_print;
|
|
||||||
#else
|
|
||||||
#define ahc_tqinpos_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "TQINPOS", 0x50, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_arg_1_print;
|
|
||||||
#else
|
|
||||||
#define ahc_arg_1_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "ARG_1", 0x51, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_arg_2_print;
|
|
||||||
#else
|
|
||||||
#define ahc_arg_2_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "ARG_2", 0x52, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_last_msg_print;
|
|
||||||
#else
|
|
||||||
#define ahc_last_msg_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "LAST_MSG", 0x53, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scsiseq_template_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scsiseq_template_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCSISEQ_TEMPLATE", 0x54, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ha_274_biosglobal_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ha_274_biosglobal_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "HA_274_BIOSGLOBAL", 0x56, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_seq_flags2_print;
|
|
||||||
#else
|
|
||||||
#define ahc_seq_flags2_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SEQ_FLAGS2", 0x57, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scsiconf_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scsiconf_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCSICONF", 0x5a, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_intdef_print;
|
|
||||||
#else
|
|
||||||
#define ahc_intdef_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "INTDEF", 0x5c, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_hostconf_print;
|
|
||||||
#else
|
|
||||||
#define ahc_hostconf_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "HOSTCONF", 0x5d, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ha_274_biosctrl_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ha_274_biosctrl_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "HA_274_BIOSCTRL", 0x5f, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_seqctl_print;
|
ahc_reg_print_t ahc_seqctl_print;
|
||||||
#else
|
#else
|
||||||
|
@ -481,111 +117,6 @@ ahc_reg_print_t ahc_seqctl_print;
|
||||||
ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SEQCTL", 0x60, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_seqram_print;
|
|
||||||
#else
|
|
||||||
#define ahc_seqram_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SEQRAM", 0x61, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_seqaddr0_print;
|
|
||||||
#else
|
|
||||||
#define ahc_seqaddr0_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SEQADDR0", 0x62, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_seqaddr1_print;
|
|
||||||
#else
|
|
||||||
#define ahc_seqaddr1_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SEQADDR1", 0x63, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_accum_print;
|
|
||||||
#else
|
|
||||||
#define ahc_accum_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "ACCUM", 0x64, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_sindex_print;
|
|
||||||
#else
|
|
||||||
#define ahc_sindex_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SINDEX", 0x65, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_dindex_print;
|
|
||||||
#else
|
|
||||||
#define ahc_dindex_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DINDEX", 0x66, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_allones_print;
|
|
||||||
#else
|
|
||||||
#define ahc_allones_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "ALLONES", 0x69, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_allzeros_print;
|
|
||||||
#else
|
|
||||||
#define ahc_allzeros_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "ALLZEROS", 0x6a, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_none_print;
|
|
||||||
#else
|
|
||||||
#define ahc_none_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "NONE", 0x6a, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_flags_print;
|
|
||||||
#else
|
|
||||||
#define ahc_flags_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "FLAGS", 0x6b, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_sindir_print;
|
|
||||||
#else
|
|
||||||
#define ahc_sindir_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SINDIR", 0x6c, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_dindir_print;
|
|
||||||
#else
|
|
||||||
#define ahc_dindir_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DINDIR", 0x6d, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_function1_print;
|
|
||||||
#else
|
|
||||||
#define ahc_function1_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "FUNCTION1", 0x6e, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_stack_print;
|
|
||||||
#else
|
|
||||||
#define ahc_stack_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "STACK", 0x6f, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_targ_offset_print;
|
|
||||||
#else
|
|
||||||
#define ahc_targ_offset_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "TARG_OFFSET", 0x70, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_sram_base_print;
|
ahc_reg_print_t ahc_sram_base_print;
|
||||||
#else
|
#else
|
||||||
|
@ -593,97 +124,6 @@ ahc_reg_print_t ahc_sram_base_print;
|
||||||
ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SRAM_BASE", 0x70, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_bctl_print;
|
|
||||||
#else
|
|
||||||
#define ahc_bctl_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "BCTL", 0x84, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_dscommand0_print;
|
|
||||||
#else
|
|
||||||
#define ahc_dscommand0_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DSCOMMAND0", 0x84, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_bustime_print;
|
|
||||||
#else
|
|
||||||
#define ahc_bustime_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "BUSTIME", 0x85, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_dscommand1_print;
|
|
||||||
#else
|
|
||||||
#define ahc_dscommand1_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DSCOMMAND1", 0x85, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_busspd_print;
|
|
||||||
#else
|
|
||||||
#define ahc_busspd_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "BUSSPD", 0x86, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_hs_mailbox_print;
|
|
||||||
#else
|
|
||||||
#define ahc_hs_mailbox_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "HS_MAILBOX", 0x86, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_dspcistatus_print;
|
|
||||||
#else
|
|
||||||
#define ahc_dspcistatus_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DSPCISTATUS", 0x86, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_hcntrl_print;
|
|
||||||
#else
|
|
||||||
#define ahc_hcntrl_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "HCNTRL", 0x87, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_haddr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_haddr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "HADDR", 0x88, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_hcnt_print;
|
|
||||||
#else
|
|
||||||
#define ahc_hcnt_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "HCNT", 0x8c, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scbptr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scbptr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCBPTR", 0x90, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_intstat_print;
|
|
||||||
#else
|
|
||||||
#define ahc_intstat_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "INTSTAT", 0x91, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_clrint_print;
|
|
||||||
#else
|
|
||||||
#define ahc_clrint_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CLRINT", 0x92, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_error_print;
|
ahc_reg_print_t ahc_error_print;
|
||||||
#else
|
#else
|
||||||
|
@ -705,69 +145,6 @@ ahc_reg_print_t ahc_dfstatus_print;
|
||||||
ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "DFSTATUS", 0x94, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_dfwaddr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_dfwaddr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DFWADDR", 0x95, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_dfraddr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_dfraddr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DFRADDR", 0x97, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_dfdat_print;
|
|
||||||
#else
|
|
||||||
#define ahc_dfdat_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DFDAT", 0x99, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scbcnt_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scbcnt_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCBCNT", 0x9a, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_qinfifo_print;
|
|
||||||
#else
|
|
||||||
#define ahc_qinfifo_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "QINFIFO", 0x9b, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_qincnt_print;
|
|
||||||
#else
|
|
||||||
#define ahc_qincnt_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "QINCNT", 0x9c, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_qoutfifo_print;
|
|
||||||
#else
|
|
||||||
#define ahc_qoutfifo_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "QOUTFIFO", 0x9d, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_crccontrol1_print;
|
|
||||||
#else
|
|
||||||
#define ahc_crccontrol1_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CRCCONTROL1", 0x9d, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_qoutcnt_print;
|
|
||||||
#else
|
|
||||||
#define ahc_qoutcnt_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "QOUTCNT", 0x9e, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_scsiphase_print;
|
ahc_reg_print_t ahc_scsiphase_print;
|
||||||
#else
|
#else
|
||||||
|
@ -775,13 +152,6 @@ ahc_reg_print_t ahc_scsiphase_print;
|
||||||
ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SCSIPHASE", 0x9e, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_sfunct_print;
|
|
||||||
#else
|
|
||||||
#define ahc_sfunct_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SFUNCT", 0x9f, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_scb_base_print;
|
ahc_reg_print_t ahc_scb_base_print;
|
||||||
#else
|
#else
|
||||||
|
@ -789,69 +159,6 @@ ahc_reg_print_t ahc_scb_base_print;
|
||||||
ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SCB_BASE", 0xa0, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_cdb_ptr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_cdb_ptr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_CDB_PTR", 0xa0, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_residual_sgptr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_residual_sgptr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR", 0xa4, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_scsi_status_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_scsi_status_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_SCSI_STATUS", 0xa8, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_target_phases_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_target_phases_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_TARGET_PHASES", 0xa9, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_target_data_dir_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_target_data_dir_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 0xaa, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_target_itag_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_target_itag_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_TARGET_ITAG", 0xab, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_dataptr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_dataptr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_DATAPTR", 0xac, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_datacnt_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_datacnt_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_DATACNT", 0xb0, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_sgptr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_sgptr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_SGPTR", 0xb4, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
#if AIC_DEBUG_REGISTERS
|
||||||
ahc_reg_print_t ahc_scb_control_print;
|
ahc_reg_print_t ahc_scb_control_print;
|
||||||
#else
|
#else
|
||||||
|
@ -880,188 +187,6 @@ ahc_reg_print_t ahc_scb_tag_print;
|
||||||
ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap)
|
ahc_print_register(NULL, 0, "SCB_TAG", 0xbb, regvalue, cur_col, wrap)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_cdb_len_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_cdb_len_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_CDB_LEN", 0xbc, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_scsirate_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_scsirate_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_SCSIRATE", 0xbd, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_scsioffset_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_scsioffset_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_SCSIOFFSET", 0xbe, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_next_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_next_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_NEXT", 0xbf, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_64_spare_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_64_spare_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_64_SPARE", 0xc0, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_seectl_2840_print;
|
|
||||||
#else
|
|
||||||
#define ahc_seectl_2840_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SEECTL_2840", 0xc0, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_status_2840_print;
|
|
||||||
#else
|
|
||||||
#define ahc_status_2840_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "STATUS_2840", 0xc1, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scb_64_btt_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scb_64_btt_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCB_64_BTT", 0xd0, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_cchaddr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_cchaddr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CCHADDR", 0xe0, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_cchcnt_print;
|
|
||||||
#else
|
|
||||||
#define ahc_cchcnt_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CCHCNT", 0xe8, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ccsgram_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ccsgram_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CCSGRAM", 0xe9, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ccsgaddr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ccsgaddr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CCSGADDR", 0xea, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ccsgctl_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ccsgctl_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CCSGCTL", 0xeb, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ccscbram_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ccscbram_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CCSCBRAM", 0xec, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ccscbaddr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ccscbaddr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CCSCBADDR", 0xed, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ccscbctl_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ccscbctl_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CCSCBCTL", 0xee, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ccscbcnt_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ccscbcnt_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CCSCBCNT", 0xef, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_scbbaddr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_scbbaddr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SCBBADDR", 0xf0, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_ccscbptr_print;
|
|
||||||
#else
|
|
||||||
#define ahc_ccscbptr_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "CCSCBPTR", 0xf1, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_hnscb_qoff_print;
|
|
||||||
#else
|
|
||||||
#define ahc_hnscb_qoff_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "HNSCB_QOFF", 0xf4, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_snscb_qoff_print;
|
|
||||||
#else
|
|
||||||
#define ahc_snscb_qoff_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SNSCB_QOFF", 0xf6, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_sdscb_qoff_print;
|
|
||||||
#else
|
|
||||||
#define ahc_sdscb_qoff_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SDSCB_QOFF", 0xf8, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_qoff_ctlsta_print;
|
|
||||||
#else
|
|
||||||
#define ahc_qoff_ctlsta_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "QOFF_CTLSTA", 0xfa, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_dff_thrsh_print;
|
|
||||||
#else
|
|
||||||
#define ahc_dff_thrsh_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "DFF_THRSH", 0xfb, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_sg_cache_shadow_print;
|
|
||||||
#else
|
|
||||||
#define ahc_sg_cache_shadow_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SG_CACHE_SHADOW", 0xfc, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if AIC_DEBUG_REGISTERS
|
|
||||||
ahc_reg_print_t ahc_sg_cache_pre_print;
|
|
||||||
#else
|
|
||||||
#define ahc_sg_cache_pre_print(regvalue, cur_col, wrap) \
|
|
||||||
ahc_print_register(NULL, 0, "SG_CACHE_PRE", 0xfc, regvalue, cur_col, wrap)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#define SCSISEQ 0x00
|
#define SCSISEQ 0x00
|
||||||
#define TEMODE 0x80
|
#define TEMODE 0x80
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -147,6 +147,8 @@ void yyerror(const char *string);
|
||||||
|
|
||||||
%token T_ACCESS_MODE
|
%token T_ACCESS_MODE
|
||||||
|
|
||||||
|
%token T_DONT_GENERATE_DEBUG_CODE
|
||||||
|
|
||||||
%token T_MODES
|
%token T_MODES
|
||||||
|
|
||||||
%token T_DEFINE
|
%token T_DEFINE
|
||||||
|
@ -357,6 +359,7 @@ reg_attribute:
|
||||||
| size
|
| size
|
||||||
| count
|
| count
|
||||||
| access_mode
|
| access_mode
|
||||||
|
| dont_generate_debug_code
|
||||||
| modes
|
| modes
|
||||||
| field_defn
|
| field_defn
|
||||||
| enum_defn
|
| enum_defn
|
||||||
|
@ -410,6 +413,13 @@ access_mode:
|
||||||
}
|
}
|
||||||
;
|
;
|
||||||
|
|
||||||
|
dont_generate_debug_code:
|
||||||
|
T_DONT_GENERATE_DEBUG_CODE
|
||||||
|
{
|
||||||
|
cur_symbol->dont_generate_debug_code = 1;
|
||||||
|
}
|
||||||
|
;
|
||||||
|
|
||||||
modes:
|
modes:
|
||||||
T_MODES mode_list
|
T_MODES mode_list
|
||||||
{
|
{
|
||||||
|
|
|
@ -164,6 +164,7 @@ download { return T_DOWNLOAD; }
|
||||||
address { return T_ADDRESS; }
|
address { return T_ADDRESS; }
|
||||||
count { return T_COUNT; }
|
count { return T_COUNT; }
|
||||||
access_mode { return T_ACCESS_MODE; }
|
access_mode { return T_ACCESS_MODE; }
|
||||||
|
dont_generate_debug_code { return T_DONT_GENERATE_DEBUG_CODE; }
|
||||||
modes { return T_MODES; }
|
modes { return T_MODES; }
|
||||||
RW|RO|WO {
|
RW|RO|WO {
|
||||||
if (strcmp(yytext, "RW") == 0)
|
if (strcmp(yytext, "RW") == 0)
|
||||||
|
|
|
@ -539,6 +539,9 @@ symtable_dump(FILE *ofile, FILE *dfile)
|
||||||
aic_print_include(dfile, stock_include_file);
|
aic_print_include(dfile, stock_include_file);
|
||||||
SLIST_FOREACH(curnode, ®isters, links) {
|
SLIST_FOREACH(curnode, ®isters, links) {
|
||||||
|
|
||||||
|
if (curnode->symbol->dont_generate_debug_code)
|
||||||
|
continue;
|
||||||
|
|
||||||
switch(curnode->symbol->type) {
|
switch(curnode->symbol->type) {
|
||||||
case REGISTER:
|
case REGISTER:
|
||||||
case SCBLOC:
|
case SCBLOC:
|
||||||
|
|
|
@ -138,6 +138,7 @@ typedef struct symbol {
|
||||||
struct cond_info *condinfo;
|
struct cond_info *condinfo;
|
||||||
struct macro_info *macroinfo;
|
struct macro_info *macroinfo;
|
||||||
} info;
|
} info;
|
||||||
|
int dont_generate_debug_code;
|
||||||
} symbol_t;
|
} symbol_t;
|
||||||
|
|
||||||
typedef struct symbol_ref {
|
typedef struct symbol_ref {
|
||||||
|
|
|
@ -401,6 +401,9 @@ static int check_ownership(struct scsi_device *sdev, struct rdac_dh_data *h)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (h->lun_state == RDAC_LUN_UNOWNED)
|
||||||
|
h->state = RDAC_STATE_PASSIVE;
|
||||||
|
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -2456,20 +2456,14 @@ static ssize_t ipr_read_trace(struct kobject *kobj,
|
||||||
struct Scsi_Host *shost = class_to_shost(dev);
|
struct Scsi_Host *shost = class_to_shost(dev);
|
||||||
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
|
struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
|
||||||
unsigned long lock_flags = 0;
|
unsigned long lock_flags = 0;
|
||||||
int size = IPR_TRACE_SIZE;
|
ssize_t ret;
|
||||||
char *src = (char *)ioa_cfg->trace;
|
|
||||||
|
|
||||||
if (off > size)
|
|
||||||
return 0;
|
|
||||||
if (off + count > size) {
|
|
||||||
size -= off;
|
|
||||||
count = size;
|
|
||||||
}
|
|
||||||
|
|
||||||
spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
|
spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
|
||||||
memcpy(buf, &src[off], count);
|
ret = memory_read_from_buffer(buf, count, &off, ioa_cfg->trace,
|
||||||
|
IPR_TRACE_SIZE);
|
||||||
spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
|
spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
|
||||||
return count;
|
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct bin_attribute ipr_trace_attr = {
|
static struct bin_attribute ipr_trace_attr = {
|
||||||
|
|
|
@ -529,6 +529,14 @@ static void scsi_single_lun_run(struct scsi_device *current_sdev)
|
||||||
spin_unlock_irqrestore(shost->host_lock, flags);
|
spin_unlock_irqrestore(shost->host_lock, flags);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline int scsi_device_is_busy(struct scsi_device *sdev)
|
||||||
|
{
|
||||||
|
if (sdev->device_busy >= sdev->queue_depth || sdev->device_blocked)
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
static inline int scsi_target_is_busy(struct scsi_target *starget)
|
static inline int scsi_target_is_busy(struct scsi_target *starget)
|
||||||
{
|
{
|
||||||
return ((starget->can_queue > 0 &&
|
return ((starget->can_queue > 0 &&
|
||||||
|
@ -536,6 +544,15 @@ static inline int scsi_target_is_busy(struct scsi_target *starget)
|
||||||
starget->target_blocked);
|
starget->target_blocked);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline int scsi_host_is_busy(struct Scsi_Host *shost)
|
||||||
|
{
|
||||||
|
if ((shost->can_queue > 0 && shost->host_busy >= shost->can_queue) ||
|
||||||
|
shost->host_blocked || shost->host_self_blocked)
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Function: scsi_run_queue()
|
* Function: scsi_run_queue()
|
||||||
*
|
*
|
||||||
|
@ -558,11 +575,7 @@ static void scsi_run_queue(struct request_queue *q)
|
||||||
scsi_single_lun_run(sdev);
|
scsi_single_lun_run(sdev);
|
||||||
|
|
||||||
spin_lock_irqsave(shost->host_lock, flags);
|
spin_lock_irqsave(shost->host_lock, flags);
|
||||||
while (!list_empty(&shost->starved_list) &&
|
while (!list_empty(&shost->starved_list) && !scsi_host_is_busy(shost)) {
|
||||||
!shost->host_blocked && !shost->host_self_blocked &&
|
|
||||||
!((shost->can_queue > 0) &&
|
|
||||||
(shost->host_busy >= shost->can_queue))) {
|
|
||||||
|
|
||||||
int flagset;
|
int flagset;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -1348,8 +1361,6 @@ int scsi_prep_fn(struct request_queue *q, struct request *req)
|
||||||
static inline int scsi_dev_queue_ready(struct request_queue *q,
|
static inline int scsi_dev_queue_ready(struct request_queue *q,
|
||||||
struct scsi_device *sdev)
|
struct scsi_device *sdev)
|
||||||
{
|
{
|
||||||
if (sdev->device_busy >= sdev->queue_depth)
|
|
||||||
return 0;
|
|
||||||
if (sdev->device_busy == 0 && sdev->device_blocked) {
|
if (sdev->device_busy == 0 && sdev->device_blocked) {
|
||||||
/*
|
/*
|
||||||
* unblock after device_blocked iterates to zero
|
* unblock after device_blocked iterates to zero
|
||||||
|
@ -1363,7 +1374,7 @@ static inline int scsi_dev_queue_ready(struct request_queue *q,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (sdev->device_blocked)
|
if (scsi_device_is_busy(sdev))
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
return 1;
|
return 1;
|
||||||
|
@ -1440,8 +1451,7 @@ static inline int scsi_host_queue_ready(struct request_queue *q,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if ((shost->can_queue > 0 && shost->host_busy >= shost->can_queue) ||
|
if (scsi_host_is_busy(shost)) {
|
||||||
shost->host_blocked || shost->host_self_blocked) {
|
|
||||||
if (list_empty(&sdev->starved_entry))
|
if (list_empty(&sdev->starved_entry))
|
||||||
list_add_tail(&sdev->starved_entry, &shost->starved_list);
|
list_add_tail(&sdev->starved_entry, &shost->starved_list);
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -1454,6 +1464,37 @@ static inline int scsi_host_queue_ready(struct request_queue *q,
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Busy state exporting function for request stacking drivers.
|
||||||
|
*
|
||||||
|
* For efficiency, no lock is taken to check the busy state of
|
||||||
|
* shost/starget/sdev, since the returned value is not guaranteed and
|
||||||
|
* may be changed after request stacking drivers call the function,
|
||||||
|
* regardless of taking lock or not.
|
||||||
|
*
|
||||||
|
* When scsi can't dispatch I/Os anymore and needs to kill I/Os
|
||||||
|
* (e.g. !sdev), scsi needs to return 'not busy'.
|
||||||
|
* Otherwise, request stacking drivers may hold requests forever.
|
||||||
|
*/
|
||||||
|
static int scsi_lld_busy(struct request_queue *q)
|
||||||
|
{
|
||||||
|
struct scsi_device *sdev = q->queuedata;
|
||||||
|
struct Scsi_Host *shost;
|
||||||
|
struct scsi_target *starget;
|
||||||
|
|
||||||
|
if (!sdev)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
shost = sdev->host;
|
||||||
|
starget = scsi_target(sdev);
|
||||||
|
|
||||||
|
if (scsi_host_in_recovery(shost) || scsi_host_is_busy(shost) ||
|
||||||
|
scsi_target_is_busy(starget) || scsi_device_is_busy(sdev))
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Kill a request for a dead device
|
* Kill a request for a dead device
|
||||||
*/
|
*/
|
||||||
|
@ -1757,6 +1798,7 @@ struct request_queue *scsi_alloc_queue(struct scsi_device *sdev)
|
||||||
blk_queue_prep_rq(q, scsi_prep_fn);
|
blk_queue_prep_rq(q, scsi_prep_fn);
|
||||||
blk_queue_softirq_done(q, scsi_softirq_done);
|
blk_queue_softirq_done(q, scsi_softirq_done);
|
||||||
blk_queue_rq_timed_out(q, scsi_times_out);
|
blk_queue_rq_timed_out(q, scsi_times_out);
|
||||||
|
blk_queue_lld_busy(q, scsi_lld_busy);
|
||||||
return q;
|
return q;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2105,23 +2147,22 @@ scsi_test_unit_ready(struct scsi_device *sdev, int timeout, int retries,
|
||||||
do {
|
do {
|
||||||
result = scsi_execute_req(sdev, cmd, DMA_NONE, NULL, 0, sshdr,
|
result = scsi_execute_req(sdev, cmd, DMA_NONE, NULL, 0, sshdr,
|
||||||
timeout, retries);
|
timeout, retries);
|
||||||
} while ((driver_byte(result) & DRIVER_SENSE) &&
|
if (sdev->removable && scsi_sense_valid(sshdr) &&
|
||||||
sshdr && sshdr->sense_key == UNIT_ATTENTION &&
|
sshdr->sense_key == UNIT_ATTENTION)
|
||||||
--retries);
|
sdev->changed = 1;
|
||||||
|
} while (scsi_sense_valid(sshdr) &&
|
||||||
|
sshdr->sense_key == UNIT_ATTENTION && --retries);
|
||||||
|
|
||||||
if (!sshdr)
|
if (!sshdr)
|
||||||
/* could not allocate sense buffer, so can't process it */
|
/* could not allocate sense buffer, so can't process it */
|
||||||
return result;
|
return result;
|
||||||
|
|
||||||
if ((driver_byte(result) & DRIVER_SENSE) && sdev->removable) {
|
if (sdev->removable && scsi_sense_valid(sshdr) &&
|
||||||
|
(sshdr->sense_key == UNIT_ATTENTION ||
|
||||||
if ((scsi_sense_valid(sshdr)) &&
|
sshdr->sense_key == NOT_READY)) {
|
||||||
((sshdr->sense_key == UNIT_ATTENTION) ||
|
|
||||||
(sshdr->sense_key == NOT_READY))) {
|
|
||||||
sdev->changed = 1;
|
sdev->changed = 1;
|
||||||
result = 0;
|
result = 0;
|
||||||
}
|
}
|
||||||
}
|
|
||||||
if (!sshdr_external)
|
if (!sshdr_external)
|
||||||
kfree(sshdr);
|
kfree(sshdr);
|
||||||
return result;
|
return result;
|
||||||
|
|
|
@ -205,16 +205,13 @@ static struct notifier_block scsi_netlink_notifier = {
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
/**
|
/*
|
||||||
* GENERIC SCSI transport receive and event handlers
|
* GENERIC SCSI transport receive and event handlers
|
||||||
**/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* scsi_generic_msg_handler - receive message handler for GENERIC transport
|
* scsi_generic_msg_handler - receive message handler for GENERIC transport messages
|
||||||
* messages
|
|
||||||
*
|
|
||||||
* @skb: socket receive buffer
|
* @skb: socket receive buffer
|
||||||
*
|
|
||||||
**/
|
**/
|
||||||
static int
|
static int
|
||||||
scsi_generic_msg_handler(struct sk_buff *skb)
|
scsi_generic_msg_handler(struct sk_buff *skb)
|
||||||
|
|
|
@ -1049,7 +1049,6 @@ static int sd_done(struct scsi_cmnd *SCpnt)
|
||||||
good_bytes = sd_completed_bytes(SCpnt);
|
good_bytes = sd_completed_bytes(SCpnt);
|
||||||
break;
|
break;
|
||||||
case RECOVERED_ERROR:
|
case RECOVERED_ERROR:
|
||||||
case NO_SENSE:
|
|
||||||
/* Inform the user, but make sure that it's not treated
|
/* Inform the user, but make sure that it's not treated
|
||||||
* as a hard error.
|
* as a hard error.
|
||||||
*/
|
*/
|
||||||
|
@ -1058,6 +1057,15 @@ static int sd_done(struct scsi_cmnd *SCpnt)
|
||||||
memset(SCpnt->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
|
memset(SCpnt->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
|
||||||
good_bytes = scsi_bufflen(SCpnt);
|
good_bytes = scsi_bufflen(SCpnt);
|
||||||
break;
|
break;
|
||||||
|
case NO_SENSE:
|
||||||
|
/* This indicates a false check condition, so ignore it. An
|
||||||
|
* unknown amount of data was transferred so treat it as an
|
||||||
|
* error.
|
||||||
|
*/
|
||||||
|
scsi_print_sense("sd", SCpnt);
|
||||||
|
SCpnt->result = 0;
|
||||||
|
memset(SCpnt->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
|
||||||
|
break;
|
||||||
case ABORTED_COMMAND:
|
case ABORTED_COMMAND:
|
||||||
if (sshdr.asc == 0x10) { /* DIF: Disk detected corruption */
|
if (sshdr.asc == 0x10) { /* DIF: Disk detected corruption */
|
||||||
scsi_print_result(SCpnt);
|
scsi_print_result(SCpnt);
|
||||||
|
@ -1071,15 +1079,6 @@ static int sd_done(struct scsi_cmnd *SCpnt)
|
||||||
scsi_print_sense("sd", SCpnt);
|
scsi_print_sense("sd", SCpnt);
|
||||||
good_bytes = sd_completed_bytes(SCpnt);
|
good_bytes = sd_completed_bytes(SCpnt);
|
||||||
}
|
}
|
||||||
if (!scsi_device_protection(SCpnt->device) &&
|
|
||||||
SCpnt->device->use_10_for_rw &&
|
|
||||||
(SCpnt->cmnd[0] == READ_10 ||
|
|
||||||
SCpnt->cmnd[0] == WRITE_10))
|
|
||||||
SCpnt->device->use_10_for_rw = 0;
|
|
||||||
if (SCpnt->device->use_10_for_ms &&
|
|
||||||
(SCpnt->cmnd[0] == MODE_SENSE_10 ||
|
|
||||||
SCpnt->cmnd[0] == MODE_SELECT_10))
|
|
||||||
SCpnt->device->use_10_for_ms = 0;
|
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
|
@ -1432,7 +1431,7 @@ got_data:
|
||||||
|
|
||||||
{
|
{
|
||||||
char cap_str_2[10], cap_str_10[10];
|
char cap_str_2[10], cap_str_10[10];
|
||||||
u64 sz = sdkp->capacity << ffz(~sector_size);
|
u64 sz = (u64)sdkp->capacity << ilog2(sector_size);
|
||||||
|
|
||||||
string_get_size(sz, STRING_UNITS_2, cap_str_2,
|
string_get_size(sz, STRING_UNITS_2, cap_str_2,
|
||||||
sizeof(cap_str_2));
|
sizeof(cap_str_2));
|
||||||
|
|
|
@ -213,7 +213,7 @@ static int __devinit esp_sun3x_probe(struct platform_device *dev)
|
||||||
esp->ops = &sun3x_esp_ops;
|
esp->ops = &sun3x_esp_ops;
|
||||||
|
|
||||||
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
||||||
if (!res && !res->start)
|
if (!res || !res->start)
|
||||||
goto fail_unlink;
|
goto fail_unlink;
|
||||||
|
|
||||||
esp->regs = ioremap_nocache(res->start, 0x20);
|
esp->regs = ioremap_nocache(res->start, 0x20);
|
||||||
|
@ -221,7 +221,7 @@ static int __devinit esp_sun3x_probe(struct platform_device *dev)
|
||||||
goto fail_unmap_regs;
|
goto fail_unmap_regs;
|
||||||
|
|
||||||
res = platform_get_resource(dev, IORESOURCE_MEM, 1);
|
res = platform_get_resource(dev, IORESOURCE_MEM, 1);
|
||||||
if (!res && !res->start)
|
if (!res || !res->start)
|
||||||
goto fail_unmap_regs;
|
goto fail_unmap_regs;
|
||||||
|
|
||||||
esp->dma_regs = ioremap_nocache(res->start, 0x10);
|
esp->dma_regs = ioremap_nocache(res->start, 0x10);
|
||||||
|
|
|
@ -23,7 +23,7 @@
|
||||||
int string_get_size(u64 size, const enum string_size_units units,
|
int string_get_size(u64 size, const enum string_size_units units,
|
||||||
char *buf, int len)
|
char *buf, int len)
|
||||||
{
|
{
|
||||||
const char *units_10[] = { "B", "KB", "MB", "GB", "TB", "PB",
|
const char *units_10[] = { "B", "kB", "MB", "GB", "TB", "PB",
|
||||||
"EB", "ZB", "YB", NULL};
|
"EB", "ZB", "YB", NULL};
|
||||||
const char *units_2[] = {"B", "KiB", "MiB", "GiB", "TiB", "PiB",
|
const char *units_2[] = {"B", "KiB", "MiB", "GiB", "TiB", "PiB",
|
||||||
"EiB", "ZiB", "YiB", NULL };
|
"EiB", "ZiB", "YiB", NULL };
|
||||||
|
@ -31,7 +31,7 @@ int string_get_size(u64 size, const enum string_size_units units,
|
||||||
[STRING_UNITS_10] = units_10,
|
[STRING_UNITS_10] = units_10,
|
||||||
[STRING_UNITS_2] = units_2,
|
[STRING_UNITS_2] = units_2,
|
||||||
};
|
};
|
||||||
const int divisor[] = {
|
const unsigned int divisor[] = {
|
||||||
[STRING_UNITS_10] = 1000,
|
[STRING_UNITS_10] = 1000,
|
||||||
[STRING_UNITS_2] = 1024,
|
[STRING_UNITS_2] = 1024,
|
||||||
};
|
};
|
||||||
|
@ -40,9 +40,12 @@ int string_get_size(u64 size, const enum string_size_units units,
|
||||||
char tmp[8];
|
char tmp[8];
|
||||||
|
|
||||||
tmp[0] = '\0';
|
tmp[0] = '\0';
|
||||||
|
i = 0;
|
||||||
for (i = 0; size > divisor[units] && units_str[units][i]; i++)
|
if (size >= divisor[units]) {
|
||||||
|
while (size >= divisor[units] && units_str[units][i]) {
|
||||||
remainder = do_div(size, divisor[units]);
|
remainder = do_div(size, divisor[units]);
|
||||||
|
i++;
|
||||||
|
}
|
||||||
|
|
||||||
sf_cap = size;
|
sf_cap = size;
|
||||||
for (j = 0; sf_cap*10 < 1000; j++)
|
for (j = 0; sf_cap*10 < 1000; j++)
|
||||||
|
@ -55,6 +58,7 @@ int string_get_size(u64 size, const enum string_size_units units,
|
||||||
(unsigned long long)remainder);
|
(unsigned long long)remainder);
|
||||||
tmp[j+1] = '\0';
|
tmp[j+1] = '\0';
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
snprintf(buf, len, "%lld%s %s", (unsigned long long)size,
|
snprintf(buf, len, "%lld%s %s", (unsigned long long)size,
|
||||||
tmp, units_str[units][i]);
|
tmp, units_str[units][i]);
|
||||||
|
|
Loading…
Reference in New Issue