ARM: net: bpf: fix zero right shift
The LSR instruction cannot be used to perform a zero right shift since a 0 as the immediate value (imm5) in the LSR instruction encoding means that a shift of 32 is perfomed. See DecodeIMMShift() in the ARM ARM. Make the JIT skip generation of the LSR if a zero-shift is requested. This was found using american fuzzy lop. Signed-off-by: Rabin Vincent <rabin@rab.in> Acked-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -756,7 +756,8 @@ load_ind:
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case BPF_ALU | BPF_RSH | BPF_K:
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case BPF_ALU | BPF_RSH | BPF_K:
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if (unlikely(k > 31))
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if (unlikely(k > 31))
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return -1;
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return -1;
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emit(ARM_LSR_I(r_A, r_A, k), ctx);
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if (k)
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emit(ARM_LSR_I(r_A, r_A, k), ctx);
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break;
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break;
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case BPF_ALU | BPF_RSH | BPF_X:
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case BPF_ALU | BPF_RSH | BPF_X:
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update_on_xread(ctx);
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update_on_xread(ctx);
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