dmaengine: edma: Merge map_dmach_to_queue into assign_channel_eventq
edma_assign_channel_eventq() is a wrapper around edma_map_dmach_to_queue() We can merge the content of the later so we will have only one function to be used for mapping channels to given eventq Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -391,22 +391,6 @@ static inline void clear_bits(int offset, int len, unsigned long *p)
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clear_bit(offset + (len - 1), p);
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clear_bit(offset + (len - 1), p);
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}
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}
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static void edma_map_dmach_to_queue(struct edma_chan *echan,
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enum dma_event_q queue_no)
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{
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struct edma_cc *ecc = echan->ecc;
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int channel = EDMA_CHAN_SLOT(echan->ch_num);
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int bit = (channel & 0x7) * 4;
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/* default to low priority queue */
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if (queue_no == EVENTQ_DEFAULT)
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queue_no = ecc->default_queue;
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queue_no &= 7;
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edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
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queue_no << bit);
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}
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static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
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static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
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int priority)
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int priority)
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{
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{
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@ -723,6 +707,25 @@ static void edma_clean_channel(struct edma_chan *echan)
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edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
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edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
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}
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}
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/* Move channel to a specific event queue */
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static void edma_assign_channel_eventq(struct edma_chan *echan,
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enum dma_event_q eventq_no)
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{
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struct edma_cc *ecc = echan->ecc;
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int channel = EDMA_CHAN_SLOT(echan->ch_num);
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int bit = (channel & 0x7) * 4;
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/* default to low priority queue */
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if (eventq_no == EVENTQ_DEFAULT)
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eventq_no = ecc->default_queue;
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if (eventq_no >= ecc->num_tc)
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return;
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eventq_no &= 7;
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edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
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eventq_no << bit);
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}
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static int edma_alloc_channel(struct edma_chan *echan,
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static int edma_alloc_channel(struct edma_chan *echan,
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enum dma_event_q eventq_no)
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enum dma_event_q eventq_no)
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{
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{
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@ -751,7 +754,7 @@ static int edma_alloc_channel(struct edma_chan *echan,
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edma_setup_interrupt(echan, true);
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edma_setup_interrupt(echan, true);
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edma_map_dmach_to_queue(echan, eventq_no);
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edma_assign_channel_eventq(echan, eventq_no);
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return 0;
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return 0;
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}
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}
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@ -764,21 +767,6 @@ static void edma_free_channel(struct edma_chan *echan)
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edma_setup_interrupt(echan, false);
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edma_setup_interrupt(echan, false);
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}
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}
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/* Move channel to a specific event queue */
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static void edma_assign_channel_eventq(struct edma_chan *echan,
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enum dma_event_q eventq_no)
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{
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struct edma_cc *ecc = echan->ecc;
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/* default to low priority queue */
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if (eventq_no == EVENTQ_DEFAULT)
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eventq_no = ecc->default_queue;
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if (eventq_no >= ecc->num_tc)
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return;
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edma_map_dmach_to_queue(echan, eventq_no);
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}
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static inline struct edma_cc *to_edma_cc(struct dma_device *d)
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static inline struct edma_cc *to_edma_cc(struct dma_device *d)
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{
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{
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return container_of(d, struct edma_cc, dma_slave);
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return container_of(d, struct edma_cc, dma_slave);
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@ -2154,8 +2142,8 @@ static int edma_probe(struct platform_device *pdev)
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for (i = 0; i < ecc->num_channels; i++) {
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for (i = 0; i < ecc->num_channels; i++) {
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/* Assign all channels to the default queue */
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/* Assign all channels to the default queue */
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edma_map_dmach_to_queue(&ecc->slave_chans[i],
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edma_assign_channel_eventq(&ecc->slave_chans[i],
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info->default_queue);
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info->default_queue);
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/* Set entry slot to the dummy slot */
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/* Set entry slot to the dummy slot */
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edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
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edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
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}
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}
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