OpenE2K
/
linux
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workarounds 

The Kconfig options for the PL310 errata workarounds do not use a
consistent naming scheme for either the config option or the bool
description.

This patch tidies up the options by ensuring that the bool descriptions
are prefixed with "PL310 errata:" and the config options are prefixed
with PL310_ERRATA_, making it much clearer in menuconfig as to what the
workarounds are for.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Will Deacon 2011-11-14 17:24:57 +01:00 committed by Russell King
parent 11ed0ba175
commit fa0ce4035d
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/Kconfig
View File

@ -1231,7 +1231,7 @@ config ARM_ERRATA_742231
capabilities of the processor. capabilities of the processor.
config PL310_ERRATA_588369 config PL310_ERRATA_588369
bool "Clean & Invalidate maintenance operations do not invalidate clean lines" bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
depends on CACHE_L2X0 depends on CACHE_L2X0
help help
The PL310 L2 cache controller implements three types of Clean & The PL310 L2 cache controller implements three types of Clean &
@ -1256,7 +1256,7 @@ config ARM_ERRATA_720789
entries regardless of the ASID. entries regardless of the ASID.
config PL310_ERRATA_727915 config PL310_ERRATA_727915
bool "Background Clean & Invalidate by Way operation can cause data corruption" bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
depends on CACHE_L2X0 depends on CACHE_L2X0
help help
PL310 implements the Clean & Invalidate by Way L2 cache maintenance PL310 implements the Clean & Invalidate by Way L2 cache maintenance
@ -1289,8 +1289,8 @@ config ARM_ERRATA_751472
operation is received by a CPU before the ICIALLUIS has completed, operation is received by a CPU before the ICIALLUIS has completed,
potentially leading to corrupted entries in the cache or TLB. potentially leading to corrupted entries in the cache or TLB.
config ARM_ERRATA_753970 config PL310_ERRATA_753970
bool "ARM errata: cache sync operation may be faulty" bool "PL310 errata: cache sync operation may be faulty"
depends on CACHE_PL310 depends on CACHE_PL310
help help
This option enables the workaround for the 753970 PL310 (r3p0) erratum. This option enables the workaround for the 753970 PL310 (r3p0) erratum.

2
arch/arm/mm/cache-l2x0.c
View File

@ -61,7 +61,7 @@ static inline void cache_sync(void)
{ {
void __iomem *base = l2x0_base; void __iomem *base = l2x0_base;
#ifdef CONFIG_ARM_ERRATA_753970 #ifdef CONFIG_PL310_ERRATA_753970
/* write to an unmmapped register */ /* write to an unmmapped register */
writel_relaxed(0, base + L2X0_DUMMY_REG); writel_relaxed(0, base + L2X0_DUMMY_REG);
#else #else