staging: brcm80211: removed static function declarations in 3 files
nicpci.c, srom.c and stf.c Reported-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Roland Vossen <rvossen@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Roland Vossen
Greg Kroah-Hartman
parent
5871e49260
commit
fa188ec8b6
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@ -215,24 +215,6 @@ struct pcicore_info {
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#define PCI_ERROR(args)
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#define PCIE_PUB(sih) ((sih)->buscoretype == PCIE_CORE_ID)
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/* routines to access mdio slave device registers */
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static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk);
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static int pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr,
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bool write, uint *val);
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static int pcie_mdiowrite(struct pcicore_info *pi, uint physmedia, uint readdr,
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uint val);
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static int pcie_mdioread(struct pcicore_info *pi, uint physmedia, uint readdr,
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uint *ret_val);
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static void pcie_extendL1timer(struct pcicore_info *pi, bool extend);
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static void pcie_clkreq_upd(struct pcicore_info *pi, uint state);
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static void pcie_war_aspm_clkreq(struct pcicore_info *pi);
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static void pcie_war_serdes(struct pcicore_info *pi);
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static void pcie_war_noplldown(struct pcicore_info *pi);
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static void pcie_war_polarity(struct pcicore_info *pi);
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static void pcie_war_pci_setup(struct pcicore_info *pi);
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#define PCIE_ASPM(sih) \
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((PCIE_PUB(sih)) && \
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(((sih)->buscorerev >= 3) && \
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@ -792,16 +792,45 @@ static const struct brcms_sromvar perpath_pci_sromvars[] = {
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static u8 srom_crc8_table[CRC8_TABLE_SIZE];
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static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off,
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struct brcms_varbuf *b);
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static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
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uint *count);
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static int sprom_read_pci(struct si_pub *sih, u16 *sprom,
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uint wordoff, u16 *buf, uint nwords, bool check_crc);
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static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz);
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/* Parse SROM and create name=value pairs. 'srom' points to
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* the SROM word array. 'off' specifies the offset of the
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* first word 'srom' points to, which should be either 0 or
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* SROM3_SWRG_OFF (full SROM or software region).
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*/
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static int initvars_table(char *start, char *end,
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char **vars, uint *count);
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static uint mask_shift(u16 mask)
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{
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uint i;
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for (i = 0; i < (sizeof(mask) << 3); i++) {
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if (mask & (1 << i))
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return i;
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}
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return 0;
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}
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static uint mask_width(u16 mask)
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{
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int i;
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for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
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if (mask & (1 << i))
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return (uint) (i - mask_shift(mask) + 1);
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}
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return 0;
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}
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static inline void ltoh16_buf(u16 *buf, unsigned int size)
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{
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size /= 2;
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while (size--)
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*(buf + size) = le16_to_cpu(*(buf + size));
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}
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static inline void htol16_buf(u16 *buf, unsigned int size)
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{
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size /= 2;
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while (size--)
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*(buf + size) = cpu_to_le16(*(buf + size));
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}
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/* Initialization of varbuf structure */
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static void varbuf_init(struct brcms_varbuf *b, char *buf, uint size)
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@ -864,167 +893,6 @@ static int varbuf_append(struct brcms_varbuf *b, const char *fmt, ...)
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return r;
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}
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/*
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* Initialize local vars from the right source for this platform.
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* Return 0 on success, nonzero on error.
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*/
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int srom_var_init(struct si_pub *sih, void *curmap, char **vars, uint *count)
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{
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uint len;
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len = 0;
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if (vars == NULL || count == NULL)
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return 0;
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*vars = NULL;
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*count = 0;
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if (curmap != NULL)
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return initvars_srom_pci(sih, curmap, vars, count);
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return -EINVAL;
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}
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static inline void ltoh16_buf(u16 *buf, unsigned int size)
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{
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size /= 2;
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while (size--)
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*(buf + size) = le16_to_cpu(*(buf + size));
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}
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static inline void htol16_buf(u16 *buf, unsigned int size)
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{
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size /= 2;
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while (size--)
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*(buf + size) = cpu_to_le16(*(buf + size));
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}
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/*
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* Read in and validate sprom.
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* Return 0 on success, nonzero on error.
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*/
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static int
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sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
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u16 *buf, uint nwords, bool check_crc)
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{
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int err = 0;
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uint i;
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/* read the sprom */
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for (i = 0; i < nwords; i++)
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buf[i] = R_REG(&sprom[wordoff + i]);
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if (check_crc) {
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if (buf[0] == 0xffff)
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/*
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* The hardware thinks that an srom that starts with
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* 0xffff is blank, regardless of the rest of the
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* content, so declare it bad.
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*/
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return -ENODATA;
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/* fixup the endianness so crc8 will pass */
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htol16_buf(buf, nwords * 2);
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if (crc8(srom_crc8_table, (u8 *) buf, nwords * 2,
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CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(srom_crc8_table))
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/* DBG only pci always read srom4 first, then srom8/9 */
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err = -EIO;
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/* now correct the endianness of the byte array */
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ltoh16_buf(buf, nwords * 2);
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}
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return err;
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}
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static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
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{
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u8 *otp;
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uint sz = OTP_SZ_MAX / 2; /* size in words */
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int err = 0;
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otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
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if (otp == NULL)
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return -ENOMEM;
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err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
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memcpy(buf, otp, bufsz);
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kfree(otp);
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/* Check CRC */
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if (buf[0] == 0xffff)
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/* The hardware thinks that an srom that starts with 0xffff
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* is blank, regardless of the rest of the content, so declare
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* it bad.
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*/
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return -ENODATA;
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/* fixup the endianness so crc8 will pass */
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htol16_buf(buf, bufsz);
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if (crc8(srom_crc8_table, (u8 *) buf, SROM4_WORDS * 2,
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CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(srom_crc8_table))
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err = -EIO;
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/* now correct the endianness of the byte array */
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ltoh16_buf(buf, bufsz);
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return err;
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}
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/*
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* Create variable table from memory.
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* Return 0 on success, nonzero on error.
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*/
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static int initvars_table(char *start, char *end,
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char **vars, uint *count)
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{
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int c = (int)(end - start);
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/* do it only when there is more than just the null string */
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if (c > 1) {
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char *vp = kmalloc(c, GFP_ATOMIC);
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if (!vp)
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return -ENOMEM;
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memcpy(vp, start, c);
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*vars = vp;
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*count = c;
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} else {
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*vars = NULL;
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*count = 0;
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}
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return 0;
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}
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/* Parse SROM and create name=value pairs. 'srom' points to
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* the SROM word array. 'off' specifies the offset of the
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* first word 'srom' points to, which should be either 0 or
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* SROM3_SWRG_OFF (full SROM or software region).
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*/
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static uint mask_shift(u16 mask)
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{
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uint i;
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for (i = 0; i < (sizeof(mask) << 3); i++) {
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if (mask & (1 << i))
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return i;
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}
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return 0;
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}
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static uint mask_width(u16 mask)
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{
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int i;
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for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
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if (mask & (1 << i))
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return (uint) (i - mask_shift(mask) + 1);
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}
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return 0;
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}
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static void
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_initvars_srom_pci(u8 sromrev, u16 *srom, uint off, struct brcms_varbuf *b)
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{
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@ -1159,6 +1027,105 @@ _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, struct brcms_varbuf *b)
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}
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}
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/*
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* Read in and validate sprom.
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* Return 0 on success, nonzero on error.
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*/
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static int
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sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
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u16 *buf, uint nwords, bool check_crc)
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{
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int err = 0;
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uint i;
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/* read the sprom */
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for (i = 0; i < nwords; i++)
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buf[i] = R_REG(&sprom[wordoff + i]);
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if (check_crc) {
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if (buf[0] == 0xffff)
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/*
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* The hardware thinks that an srom that starts with
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* 0xffff is blank, regardless of the rest of the
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* content, so declare it bad.
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*/
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return -ENODATA;
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/* fixup the endianness so crc8 will pass */
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htol16_buf(buf, nwords * 2);
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if (crc8(srom_crc8_table, (u8 *) buf, nwords * 2,
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CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(srom_crc8_table))
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/* DBG only pci always read srom4 first, then srom8/9 */
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err = -EIO;
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/* now correct the endianness of the byte array */
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ltoh16_buf(buf, nwords * 2);
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}
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return err;
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}
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static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
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{
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u8 *otp;
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uint sz = OTP_SZ_MAX / 2; /* size in words */
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int err = 0;
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otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
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if (otp == NULL)
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return -ENOMEM;
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err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
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memcpy(buf, otp, bufsz);
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kfree(otp);
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/* Check CRC */
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if (buf[0] == 0xffff)
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/* The hardware thinks that an srom that starts with 0xffff
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* is blank, regardless of the rest of the content, so declare
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* it bad.
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*/
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return -ENODATA;
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/* fixup the endianness so crc8 will pass */
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htol16_buf(buf, bufsz);
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if (crc8(srom_crc8_table, (u8 *) buf, SROM4_WORDS * 2,
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CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(srom_crc8_table))
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err = -EIO;
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/* now correct the endianness of the byte array */
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ltoh16_buf(buf, bufsz);
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return err;
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}
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/*
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* Create variable table from memory.
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* Return 0 on success, nonzero on error.
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*/
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static int initvars_table(char *start, char *end,
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char **vars, uint *count)
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{
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int c = (int)(end - start);
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/* do it only when there is more than just the null string */
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if (c > 1) {
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char *vp = kmalloc(c, GFP_ATOMIC);
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if (!vp)
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return -ENOMEM;
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memcpy(vp, start, c);
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*vars = vp;
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*count = c;
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} else {
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*vars = NULL;
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*count = 0;
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}
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return 0;
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}
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/*
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* Initialize nonvolatile variable table from sprom.
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* Return 0 on success, nonzero on error.
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@ -1249,3 +1216,25 @@ errout:
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kfree(srom);
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return err;
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}
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/*
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* Initialize local vars from the right source for this platform.
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* Return 0 on success, nonzero on error.
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*/
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int srom_var_init(struct si_pub *sih, void *curmap, char **vars, uint *count)
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{
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uint len;
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len = 0;
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if (vars == NULL || count == NULL)
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return 0;
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*vars = NULL;
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*count = 0;
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if (curmap != NULL)
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return initvars_srom_pci(sih, curmap, vars, count);
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return -EINVAL;
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}
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@ -30,15 +30,6 @@
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#define BRCMS_STF_SS_STBC_RX(wlc) (BRCMS_ISNPHY(wlc->band) && \
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NREV_GT(wlc->band->phyrev, 3) && NREV_LE(wlc->band->phyrev, 6))
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static bool brcms_c_stf_stbc_tx_set(struct brcms_c_info *wlc, s32 int_val);
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static int brcms_c_stf_txcore_set(struct brcms_c_info *wlc, u8 Nsts, u8 val);
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static int brcms_c_stf_spatial_policy_set(struct brcms_c_info *wlc, int val);
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static void brcms_c_stf_stbc_rx_ht_update(struct brcms_c_info *wlc, int val);
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static void _brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc);
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static u16 _brcms_c_stf_phytxchain_sel(struct brcms_c_info *wlc,
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u32 rspec);
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#define NSTS_1 1
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#define NSTS_2 2
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#define NSTS_3 3
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@ -222,6 +213,60 @@ static int brcms_c_stf_spatial_policy_set(struct brcms_c_info *wlc, int val)
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return 0;
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}
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/*
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* Centralized txant update function. call it whenever wlc->stf->txant and/or
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* wlc->stf->txchain change.
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*
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* Antennas are controlled by ucode indirectly, which drives PHY or GPIO to
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* achieve various tx/rx antenna selection schemes
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*
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* legacy phy, bit 6 and bit 7 means antenna 0 and 1 respectively, bit6+bit7
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* means auto(last rx).
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* for NREV<3, bit 6 and bit 7 means antenna 0 and 1 respectively, bit6+bit7
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* means last rx and do tx-antenna selection for SISO transmissions
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* for NREV=3, bit 6 and bit _8_ means antenna 0 and 1 respectively, bit6+bit7
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* means last rx and do tx-antenna selection for SISO transmissions
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* for NREV>=7, bit 6 and bit 7 mean antenna 0 and 1 respectively, nit6+bit7
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* means both cores active
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*/
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static void _brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc)
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{
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s8 txant;
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txant = (s8) wlc->stf->txant;
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if (BRCMS_PHY_11N_CAP(wlc->band)) {
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if (txant == ANT_TX_FORCE_0) {
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wlc->stf->phytxant = PHY_TXC_ANT_0;
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} else if (txant == ANT_TX_FORCE_1) {
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wlc->stf->phytxant = PHY_TXC_ANT_1;
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if (BRCMS_ISNPHY(wlc->band) &&
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NREV_GE(wlc->band->phyrev, 3)
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&& NREV_LT(wlc->band->phyrev, 7))
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wlc->stf->phytxant = PHY_TXC_ANT_2;
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} else {
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if (BRCMS_ISLCNPHY(wlc->band) ||
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BRCMS_ISSSLPNPHY(wlc->band))
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wlc->stf->phytxant = PHY_TXC_LCNPHY_ANT_LAST;
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else {
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/* catch out of sync wlc->stf->txcore */
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WARN_ON(wlc->stf->txchain <= 0);
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wlc->stf->phytxant =
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wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
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}
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}
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} else {
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if (txant == ANT_TX_FORCE_0)
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wlc->stf->phytxant = PHY_TXC_OLD_ANT_0;
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else if (txant == ANT_TX_FORCE_1)
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wlc->stf->phytxant = PHY_TXC_OLD_ANT_1;
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else
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wlc->stf->phytxant = PHY_TXC_OLD_ANT_LAST;
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}
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brcms_b_txant_set(wlc->hw, wlc->stf->phytxant);
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}
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int brcms_c_stf_txchain_set(struct brcms_c_info *wlc, s32 int_val, bool force)
|
||||
{
|
||||
u8 txchain = (u8) int_val;
|
||||
|
|
@ -358,60 +403,6 @@ void brcms_c_stf_detach(struct brcms_c_info *wlc)
|
|||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Centralized txant update function. call it whenever wlc->stf->txant and/or
|
||||
* wlc->stf->txchain change.
|
||||
*
|
||||
* Antennas are controlled by ucode indirectly, which drives PHY or GPIO to
|
||||
* achieve various tx/rx antenna selection schemes
|
||||
*
|
||||
* legacy phy, bit 6 and bit 7 means antenna 0 and 1 respectively, bit6+bit7
|
||||
* means auto(last rx).
|
||||
* for NREV<3, bit 6 and bit 7 means antenna 0 and 1 respectively, bit6+bit7
|
||||
* means last rx and do tx-antenna selection for SISO transmissions
|
||||
* for NREV=3, bit 6 and bit _8_ means antenna 0 and 1 respectively, bit6+bit7
|
||||
* means last rx and do tx-antenna selection for SISO transmissions
|
||||
* for NREV>=7, bit 6 and bit 7 mean antenna 0 and 1 respectively, nit6+bit7
|
||||
* means both cores active
|
||||
*/
|
||||
static void _brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc)
|
||||
{
|
||||
s8 txant;
|
||||
|
||||
txant = (s8) wlc->stf->txant;
|
||||
if (BRCMS_PHY_11N_CAP(wlc->band)) {
|
||||
if (txant == ANT_TX_FORCE_0) {
|
||||
wlc->stf->phytxant = PHY_TXC_ANT_0;
|
||||
} else if (txant == ANT_TX_FORCE_1) {
|
||||
wlc->stf->phytxant = PHY_TXC_ANT_1;
|
||||
|
||||
if (BRCMS_ISNPHY(wlc->band) &&
|
||||
NREV_GE(wlc->band->phyrev, 3)
|
||||
&& NREV_LT(wlc->band->phyrev, 7))
|
||||
wlc->stf->phytxant = PHY_TXC_ANT_2;
|
||||
} else {
|
||||
if (BRCMS_ISLCNPHY(wlc->band) ||
|
||||
BRCMS_ISSSLPNPHY(wlc->band))
|
||||
wlc->stf->phytxant = PHY_TXC_LCNPHY_ANT_LAST;
|
||||
else {
|
||||
/* catch out of sync wlc->stf->txcore */
|
||||
WARN_ON(wlc->stf->txchain <= 0);
|
||||
wlc->stf->phytxant =
|
||||
wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (txant == ANT_TX_FORCE_0)
|
||||
wlc->stf->phytxant = PHY_TXC_OLD_ANT_0;
|
||||
else if (txant == ANT_TX_FORCE_1)
|
||||
wlc->stf->phytxant = PHY_TXC_OLD_ANT_1;
|
||||
else
|
||||
wlc->stf->phytxant = PHY_TXC_OLD_ANT_LAST;
|
||||
}
|
||||
|
||||
brcms_b_txant_set(wlc->hw, wlc->stf->phytxant);
|
||||
}
|
||||
|
||||
void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc)
|
||||
{
|
||||
_brcms_c_stf_phy_txant_upd(wlc);
|
||||
|
|
|
|||
Loading…
Reference in New Issue