gpio: add driver for SAMA5D2 PIOBU pins
PIOBU pins do not lose their voltage during Backup/Self-refresh. This patch adds a simple GPIO controller for them and a maintainer for the driver. This driver adds support for using the pins as GPIO offering the possibility to read/set the voltage. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Andrei.Stefanescu@microchip.com
Linus Walleij
parent
6bd925a8b7
commit
fb0b35d307
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@ -9768,6 +9768,12 @@ M: Nicolas Ferre <nicolas.ferre@microchip.com>
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S: Supported
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F: drivers/power/reset/at91-sama5d2_shdwc.c
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MICROCHIP SAMA5D2-COMPATIBLE PIOBU GPIO
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M: Andrei Stefanescu <andrei.stefanescu@microchip.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: linux-gpio@vger.kernel.org
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F: drivers/gpio/gpio-sama5d2-piobu.c
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MICROCHIP SPI DRIVER
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M: Nicolas Ferre <nicolas.ferre@microchip.com>
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S: Supported
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@ -430,6 +430,17 @@ config GPIO_REG
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A 32-bit single register GPIO fixed in/out implementation. This
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can be used to represent any register as a set of GPIO signals.
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config GPIO_SAMA5D2_PIOBU
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tristate "SAMA5D2 PIOBU GPIO support"
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depends on MFD_SYSCON
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select GPIO_SYSCON
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help
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Say yes here to use the PIOBU pins as GPIOs.
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PIOBU pins on the SAMA5D2 can be used as GPIOs.
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The difference from regular GPIOs is that they
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maintain their value during backup/self-refresh.
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config GPIO_SIOX
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tristate "SIOX GPIO support"
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depends on SIOX
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@ -108,6 +108,7 @@ obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
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obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
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obj-$(CONFIG_GPIO_REG) += gpio-reg.o
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obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
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obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o
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obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
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obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
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obj-$(CONFIG_GPIO_SNPS_CREG) += gpio-creg-snps.o
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@ -0,0 +1,253 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* SAMA5D2 PIOBU GPIO controller
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*
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* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Andrei Stefanescu <andrei.stefanescu@microchip.com>
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*
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*/
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#include <linux/bits.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define PIOBU_NUM 8
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#define PIOBU_REG_SIZE 4
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/*
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* backup mode protection register for tamper detection
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* normal mode protection register for tamper detection
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* wakeup signal generation
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*/
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#define PIOBU_BMPR 0x7C
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#define PIOBU_NMPR 0x80
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#define PIOBU_WKPR 0x90
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#define PIOBU_BASE 0x18 /* PIOBU offset from SECUMOD base register address. */
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#define PIOBU_DET_OFFSET 16
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/* In the datasheet this bit is called OUTPUT */
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#define PIOBU_DIRECTION BIT(8)
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#define PIOBU_OUT BIT(8)
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#define PIOBU_IN 0
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#define PIOBU_SOD BIT(9)
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#define PIOBU_PDS BIT(10)
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#define PIOBU_HIGH BIT(9)
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#define PIOBU_LOW 0
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struct sama5d2_piobu {
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struct gpio_chip chip;
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struct regmap *regmap;
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};
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/**
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* sama5d2_piobu_setup_pin() - prepares a pin for set_direction call
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*
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* Do not consider pin for tamper detection (normal and backup modes)
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* Do not consider pin as tamper wakeup interrupt source
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*/
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static int sama5d2_piobu_setup_pin(struct gpio_chip *chip, unsigned int pin)
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{
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int ret;
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struct sama5d2_piobu *piobu = container_of(chip, struct sama5d2_piobu,
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chip);
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unsigned int mask = BIT(PIOBU_DET_OFFSET + pin);
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ret = regmap_update_bits(piobu->regmap, PIOBU_BMPR, mask, 0);
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if (ret)
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return ret;
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ret = regmap_update_bits(piobu->regmap, PIOBU_NMPR, mask, 0);
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if (ret)
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return ret;
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return regmap_update_bits(piobu->regmap, PIOBU_WKPR, mask, 0);
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}
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/**
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* sama5d2_piobu_write_value() - writes value & mask at the pin's PIOBU register
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*/
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static int sama5d2_piobu_write_value(struct gpio_chip *chip, unsigned int pin,
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unsigned int mask, unsigned int value)
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{
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int reg;
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struct sama5d2_piobu *piobu = container_of(chip, struct sama5d2_piobu,
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chip);
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reg = PIOBU_BASE + pin * PIOBU_REG_SIZE;
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return regmap_update_bits(piobu->regmap, reg, mask, value);
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}
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/**
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* sama5d2_piobu_read_value() - read the value with masking from the pin's PIOBU
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* register
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*/
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static int sama5d2_piobu_read_value(struct gpio_chip *chip, unsigned int pin,
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unsigned int mask)
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{
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struct sama5d2_piobu *piobu = container_of(chip, struct sama5d2_piobu,
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chip);
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unsigned int val, reg;
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int ret;
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reg = PIOBU_BASE + pin * PIOBU_REG_SIZE;
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ret = regmap_read(piobu->regmap, reg, &val);
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if (ret < 0)
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return ret;
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return val & mask;
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}
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/**
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* sama5d2_piobu_set_direction() - mark pin as input or output
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*/
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static int sama5d2_piobu_set_direction(struct gpio_chip *chip,
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unsigned int direction,
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unsigned int pin)
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{
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return sama5d2_piobu_write_value(chip, pin, PIOBU_DIRECTION, direction);
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}
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/**
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* sama5d2_piobu_get_direction() - gpiochip get_direction
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*/
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static int sama5d2_piobu_get_direction(struct gpio_chip *chip,
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unsigned int pin)
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{
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int ret = sama5d2_piobu_read_value(chip, pin, PIOBU_DIRECTION);
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if (ret < 0)
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return ret;
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return (ret == PIOBU_IN) ? 1 : 0;
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}
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/**
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* sama5d2_piobu_direction_input() - gpiochip direction_input
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*/
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static int sama5d2_piobu_direction_input(struct gpio_chip *chip,
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unsigned int pin)
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{
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return sama5d2_piobu_set_direction(chip, PIOBU_IN, pin);
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}
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/**
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* sama5d2_piobu_direction_output() - gpiochip direction_output
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*/
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static int sama5d2_piobu_direction_output(struct gpio_chip *chip,
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unsigned int pin, int value)
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{
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return sama5d2_piobu_set_direction(chip, PIOBU_OUT, pin);
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}
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/**
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* sama5d2_piobu_get() - gpiochip get
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*/
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static int sama5d2_piobu_get(struct gpio_chip *chip, unsigned int pin)
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{
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/* if pin is input, read value from PDS else read from SOD */
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int ret = sama5d2_piobu_get_direction(chip, pin);
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if (ret == 1)
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ret = sama5d2_piobu_read_value(chip, pin, PIOBU_PDS);
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else if (!ret)
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ret = sama5d2_piobu_read_value(chip, pin, PIOBU_SOD);
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if (ret < 0)
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return ret;
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return !!ret;
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}
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/**
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* sama5d2_piobu_set() - gpiochip set
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*/
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static void sama5d2_piobu_set(struct gpio_chip *chip, unsigned int pin,
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int value)
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{
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if (!value)
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value = PIOBU_LOW;
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else
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value = PIOBU_HIGH;
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sama5d2_piobu_write_value(chip, pin, PIOBU_SOD, value);
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}
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static int sama5d2_piobu_probe(struct platform_device *pdev)
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{
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struct sama5d2_piobu *piobu;
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int ret, i;
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piobu = devm_kzalloc(&pdev->dev, sizeof(*piobu), GFP_KERNEL);
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if (!piobu)
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return -ENOMEM;
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platform_set_drvdata(pdev, piobu);
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piobu->chip.label = pdev->name;
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piobu->chip.parent = &pdev->dev;
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piobu->chip.of_node = pdev->dev.of_node;
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piobu->chip.owner = THIS_MODULE,
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piobu->chip.get_direction = sama5d2_piobu_get_direction,
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piobu->chip.direction_input = sama5d2_piobu_direction_input,
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piobu->chip.direction_output = sama5d2_piobu_direction_output,
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piobu->chip.get = sama5d2_piobu_get,
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piobu->chip.set = sama5d2_piobu_set,
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piobu->chip.base = -1,
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piobu->chip.ngpio = PIOBU_NUM,
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piobu->chip.can_sleep = 0,
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piobu->regmap = syscon_node_to_regmap(pdev->dev.of_node);
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if (IS_ERR(piobu->regmap)) {
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dev_err(&pdev->dev, "Failed to get syscon regmap %ld\n",
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PTR_ERR(piobu->regmap));
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return PTR_ERR(piobu->regmap);
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}
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ret = devm_gpiochip_add_data(&pdev->dev, &piobu->chip, piobu);
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if (ret) {
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dev_err(&pdev->dev, "Failed to add gpiochip %d\n", ret);
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return ret;
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}
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for (i = 0; i < PIOBU_NUM; ++i) {
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ret = sama5d2_piobu_setup_pin(&piobu->chip, i);
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if (ret) {
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dev_err(&pdev->dev, "Failed to setup pin: %d %d\n",
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i, ret);
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return ret;
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}
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}
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return 0;
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}
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static const struct of_device_id sama5d2_piobu_ids[] = {
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{ .compatible = "atmel,sama5d2-secumod" },
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{},
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};
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MODULE_DEVICE_TABLE(of, sama5d2_piobu_ids);
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static struct platform_driver sama5d2_piobu_driver = {
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.driver = {
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.name = "sama5d2-piobu",
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.of_match_table = of_match_ptr(sama5d2_piobu_ids)
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},
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.probe = sama5d2_piobu_probe,
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};
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module_platform_driver(sama5d2_piobu_driver);
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MODULE_VERSION("1.0");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("SAMA5D2 PIOBU controller driver");
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MODULE_AUTHOR("Andrei Stefanescu <andrei.stefanescu@microchip.com>");
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