KVM: arm/arm64: vgic-new: Add GICv2 MMIO handling framework
Create vgic-mmio-v2.c to describe GICv2 emulation specific handlers using the initializer macros provided by the VGIC MMIO framework. Provide a function to register the GICv2 distributor registers to the kvm_io_bus framework. The actual handler functions are still stubs in this patch. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
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/*
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* VGICv2 MMIO handling functions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/irqchip/arm-gic.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <kvm/iodev.h>
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#include <kvm/arm_vgic.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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static const struct vgic_register_region vgic_v2_dist_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 12,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
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vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 2,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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};
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
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{
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dev->regions = vgic_v2_dist_registers;
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dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
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kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
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return SZ_4K;
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}
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@ -182,3 +182,29 @@ struct kvm_io_device_ops kvm_io_gic_ops = {
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.read = dispatch_mmio_read,
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.read = dispatch_mmio_read,
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.write = dispatch_mmio_write,
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.write = dispatch_mmio_write,
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};
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};
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int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
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enum vgic_type type)
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{
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struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
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int ret = 0;
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unsigned int len;
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switch (type) {
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case VGIC_V2:
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len = vgic_v2_init_dist_iodev(io_device);
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break;
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default:
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BUG_ON(1);
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}
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io_device->base_addr = dist_base_address;
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io_device->redist_vcpu = NULL;
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mutex_lock(&kvm->slots_lock);
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ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
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len, &io_device->dev);
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mutex_unlock(&kvm->slots_lock);
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return ret;
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}
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@ -96,4 +96,6 @@ unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
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void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
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void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len, unsigned long val);
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unsigned int len, unsigned long val);
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
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#endif
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#endif
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@ -27,6 +27,8 @@ void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
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void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
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void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
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void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
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void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
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void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
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void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
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int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
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enum vgic_type);
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#ifdef CONFIG_KVM_ARM_VGIC_V3
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#ifdef CONFIG_KVM_ARM_VGIC_V3
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void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu);
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void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu);
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