CRIS v32: Update and improve kernel/time.c
- Shorten include paths to machine dependent header files. - Register name for first timer is now regi_timer0. - Remove raw_printk hack, use oops_in_progress instead. - Add handling of CPU frequency scaling for CRIS. - Remove regs parameter to timer_interrupt, get them from get_irq_regs instead. - Whitespace and formatting changes.
This commit is contained in:
Jesper Nilsson
parent
bd1c8c54b9
commit
fbdb5f865b
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@ -1,8 +1,7 @@
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/* $Id: time.c,v 1.19 2005/04/29 05:40:09 starvik Exp $
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*
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/*
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* linux/arch/cris/arch-v32/kernel/time.c
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*
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* Copyright (C) 2003 Axis Communications AB
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* Copyright (C) 2003-2007 Axis Communications AB
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*
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*/
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@ -14,28 +13,34 @@
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <linux/cpufreq.h>
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#include <asm/types.h>
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#include <asm/signal.h>
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#include <asm/io.h>
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#include <asm/delay.h>
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#include <asm/rtc.h>
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#include <asm/irq.h>
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#include <asm/irq_regs.h>
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#include <asm/arch/hwregs/reg_map.h>
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#include <asm/arch/hwregs/reg_rdwr.h>
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#include <asm/arch/hwregs/timer_defs.h>
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#include <asm/arch/hwregs/intr_vect_defs.h>
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <hwregs/timer_defs.h>
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#include <hwregs/intr_vect_defs.h>
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#ifdef CONFIG_CRIS_MACH_ARTPEC3
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#include <hwregs/clkgen_defs.h>
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#endif
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/* Watchdog defines */
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#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
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#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */
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#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1) /* Number of 763 counts before watchdog bites */
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#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
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#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */
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/* Number of 763 counts before watchdog bites */
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#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1)
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unsigned long timer_regs[NR_CPUS] =
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{
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regi_timer,
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regi_timer0,
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#ifdef CONFIG_SMP
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regi_timer2
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regi_timer2
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#endif
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};
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@ -44,12 +49,22 @@ extern int set_rtc_mmss(unsigned long nowtime);
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extern int setup_irq(int, struct irqaction *);
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extern int have_rtc;
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#ifdef CONFIG_CPU_FREQ
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static int
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cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
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void *data);
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static struct notifier_block cris_time_freq_notifier_block = {
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.notifier_call = cris_time_freq_notifier,
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};
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#endif
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unsigned long get_ns_in_jiffie(void)
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{
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reg_timer_r_tmr0_data data;
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unsigned long ns;
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data = REG_RD(timer, regi_timer, r_tmr0_data);
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data = REG_RD(timer, regi_timer0, r_tmr0_data);
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ns = (TIMER0_DIV - data) * 10;
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return ns;
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}
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@ -59,31 +74,27 @@ unsigned long do_slow_gettimeoffset(void)
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unsigned long count;
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unsigned long usec_count = 0;
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static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
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/* For the first call after boot */
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static unsigned long count_p = TIMER0_DIV;
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static unsigned long jiffies_p = 0;
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/*
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* cache volatile jiffies temporarily; we have IRQs turned off.
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*/
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/* Cache volatile jiffies temporarily; we have IRQs turned off. */
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unsigned long jiffies_t;
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/* The timer interrupt comes from Etrax timer 0. In order to get
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* better precision, we check the current value. It might have
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* underflowed already though.
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*/
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* underflowed already though. */
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count = REG_RD(timer, regi_timer0, r_tmr0_data);
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jiffies_t = jiffies;
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count = REG_RD(timer, regi_timer, r_tmr0_data);
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jiffies_t = jiffies;
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/*
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* avoiding timer inconsistencies (they are rare, but they happen)...
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* there are one problem that must be avoided here:
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* 1. the timer counter underflows
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/* Avoiding timer inconsistencies (they are rare, but they happen)
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* There is one problem that must be avoided here:
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* 1. the timer counter underflows
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*/
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if( jiffies_t == jiffies_p ) {
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if( count > count_p ) {
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/* Timer wrapped, use new count and prescale
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* increase the time corresponding to one jiffie
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/* Timer wrapped, use new count and prescale.
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* Increase the time corresponding to one jiffy.
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*/
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usec_count = 1000000/HZ;
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}
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@ -106,17 +117,15 @@ unsigned long do_slow_gettimeoffset(void)
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*/
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/* This gives us 1.3 ms to do something useful when the NMI comes */
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/* right now, starting the watchdog is the same as resetting it */
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/* Right now, starting the watchdog is the same as resetting it */
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#define start_watchdog reset_watchdog
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#if defined(CONFIG_ETRAX_WATCHDOG)
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static short int watchdog_key = 42; /* arbitrary 7 bit number */
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#endif
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/* number of pages to consider "out of memory". it is normal that the memory
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* is used though, so put this really low.
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*/
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/* Number of pages to consider "out of memory". It is normal that the memory
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* is used though, so set this really low. */
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#define WATCHDOG_MIN_FREE_PAGES 8
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void
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@ -125,14 +134,15 @@ reset_watchdog(void)
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#if defined(CONFIG_ETRAX_WATCHDOG)
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reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
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/* only keep watchdog happy as long as we have memory left! */
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/* Only keep watchdog happy as long as we have memory left! */
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if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
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/* reset the watchdog with the inverse of the old key */
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watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
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/* Reset the watchdog with the inverse of the old key */
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/* Invert key, which is 7 bits */
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watchdog_key ^= ETRAX_WD_KEY_MASK;
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wd_ctrl.cnt = ETRAX_WD_CNT;
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wd_ctrl.cmd = regk_timer_start;
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wd_ctrl.key = watchdog_key;
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REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
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REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
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}
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#endif
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}
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@ -148,7 +158,7 @@ stop_watchdog(void)
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wd_ctrl.cnt = ETRAX_WD_CNT;
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wd_ctrl.cmd = regk_timer_stop;
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wd_ctrl.key = watchdog_key;
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REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
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REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
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#endif
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}
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@ -160,17 +170,28 @@ handle_watchdog_bite(struct pt_regs* regs)
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#if defined(CONFIG_ETRAX_WATCHDOG)
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extern int cause_of_death;
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raw_printk("Watchdog bite\n");
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oops_in_progress = 1;
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printk(KERN_WARNING "Watchdog bite\n");
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/* Check if forced restart or unexpected watchdog */
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if (cause_of_death == 0xbedead) {
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#ifdef CONFIG_CRIS_MACH_ARTPEC3
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/* There is a bug in Artpec-3 (voodoo TR 78) that requires
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* us to go to lower frequency for the reset to be reliable
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*/
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reg_clkgen_rw_clk_ctrl ctrl =
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REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
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ctrl.pll = 0;
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REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
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#endif
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while(1);
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}
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/* Unexpected watchdog, stop the watchdog and dump registers*/
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/* Unexpected watchdog, stop the watchdog and dump registers. */
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stop_watchdog();
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raw_printk("Oops: bitten by watchdog\n");
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show_registers(regs);
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printk(KERN_WARNING "Oops: bitten by watchdog\n");
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show_registers(regs);
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oops_in_progress = 0;
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#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
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reset_watchdog();
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#endif
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@ -178,21 +199,19 @@ handle_watchdog_bite(struct pt_regs* regs)
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#endif
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}
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/* last time the cmos clock got updated */
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/* Last time the cmos clock got updated. */
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static long last_rtc_update = 0;
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/*
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* timer_interrupt() needs to keep up the real-time clock,
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* as well as call the "do_timer()" routine every clocktick
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* as well as call the "do_timer()" routine every clocktick.
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*/
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//static unsigned short myjiff; /* used by our debug routine print_timestamp */
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extern void cris_do_profile(struct pt_regs *regs);
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static inline irqreturn_t
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timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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timer_interrupt(int irq, void *dev_id)
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{
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struct pt_regs *regs = get_irq_regs();
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int cpu = smp_processor_id();
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reg_timer_r_masked_intr masked_intr;
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reg_timer_rw_ack_intr ack_intr = { 0 };
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@ -202,11 +221,11 @@ timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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if (!masked_intr.tmr0)
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return IRQ_NONE;
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/* acknowledge the timer irq */
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/* Acknowledge the timer irq. */
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ack_intr.tmr0 = 1;
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REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
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/* reset watchdog otherwise it resets us! */
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/* Reset watchdog otherwise it resets us! */
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reset_watchdog();
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/* Update statistics. */
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@ -218,7 +237,7 @@ timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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if (cpu != 0)
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return IRQ_HANDLED;
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/* call the real timer interrupt handler */
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/* Call the real timer interrupt handler */
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do_timer(1);
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/*
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@ -236,17 +255,17 @@ timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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if (set_rtc_mmss(xtime.tv_sec) == 0)
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last_rtc_update = xtime.tv_sec;
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else
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last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
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/* Do it again in 60 s */
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last_rtc_update = xtime.tv_sec - 600;
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}
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return IRQ_HANDLED;
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}
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/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
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* it needs to be IRQF_DISABLED to make the jiffies update work properly
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/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain.
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* It needs to be IRQF_DISABLED to make the jiffies update work properly.
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*/
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static struct irqaction irq_timer = {
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.mask = timer_interrupt,
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static struct irqaction irq_timer = {
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.handler = timer_interrupt,
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.flags = IRQF_SHARED | IRQF_DISABLED,
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.mask = CPU_MASK_NONE,
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.name = "timer"
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@ -256,27 +275,27 @@ void __init
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cris_timer_init(void)
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{
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int cpu = smp_processor_id();
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reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
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reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
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reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
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reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
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reg_timer_rw_intr_mask timer_intr_mask;
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/* Setup the etrax timers
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/* Setup the etrax timers.
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* Base frequency is 100MHz, divider 1000000 -> 100 HZ
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* We use timer0, so timer1 is free.
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* The trig timer is used by the fasttimer API if enabled.
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*/
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tmr0_ctrl.op = regk_timer_ld;
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tmr0_ctrl.op = regk_timer_ld;
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tmr0_ctrl.freq = regk_timer_f100;
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REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
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REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
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tmr0_ctrl.op = regk_timer_run;
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REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
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REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
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REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
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tmr0_ctrl.op = regk_timer_run;
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REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
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/* enable the timer irq */
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timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
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timer_intr_mask.tmr0 = 1;
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REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
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/* Enable the timer irq. */
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timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
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timer_intr_mask.tmr0 = 1;
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REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
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}
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void __init
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@ -284,7 +303,7 @@ time_init(void)
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{
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reg_intr_vect_rw_mask intr_mask;
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/* probe for the RTC and read it if it exists
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/* Probe for the RTC and read it if it exists.
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* Before the RTC can be probed the loops_per_usec variable needs
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* to be initialized to make usleep work. A better value for
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* loops_per_usec is calculated by the kernel later once the
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@ -293,52 +312,74 @@ time_init(void)
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loops_per_usec = 50;
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if(RTC_INIT() < 0) {
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/* no RTC, start at 1980 */
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/* No RTC, start at 1980 */
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xtime.tv_sec = 0;
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xtime.tv_nsec = 0;
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have_rtc = 0;
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} else {
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/* get the current time */
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/* Get the current time */
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have_rtc = 1;
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update_xtime_from_cmos();
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}
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/*
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* Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
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* tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
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* Initialize wall_to_monotonic such that adding it to
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* xtime will yield zero, the tv_nsec field must be normalized
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* (i.e., 0 <= nsec < NSEC_PER_SEC).
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*/
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set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
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/* Start CPU local timer */
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/* Start CPU local timer. */
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cris_timer_init();
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/* enable the timer irq in global config */
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intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
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intr_mask.timer = 1;
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REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
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/* Enable the timer irq in global config. */
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intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
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intr_mask.timer0 = 1;
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REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
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/* now actually register the timer irq handler that calls timer_interrupt() */
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/* Now actually register the timer irq handler that calls
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* timer_interrupt(). */
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setup_irq(TIMER0_INTR_VECT, &irq_timer);
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setup_irq(TIMER_INTR_VECT, &irq_timer);
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/* enable watchdog if we should use one */
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/* Enable watchdog if we should use one. */
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#if defined(CONFIG_ETRAX_WATCHDOG)
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printk("Enabling watchdog...\n");
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printk(KERN_INFO "Enabling watchdog...\n");
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start_watchdog();
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/* If we use the hardware watchdog, we want to trap it as an NMI
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and dump registers before it resets us. For this to happen, we
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must set the "m" NMI enable flag (which once set, is unset only
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when an NMI is taken).
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* and dump registers before it resets us. For this to happen, we
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* must set the "m" NMI enable flag (which once set, is unset only
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* when an NMI is taken). */
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{
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unsigned long flags;
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local_save_flags(flags);
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flags |= (1<<30); /* NMI M flag is at bit 30 */
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local_irq_restore(flags);
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}
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#endif
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The same goes for the external NMI, but that doesn't have any
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driver or infrastructure support yet. */
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{
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unsigned long flags;
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local_save_flags(flags);
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flags |= (1<<30); /* NMI M flag is at bit 30 */
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local_irq_restore(flags);
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}
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#ifdef CONFIG_CPU_FREQ
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cpufreq_register_notifier(&cris_time_freq_notifier_block,
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CPUFREQ_TRANSITION_NOTIFIER);
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#endif
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}
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#ifdef CONFIG_CPU_FREQ
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static int
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cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
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void *data)
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{
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struct cpufreq_freqs *freqs = data;
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if (val == CPUFREQ_POSTCHANGE) {
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reg_timer_r_tmr0_data data;
|
||||
reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
|
||||
do {
|
||||
data = REG_RD(timer, timer_regs[freqs->cpu],
|
||||
r_tmr0_data);
|
||||
} while (data > 20);
|
||||
REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue