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staging: tidspbridge: MMU2 registers are limited to 32-bit data access 

According to OMAP3 TRM access to MMU registers shall be strictly 32-bit
aligned.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Vladimir Zapolskiy 2011-10-19 22:39:12 +03:00 committed by Greg Kroah-Hartman
parent 6b7200fe0a
commit fcde2bf0b9
1 changed files with 1 additions and 1 deletions
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2
drivers/staging/tidspbridge/hw/hw_mmu.c
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@ -558,5 +558,5 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address,
void hw_mmu_tlb_flush_all(const void __iomem *base)
{
__raw_writeb(1, base + MMU_GFLUSH);
__raw_writel(1, base + MMU_GFLUSH);
}