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powerpc/powernv: Reset root port in firmware

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Resetting root port has more stuff to do than that for PCIe switch
ports and we should have resetting root port done in firmware instead
of the kernel itself. The problem was introduced by commit 5b2e198e
("powerpc/powernv: Rework EEH reset").

Cc: linux-stable <stable@vger.kernel.org>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Gavin Shan 2014-04-24 18:00:22 +10:00 committed by Benjamin Herrenschmidt
parent 54f112a383
commit fd5cee7ce8
1 changed files with 6 additions and 7 deletions
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13
arch/powerpc/platforms/powernv/eeh-ioda.c
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@ -510,12 +510,10 @@ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
int ret;
/*
* The rules applied to reset, either fundamental or hot reset:
*
* We always reset the direct upstream bridge of the PE. If the
* direct upstream bridge isn't root bridge, we always take hot
* reset no matter what option (fundamental or hot) is. Otherwise,
* we should do the reset according to the required option.
* For PHB reset, we always have complete reset. For those PEs whose
* primary bus derived from root complex (root bus) or root port
* (usually bus#1), we apply hot or fundamental reset on the root port.
* For other PEs, we always have hot reset on the PE primary bus.
*
* Here, we have different design to pHyp, which always clear the
* frozen state during PE reset. However, the good idea here from
@ -529,7 +527,8 @@ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
ret = ioda_eeh_phb_reset(hose, option);
} else {
bus = eeh_pe_bus_get(pe);
if (pci_is_root_bus(bus))
if (pci_is_root_bus(bus) ||
pci_is_root_bus(bus->parent))
ret = ioda_eeh_root_reset(hose, option);
else
ret = ioda_eeh_bridge_reset(bus->self, option);