[ARM] 3246/1: S3C24XX - retab clock list in arch/arm/mach-s3c2410/clock.c
Patch from Ben Dooks Properly tabulate the clock table in arch/arm/mach-s3c2410/clock.c and put the requisite commas on the end of the structs. Fix the comment about clock enable and disable in the setup code Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks
Russell King
parent
9d4ae7276a
commit
fe38ea5623
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@ -253,100 +253,101 @@ struct clk s3c24xx_uclk = {
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/* clock definitions */
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static struct clk init_clocks[] = {
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{ .name = "nand",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_NAND
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},
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{ .name = "lcd",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_LCDC
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},
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{ .name = "usb-host",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_USBH
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},
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{ .name = "usb-device",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_USBD
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},
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{ .name = "timers",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_PWMT
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},
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{ .name = "sdi",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_SDI
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},
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{ .name = "uart",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART0
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},
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{ .name = "uart",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART1
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},
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{ .name = "uart",
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.id = 2,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART2
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},
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{ .name = "gpio",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_GPIO
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},
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{ .name = "rtc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_RTC
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},
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{ .name = "adc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_ADC
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},
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{ .name = "i2c",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_IIC
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},
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{ .name = "iis",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_IIS
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},
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{ .name = "spi",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_SPI
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},
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{ .name = "watchdog",
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.id = -1,
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.parent = &clk_p,
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.ctrlbit = 0
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{
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.name = "nand",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_NAND,
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}, {
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.name = "lcd",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_LCDC,
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}, {
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.name = "usb-host",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_USBH,
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}, {
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.name = "usb-device",
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.id = -1,
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.parent = &clk_h,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_USBD,
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}, {
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.name = "timers",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_PWMT,
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}, {
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.name = "sdi",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_SDI,
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}, {
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.name = "uart",
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.id = 0,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART0,
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}, {
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.name = "uart",
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.id = 1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART1,
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}, {
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.name = "uart",
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.id = 2,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_UART2,
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}, {
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.name = "gpio",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_GPIO,
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}, {
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.name = "rtc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_RTC,
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}, {
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.name = "adc",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_ADC,
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}, {
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.name = "i2c",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_IIC,
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}, {
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.name = "iis",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_IIS,
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}, {
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.name = "spi",
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.id = -1,
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.parent = &clk_p,
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.enable = s3c24xx_clkcon_enable,
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.ctrlbit = S3C2410_CLKCON_SPI,
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}, {
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.name = "watchdog",
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.id = -1,
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.parent = &clk_p,
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.ctrlbit = 0,
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}
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};
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@ -390,16 +391,15 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
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clk_p.rate = pclk;
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clk_f.rate = fclk;
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/* it looks like just setting the register here is not good
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* enough, and causes the odd hang at initial boot time, so
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* do all of them indivdually.
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/* We must be careful disabling the clocks we are not intending to
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* be using at boot time, as subsytems such as the LCD which do
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* their own DMA requests to the bus can cause the system to lockup
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* if they where in the middle of requesting bus access.
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*
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* I think disabling the LCD clock if the LCD is active is
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* very dangerous, and therefore the bootloader should be
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* careful to not enable the LCD clock if it is not needed.
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*
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* and of course, this looks neater
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*/
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* Disabling the LCD clock if the LCD is active is very dangerous,
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* and therefore the bootloader should be careful to not enable
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* the LCD clock if it is not needed.
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*/
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s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
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s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
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