Merge branch 'clk-omap-legacy' into clk-next
Conflicts: arch/arm/mach-omap2/cclock3xxx_data.c
This commit is contained in:
Michael Turquette
commit
fe76756052
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@ -187,7 +187,7 @@ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
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obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
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obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o cclock3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
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obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
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File diff suppressed because it is too large
Load Diff
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@ -461,7 +461,17 @@ void __init omap3_init_early(void)
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omap3xxx_clockdomains_init();
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omap3xxx_hwmod_init();
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omap_hwmod_init_postsetup();
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omap_clk_soc_init = omap3xxx_clk_init;
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if (!of_have_populated_dt()) {
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omap3_prcm_legacy_iomaps_init();
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if (soc_is_am35xx())
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omap_clk_soc_init = am35xx_clk_legacy_init;
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else if (cpu_is_omap3630())
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omap_clk_soc_init = omap36xx_clk_legacy_init;
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else if (omap_rev() == OMAP3430_REV_ES1_0)
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omap_clk_soc_init = omap3430es1_clk_legacy_init;
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else
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omap_clk_soc_init = omap3430_clk_legacy_init;
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}
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}
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void __init omap3430_init_early(void)
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@ -509,8 +519,6 @@ void __init ti81xx_init_early(void)
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omap_hwmod_init_postsetup();
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if (of_have_populated_dt())
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omap_clk_soc_init = ti81xx_dt_clk_init;
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else
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omap_clk_soc_init = omap3xxx_clk_init;
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}
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void __init omap3_init_late(void)
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@ -731,15 +739,17 @@ int __init omap_clk_init(void)
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ti_clk_init_features();
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ret = of_prcm_init();
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if (ret)
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return ret;
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if (of_have_populated_dt()) {
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ret = of_prcm_init();
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if (ret)
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return ret;
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of_clk_init(NULL);
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of_clk_init(NULL);
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ti_dt_clk_init_retry_clks();
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ti_dt_clk_init_retry_clks();
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ti_dt_clockdomains_setup();
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ti_dt_clockdomains_setup();
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}
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ret = omap_clk_soc_init();
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@ -20,6 +20,7 @@ extern void __iomem *prm_base;
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extern u16 prm_features;
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extern void omap2_set_globals_prm(void __iomem *prm);
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int of_prcm_init(void);
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void omap3_prcm_legacy_iomaps_init(void);
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# endif
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/*
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@ -35,6 +35,8 @@
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#include "prm44xx.h"
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#include "common.h"
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#include "clock.h"
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#include "cm.h"
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#include "control.h"
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/*
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* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
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@ -627,6 +629,15 @@ int __init of_prcm_init(void)
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return 0;
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}
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void __init omap3_prcm_legacy_iomaps_init(void)
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{
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ti_clk_ll_ops = &omap_clk_ll_ops;
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clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
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clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
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clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
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}
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static int __init prm_late_init(void)
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{
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if (prm_ll_data->late_init)
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@ -5,7 +5,8 @@ clk-common = dpll.o composite.o divider.o gate.o \
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obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
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obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
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obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o clk-3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
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clk-3xxx.o clk-3xxx-legacy.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o
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obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o
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obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
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File diff suppressed because it is too large
Load Diff
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@ -22,6 +22,8 @@
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#include <linux/of_address.h>
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#include <linux/list.h>
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#include "clock.h"
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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@ -183,3 +185,126 @@ void ti_dt_clk_init_retry_clks(void)
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retries--;
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}
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}
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void __init ti_clk_patch_legacy_clks(struct ti_clk **patch)
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{
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while (*patch) {
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memcpy((*patch)->patch, *patch, sizeof(**patch));
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patch++;
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}
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}
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struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
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{
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struct clk *clk;
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struct ti_clk_fixed *fixed;
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struct ti_clk_fixed_factor *fixed_factor;
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struct clk_hw *clk_hw;
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if (setup->clk)
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return setup->clk;
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switch (setup->type) {
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case TI_CLK_FIXED:
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fixed = setup->data;
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clk = clk_register_fixed_rate(NULL, setup->name, NULL,
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CLK_IS_ROOT, fixed->frequency);
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break;
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case TI_CLK_MUX:
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clk = ti_clk_register_mux(setup);
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break;
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case TI_CLK_DIVIDER:
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clk = ti_clk_register_divider(setup);
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break;
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case TI_CLK_COMPOSITE:
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clk = ti_clk_register_composite(setup);
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break;
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case TI_CLK_FIXED_FACTOR:
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fixed_factor = setup->data;
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clk = clk_register_fixed_factor(NULL, setup->name,
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fixed_factor->parent,
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0, fixed_factor->mult,
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fixed_factor->div);
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break;
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case TI_CLK_GATE:
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clk = ti_clk_register_gate(setup);
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break;
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case TI_CLK_DPLL:
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clk = ti_clk_register_dpll(setup);
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break;
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default:
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pr_err("bad type for %s!\n", setup->name);
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clk = ERR_PTR(-EINVAL);
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}
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if (!IS_ERR(clk)) {
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setup->clk = clk;
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if (setup->clkdm_name) {
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if (__clk_get_flags(clk) & CLK_IS_BASIC) {
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pr_warn("can't setup clkdm for basic clk %s\n",
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setup->name);
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} else {
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clk_hw = __clk_get_hw(clk);
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to_clk_hw_omap(clk_hw)->clkdm_name =
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setup->clkdm_name;
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omap2_init_clk_clkdm(clk_hw);
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}
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}
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}
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return clk;
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}
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int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
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{
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struct clk *clk;
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bool retry;
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struct ti_clk_alias *retry_clk;
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struct ti_clk_alias *tmp;
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while (clks->clk) {
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clk = ti_clk_register_clk(clks->clk);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) == -EAGAIN) {
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list_add(&clks->link, &retry_list);
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} else {
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pr_err("register for %s failed: %ld\n",
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clks->clk->name, PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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} else {
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clks->lk.clk = clk;
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clkdev_add(&clks->lk);
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}
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clks++;
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}
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retry = true;
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while (!list_empty(&retry_list) && retry) {
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retry = false;
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list_for_each_entry_safe(retry_clk, tmp, &retry_list, link) {
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pr_debug("retry-init: %s\n", retry_clk->clk->name);
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clk = ti_clk_register_clk(retry_clk->clk);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) == -EAGAIN) {
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continue;
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} else {
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pr_err("register for %s failed: %ld\n",
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retry_clk->clk->name,
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PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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} else {
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retry = true;
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retry_clk->lk.clk = clk;
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clkdev_add(&retry_clk->lk);
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list_del(&retry_clk->link);
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}
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}
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}
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return 0;
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}
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@ -0,0 +1,172 @@
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/*
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* TI Clock driver internal definitions
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*
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* Copyright (C) 2014 Texas Instruments, Inc
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* Tero Kristo (t-kristo@ti.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DRIVERS_CLK_TI_CLOCK__
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#define __DRIVERS_CLK_TI_CLOCK__
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enum {
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TI_CLK_FIXED,
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TI_CLK_MUX,
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TI_CLK_DIVIDER,
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TI_CLK_COMPOSITE,
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TI_CLK_FIXED_FACTOR,
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TI_CLK_GATE,
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TI_CLK_DPLL,
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};
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/* Global flags */
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#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
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#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
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#define CLKF_SET_RATE_PARENT (1 << 2)
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#define CLKF_OMAP3 (1 << 3)
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#define CLKF_AM35XX (1 << 4)
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/* Gate flags */
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#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
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#define CLKF_INTERFACE (1 << 6)
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#define CLKF_SSI (1 << 7)
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#define CLKF_DSS (1 << 8)
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#define CLKF_HSOTGUSB (1 << 9)
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#define CLKF_WAIT (1 << 10)
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#define CLKF_NO_WAIT (1 << 11)
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#define CLKF_HSDIV (1 << 12)
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#define CLKF_CLKDM (1 << 13)
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/* DPLL flags */
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#define CLKF_LOW_POWER_STOP (1 << 5)
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#define CLKF_LOCK (1 << 6)
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#define CLKF_LOW_POWER_BYPASS (1 << 7)
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#define CLKF_PER (1 << 8)
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#define CLKF_CORE (1 << 9)
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#define CLKF_J_TYPE (1 << 10)
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#define CLK(dev, con, ck) \
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{ \
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.lk = { \
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.dev_id = dev, \
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.con_id = con, \
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}, \
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.clk = ck, \
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}
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struct ti_clk {
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const char *name;
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const char *clkdm_name;
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int type;
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void *data;
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struct ti_clk *patch;
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struct clk *clk;
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};
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struct ti_clk_alias {
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struct ti_clk *clk;
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struct clk_lookup lk;
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struct list_head link;
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};
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struct ti_clk_fixed {
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u32 frequency;
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u16 flags;
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};
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struct ti_clk_mux {
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u8 bit_shift;
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int num_parents;
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u16 reg;
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u8 module;
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const char **parents;
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u16 flags;
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};
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struct ti_clk_divider {
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const char *parent;
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u8 bit_shift;
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u16 max_div;
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u16 reg;
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u8 module;
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int *dividers;
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int num_dividers;
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u16 flags;
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};
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struct ti_clk_fixed_factor {
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const char *parent;
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u16 div;
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u16 mult;
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u16 flags;
|
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};
|
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|
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struct ti_clk_gate {
|
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const char *parent;
|
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u8 bit_shift;
|
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u16 reg;
|
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u8 module;
|
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u16 flags;
|
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};
|
||||
|
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struct ti_clk_composite {
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struct ti_clk_divider *divider;
|
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struct ti_clk_mux *mux;
|
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struct ti_clk_gate *gate;
|
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u16 flags;
|
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};
|
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|
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struct ti_clk_clkdm_gate {
|
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const char *parent;
|
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u16 flags;
|
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};
|
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|
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struct ti_clk_dpll {
|
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int num_parents;
|
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u16 control_reg;
|
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u16 idlest_reg;
|
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u16 autoidle_reg;
|
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u16 mult_div1_reg;
|
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u8 module;
|
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const char **parents;
|
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u16 flags;
|
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u8 modes;
|
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u32 mult_mask;
|
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u32 div1_mask;
|
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u32 enable_mask;
|
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u32 autoidle_mask;
|
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u32 freqsel_mask;
|
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u32 idlest_mask;
|
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u32 dco_mask;
|
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u32 sddiv_mask;
|
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u16 max_multiplier;
|
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u16 max_divider;
|
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u8 min_divider;
|
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u8 auto_recal_bit;
|
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u8 recal_en_bit;
|
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u8 recal_st_bit;
|
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};
|
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|
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struct clk *ti_clk_register_gate(struct ti_clk *setup);
|
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struct clk *ti_clk_register_interface(struct ti_clk *setup);
|
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struct clk *ti_clk_register_mux(struct ti_clk *setup);
|
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struct clk *ti_clk_register_divider(struct ti_clk *setup);
|
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struct clk *ti_clk_register_composite(struct ti_clk *setup);
|
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struct clk *ti_clk_register_dpll(struct ti_clk *setup);
|
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|
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struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
|
||||
struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
|
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struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
|
||||
|
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void ti_clk_patch_legacy_clks(struct ti_clk **patch);
|
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struct clk *ti_clk_register_clk(struct ti_clk *setup);
|
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int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
|
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|
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#endif
|
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|
|
@ -23,6 +23,8 @@
|
|||
#include <linux/clk/ti.h>
|
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#include <linux/list.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
|
|
@ -116,8 +118,44 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
|
|||
|
||||
#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
|
||||
|
||||
static void __init ti_clk_register_composite(struct clk_hw *hw,
|
||||
struct device_node *node)
|
||||
struct clk *ti_clk_register_composite(struct ti_clk *setup)
|
||||
{
|
||||
struct ti_clk_composite *comp;
|
||||
struct clk_hw *gate;
|
||||
struct clk_hw *mux;
|
||||
struct clk_hw *div;
|
||||
int num_parents = 1;
|
||||
const char **parent_names = NULL;
|
||||
struct clk *clk;
|
||||
|
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comp = setup->data;
|
||||
|
||||
div = ti_clk_build_component_div(comp->divider);
|
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gate = ti_clk_build_component_gate(comp->gate);
|
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mux = ti_clk_build_component_mux(comp->mux);
|
||||
|
||||
if (div)
|
||||
parent_names = &comp->divider->parent;
|
||||
|
||||
if (gate)
|
||||
parent_names = &comp->gate->parent;
|
||||
|
||||
if (mux) {
|
||||
num_parents = comp->mux->num_parents;
|
||||
parent_names = comp->mux->parents;
|
||||
}
|
||||
|
||||
clk = clk_register_composite(NULL, setup->name,
|
||||
parent_names, num_parents, mux,
|
||||
&ti_clk_mux_ops, div,
|
||||
&ti_composite_divider_ops, gate,
|
||||
&ti_composite_gate_ops, 0);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static void __init _register_composite(struct clk_hw *hw,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
|
||||
|
|
@ -136,7 +174,7 @@ static void __init ti_clk_register_composite(struct clk_hw *hw,
|
|||
pr_debug("component %s not ready for %s, retry\n",
|
||||
cclk->comp_nodes[i]->name, node->name);
|
||||
if (!ti_clk_retry_init(node, hw,
|
||||
ti_clk_register_composite))
|
||||
_register_composite))
|
||||
return;
|
||||
|
||||
goto cleanup;
|
||||
|
|
@ -216,7 +254,7 @@ static void __init of_ti_composite_clk_setup(struct device_node *node)
|
|||
for (i = 0; i < num_clks; i++)
|
||||
cclk->comp_nodes[i] = _get_component_node(node, i);
|
||||
|
||||
ti_clk_register_composite(&cclk->hw, node);
|
||||
_register_composite(&cclk->hw, node);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
|
||||
of_ti_composite_clk_setup);
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
#include "clock.h"
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
|
@ -300,6 +301,134 @@ static struct clk *_register_divider(struct device *dev, const char *name,
|
|||
return clk;
|
||||
}
|
||||
|
||||
static struct clk_div_table *
|
||||
_get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
|
||||
{
|
||||
int valid_div = 0;
|
||||
struct clk_div_table *table;
|
||||
int i;
|
||||
int div;
|
||||
u32 val;
|
||||
u8 flags;
|
||||
|
||||
if (!setup->num_dividers) {
|
||||
/* Clk divider table not provided, determine min/max divs */
|
||||
flags = setup->flags;
|
||||
|
||||
if (flags & CLKF_INDEX_STARTS_AT_ONE)
|
||||
val = 1;
|
||||
else
|
||||
val = 0;
|
||||
|
||||
div = 1;
|
||||
|
||||
while (div < setup->max_div) {
|
||||
if (flags & CLKF_INDEX_POWER_OF_TWO)
|
||||
div <<= 1;
|
||||
else
|
||||
div++;
|
||||
val++;
|
||||
}
|
||||
|
||||
*width = fls(val);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
for (i = 0; i < setup->num_dividers; i++)
|
||||
if (setup->dividers[i])
|
||||
valid_div++;
|
||||
|
||||
table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
|
||||
if (!table)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
valid_div = 0;
|
||||
*width = 0;
|
||||
|
||||
for (i = 0; i < setup->num_dividers; i++)
|
||||
if (setup->dividers[i]) {
|
||||
table[valid_div].div = setup->dividers[i];
|
||||
table[valid_div].val = i;
|
||||
valid_div++;
|
||||
*width = i;
|
||||
}
|
||||
|
||||
*width = fls(*width);
|
||||
|
||||
return table;
|
||||
}
|
||||
|
||||
struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
|
||||
{
|
||||
struct clk_divider *div;
|
||||
struct clk_omap_reg *reg;
|
||||
|
||||
if (!setup)
|
||||
return NULL;
|
||||
|
||||
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
||||
if (!div)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
reg = (struct clk_omap_reg *)&div->reg;
|
||||
reg->index = setup->module;
|
||||
reg->offset = setup->reg;
|
||||
|
||||
if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
|
||||
div->flags |= CLK_DIVIDER_ONE_BASED;
|
||||
|
||||
if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
|
||||
div->flags |= CLK_DIVIDER_POWER_OF_TWO;
|
||||
|
||||
div->table = _get_div_table_from_setup(setup, &div->width);
|
||||
|
||||
div->shift = setup->bit_shift;
|
||||
|
||||
return &div->hw;
|
||||
}
|
||||
|
||||
struct clk *ti_clk_register_divider(struct ti_clk *setup)
|
||||
{
|
||||
struct ti_clk_divider *div;
|
||||
struct clk_omap_reg *reg_setup;
|
||||
u32 reg;
|
||||
u8 width;
|
||||
u32 flags = 0;
|
||||
u8 div_flags = 0;
|
||||
struct clk_div_table *table;
|
||||
struct clk *clk;
|
||||
|
||||
div = setup->data;
|
||||
|
||||
reg_setup = (struct clk_omap_reg *)®
|
||||
|
||||
reg_setup->index = div->module;
|
||||
reg_setup->offset = div->reg;
|
||||
|
||||
if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
|
||||
div_flags |= CLK_DIVIDER_ONE_BASED;
|
||||
|
||||
if (div->flags & CLKF_INDEX_POWER_OF_TWO)
|
||||
div_flags |= CLK_DIVIDER_POWER_OF_TWO;
|
||||
|
||||
if (div->flags & CLKF_SET_RATE_PARENT)
|
||||
flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
table = _get_div_table_from_setup(div, &width);
|
||||
if (IS_ERR(table))
|
||||
return (struct clk *)table;
|
||||
|
||||
clk = _register_divider(NULL, setup->name, div->parent,
|
||||
flags, (void __iomem *)reg, div->bit_shift,
|
||||
width, div_flags, table, NULL);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
kfree(table);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static struct clk_div_table *
|
||||
__init ti_clk_get_div_table(struct device_node *node)
|
||||
{
|
||||
|
|
@ -455,7 +584,8 @@ static void __init of_ti_divider_clk_setup(struct device_node *node)
|
|||
goto cleanup;
|
||||
|
||||
clk = _register_divider(NULL, node->name, parent_name, flags, reg,
|
||||
shift, width, clk_divider_flags, table, NULL);
|
||||
shift, width, clk_divider_flags, table,
|
||||
NULL);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
#include "clock.h"
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
|
@ -130,7 +131,7 @@ static const struct clk_ops dpll_x2_ck_ops = {
|
|||
};
|
||||
|
||||
/**
|
||||
* ti_clk_register_dpll - low level registration of a DPLL clock
|
||||
* _register_dpll - low level registration of a DPLL clock
|
||||
* @hw: hardware clock definition for the clock
|
||||
* @node: device node for the clock
|
||||
*
|
||||
|
|
@ -138,8 +139,8 @@ static const struct clk_ops dpll_x2_ck_ops = {
|
|||
* clk-bypass is missing), the clock is added to retry list and
|
||||
* the initialization is retried on later stage.
|
||||
*/
|
||||
static void __init ti_clk_register_dpll(struct clk_hw *hw,
|
||||
struct device_node *node)
|
||||
static void __init _register_dpll(struct clk_hw *hw,
|
||||
struct device_node *node)
|
||||
{
|
||||
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
|
||||
struct dpll_data *dd = clk_hw->dpll_data;
|
||||
|
|
@ -151,7 +152,7 @@ static void __init ti_clk_register_dpll(struct clk_hw *hw,
|
|||
if (IS_ERR(dd->clk_ref) || IS_ERR(dd->clk_bypass)) {
|
||||
pr_debug("clk-ref or clk-bypass missing for %s, retry later\n",
|
||||
node->name);
|
||||
if (!ti_clk_retry_init(node, hw, ti_clk_register_dpll))
|
||||
if (!ti_clk_retry_init(node, hw, _register_dpll))
|
||||
return;
|
||||
|
||||
goto cleanup;
|
||||
|
|
@ -175,20 +176,116 @@ cleanup:
|
|||
kfree(clk_hw);
|
||||
}
|
||||
|
||||
void __iomem *_get_reg(u8 module, u16 offset)
|
||||
{
|
||||
u32 reg;
|
||||
struct clk_omap_reg *reg_setup;
|
||||
|
||||
reg_setup = (struct clk_omap_reg *)®
|
||||
|
||||
reg_setup->index = module;
|
||||
reg_setup->offset = offset;
|
||||
|
||||
return (void __iomem *)reg;
|
||||
}
|
||||
|
||||
struct clk *ti_clk_register_dpll(struct ti_clk *setup)
|
||||
{
|
||||
struct clk_hw_omap *clk_hw;
|
||||
struct clk_init_data init = { NULL };
|
||||
struct dpll_data *dd;
|
||||
struct clk *clk;
|
||||
struct ti_clk_dpll *dpll;
|
||||
const struct clk_ops *ops = &omap3_dpll_ck_ops;
|
||||
struct clk *clk_ref;
|
||||
struct clk *clk_bypass;
|
||||
|
||||
dpll = setup->data;
|
||||
|
||||
if (dpll->num_parents < 2)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
clk_ref = clk_get_sys(NULL, dpll->parents[0]);
|
||||
clk_bypass = clk_get_sys(NULL, dpll->parents[1]);
|
||||
|
||||
if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass))
|
||||
return ERR_PTR(-EAGAIN);
|
||||
|
||||
dd = kzalloc(sizeof(*dd), GFP_KERNEL);
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
|
||||
if (!dd || !clk_hw) {
|
||||
clk = ERR_PTR(-ENOMEM);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
clk_hw->dpll_data = dd;
|
||||
clk_hw->ops = &clkhwops_omap3_dpll;
|
||||
clk_hw->hw.init = &init;
|
||||
clk_hw->flags = MEMMAP_ADDRESSING;
|
||||
|
||||
init.name = setup->name;
|
||||
init.ops = ops;
|
||||
|
||||
init.num_parents = dpll->num_parents;
|
||||
init.parent_names = dpll->parents;
|
||||
|
||||
dd->control_reg = _get_reg(dpll->module, dpll->control_reg);
|
||||
dd->idlest_reg = _get_reg(dpll->module, dpll->idlest_reg);
|
||||
dd->mult_div1_reg = _get_reg(dpll->module, dpll->mult_div1_reg);
|
||||
dd->autoidle_reg = _get_reg(dpll->module, dpll->autoidle_reg);
|
||||
|
||||
dd->modes = dpll->modes;
|
||||
dd->div1_mask = dpll->div1_mask;
|
||||
dd->idlest_mask = dpll->idlest_mask;
|
||||
dd->mult_mask = dpll->mult_mask;
|
||||
dd->autoidle_mask = dpll->autoidle_mask;
|
||||
dd->enable_mask = dpll->enable_mask;
|
||||
dd->sddiv_mask = dpll->sddiv_mask;
|
||||
dd->dco_mask = dpll->dco_mask;
|
||||
dd->max_divider = dpll->max_divider;
|
||||
dd->min_divider = dpll->min_divider;
|
||||
dd->max_multiplier = dpll->max_multiplier;
|
||||
dd->auto_recal_bit = dpll->auto_recal_bit;
|
||||
dd->recal_en_bit = dpll->recal_en_bit;
|
||||
dd->recal_st_bit = dpll->recal_st_bit;
|
||||
|
||||
dd->clk_ref = clk_ref;
|
||||
dd->clk_bypass = clk_bypass;
|
||||
|
||||
if (dpll->flags & CLKF_CORE)
|
||||
ops = &omap3_dpll_core_ck_ops;
|
||||
|
||||
if (dpll->flags & CLKF_PER)
|
||||
ops = &omap3_dpll_per_ck_ops;
|
||||
|
||||
if (dpll->flags & CLKF_J_TYPE)
|
||||
dd->flags |= DPLL_J_TYPE;
|
||||
|
||||
clk = clk_register(NULL, &clk_hw->hw);
|
||||
|
||||
if (!IS_ERR(clk))
|
||||
return clk;
|
||||
|
||||
cleanup:
|
||||
kfree(dd);
|
||||
kfree(clk_hw);
|
||||
return clk;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
|
||||
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
|
||||
defined(CONFIG_SOC_AM43XX)
|
||||
/**
|
||||
* ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
|
||||
* _register_dpll_x2 - Registers a DPLLx2 clock
|
||||
* @node: device node for this clock
|
||||
* @ops: clk_ops for this clock
|
||||
* @hw_ops: clk_hw_ops for this clock
|
||||
*
|
||||
* Initializes a DPLL x 2 clock from device tree data.
|
||||
*/
|
||||
static void ti_clk_register_dpll_x2(struct device_node *node,
|
||||
const struct clk_ops *ops,
|
||||
const struct clk_hw_omap_ops *hw_ops)
|
||||
static void _register_dpll_x2(struct device_node *node,
|
||||
const struct clk_ops *ops,
|
||||
const struct clk_hw_omap_ops *hw_ops)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_init_data init = { NULL };
|
||||
|
|
@ -318,7 +415,7 @@ static void __init of_ti_dpll_setup(struct device_node *node,
|
|||
if (dpll_mode)
|
||||
dd->modes = dpll_mode;
|
||||
|
||||
ti_clk_register_dpll(&clk_hw->hw, node);
|
||||
_register_dpll(&clk_hw->hw, node);
|
||||
return;
|
||||
|
||||
cleanup:
|
||||
|
|
@ -332,7 +429,7 @@ cleanup:
|
|||
defined(CONFIG_SOC_DRA7XX)
|
||||
static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
|
||||
{
|
||||
ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
|
||||
_register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
|
||||
of_ti_omap4_dpll_x2_setup);
|
||||
|
|
@ -341,7 +438,7 @@ CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
|
|||
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
|
||||
static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
|
||||
{
|
||||
ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
|
||||
_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
|
||||
of_ti_am3_dpll_x2_setup);
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
#undef pr_fmt
|
||||
|
|
@ -90,63 +92,162 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static struct clk *_register_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, const struct clk_ops *ops,
|
||||
const struct clk_hw_omap_ops *hw_ops)
|
||||
{
|
||||
struct clk_init_data init = { NULL };
|
||||
struct clk_hw_omap *clk_hw;
|
||||
struct clk *clk;
|
||||
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
|
||||
if (!clk_hw)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
clk_hw->hw.init = &init;
|
||||
|
||||
init.name = name;
|
||||
init.ops = ops;
|
||||
|
||||
clk_hw->enable_reg = reg;
|
||||
clk_hw->enable_bit = bit_idx;
|
||||
clk_hw->ops = hw_ops;
|
||||
|
||||
clk_hw->flags = MEMMAP_ADDRESSING | clk_gate_flags;
|
||||
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
init.flags = flags;
|
||||
|
||||
clk = clk_register(NULL, &clk_hw->hw);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
kfree(clk_hw);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *ti_clk_register_gate(struct ti_clk *setup)
|
||||
{
|
||||
const struct clk_ops *ops = &omap_gate_clk_ops;
|
||||
const struct clk_hw_omap_ops *hw_ops = NULL;
|
||||
u32 reg;
|
||||
struct clk_omap_reg *reg_setup;
|
||||
u32 flags = 0;
|
||||
u8 clk_gate_flags = 0;
|
||||
struct ti_clk_gate *gate;
|
||||
|
||||
gate = setup->data;
|
||||
|
||||
if (gate->flags & CLKF_INTERFACE)
|
||||
return ti_clk_register_interface(setup);
|
||||
|
||||
reg_setup = (struct clk_omap_reg *)®
|
||||
|
||||
if (gate->flags & CLKF_SET_RATE_PARENT)
|
||||
flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
if (gate->flags & CLKF_SET_BIT_TO_DISABLE)
|
||||
clk_gate_flags |= INVERT_ENABLE;
|
||||
|
||||
if (gate->flags & CLKF_HSDIV) {
|
||||
ops = &omap_gate_clk_hsdiv_restore_ops;
|
||||
hw_ops = &clkhwops_wait;
|
||||
}
|
||||
|
||||
if (gate->flags & CLKF_DSS)
|
||||
hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait;
|
||||
|
||||
if (gate->flags & CLKF_WAIT)
|
||||
hw_ops = &clkhwops_wait;
|
||||
|
||||
if (gate->flags & CLKF_CLKDM)
|
||||
ops = &omap_gate_clkdm_clk_ops;
|
||||
|
||||
if (gate->flags & CLKF_AM35XX)
|
||||
hw_ops = &clkhwops_am35xx_ipss_module_wait;
|
||||
|
||||
reg_setup->index = gate->module;
|
||||
reg_setup->offset = gate->reg;
|
||||
|
||||
return _register_gate(NULL, setup->name, gate->parent, flags,
|
||||
(void __iomem *)reg, gate->bit_shift,
|
||||
clk_gate_flags, ops, hw_ops);
|
||||
}
|
||||
|
||||
struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
|
||||
{
|
||||
struct clk_hw_omap *gate;
|
||||
struct clk_omap_reg *reg;
|
||||
const struct clk_hw_omap_ops *ops = &clkhwops_wait;
|
||||
|
||||
if (!setup)
|
||||
return NULL;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
reg = (struct clk_omap_reg *)&gate->enable_reg;
|
||||
reg->index = setup->module;
|
||||
reg->offset = setup->reg;
|
||||
|
||||
gate->enable_bit = setup->bit_shift;
|
||||
|
||||
if (setup->flags & CLKF_NO_WAIT)
|
||||
ops = NULL;
|
||||
|
||||
if (setup->flags & CLKF_INTERFACE)
|
||||
ops = &clkhwops_iclk_wait;
|
||||
|
||||
gate->ops = ops;
|
||||
gate->flags = MEMMAP_ADDRESSING;
|
||||
|
||||
return &gate->hw;
|
||||
}
|
||||
|
||||
static void __init _of_ti_gate_clk_setup(struct device_node *node,
|
||||
const struct clk_ops *ops,
|
||||
const struct clk_hw_omap_ops *hw_ops)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_init_data init = { NULL };
|
||||
struct clk_hw_omap *clk_hw;
|
||||
const char *clk_name = node->name;
|
||||
const char *parent_name;
|
||||
void __iomem *reg = NULL;
|
||||
u8 enable_bit = 0;
|
||||
u32 val;
|
||||
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
|
||||
if (!clk_hw)
|
||||
return;
|
||||
|
||||
clk_hw->hw.init = &init;
|
||||
|
||||
init.name = clk_name;
|
||||
init.ops = ops;
|
||||
u32 flags = 0;
|
||||
u8 clk_gate_flags = 0;
|
||||
|
||||
if (ops != &omap_gate_clkdm_clk_ops) {
|
||||
clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
|
||||
if (!clk_hw->enable_reg)
|
||||
goto cleanup;
|
||||
reg = ti_clk_get_reg_addr(node, 0);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
clk_hw->enable_bit = val;
|
||||
enable_bit = val;
|
||||
}
|
||||
|
||||
clk_hw->ops = hw_ops;
|
||||
|
||||
clk_hw->flags = MEMMAP_ADDRESSING;
|
||||
|
||||
if (of_clk_get_parent_count(node) != 1) {
|
||||
pr_err("%s must have 1 parent\n", clk_name);
|
||||
goto cleanup;
|
||||
pr_err("%s must have 1 parent\n", node->name);
|
||||
return;
|
||||
}
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
if (of_property_read_bool(node, "ti,set-rate-parent"))
|
||||
init.flags |= CLK_SET_RATE_PARENT;
|
||||
flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
if (of_property_read_bool(node, "ti,set-bit-to-disable"))
|
||||
clk_hw->flags |= INVERT_ENABLE;
|
||||
clk_gate_flags |= INVERT_ENABLE;
|
||||
|
||||
clk = clk_register(NULL, &clk_hw->hw);
|
||||
clk = _register_gate(NULL, node->name, parent_name, flags, reg,
|
||||
enable_bit, clk_gate_flags, ops, hw_ops);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
if (!IS_ERR(clk))
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
kfree(clk_hw);
|
||||
}
|
||||
|
||||
static void __init
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
#include "clock.h"
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
|
@ -31,53 +32,100 @@ static const struct clk_ops ti_interface_clk_ops = {
|
|||
.is_enabled = &omap2_dflt_clk_is_enabled,
|
||||
};
|
||||
|
||||
static void __init _of_ti_interface_clk_setup(struct device_node *node,
|
||||
const struct clk_hw_omap_ops *ops)
|
||||
static struct clk *_register_interface(struct device *dev, const char *name,
|
||||
const char *parent_name,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
const struct clk_hw_omap_ops *ops)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_init_data init = { NULL };
|
||||
struct clk_hw_omap *clk_hw;
|
||||
const char *parent_name;
|
||||
u32 val;
|
||||
struct clk *clk;
|
||||
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
|
||||
if (!clk_hw)
|
||||
return;
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
clk_hw->hw.init = &init;
|
||||
clk_hw->ops = ops;
|
||||
clk_hw->flags = MEMMAP_ADDRESSING;
|
||||
clk_hw->enable_reg = reg;
|
||||
clk_hw->enable_bit = bit_idx;
|
||||
|
||||
clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
|
||||
if (!clk_hw->enable_reg)
|
||||
goto cleanup;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
clk_hw->enable_bit = val;
|
||||
|
||||
init.name = node->name;
|
||||
init.name = name;
|
||||
init.ops = &ti_interface_clk_ops;
|
||||
init.flags = 0;
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
if (!parent_name) {
|
||||
pr_err("%s must have a parent\n", node->name);
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
init.num_parents = 1;
|
||||
init.parent_names = &parent_name;
|
||||
|
||||
clk = clk_register(NULL, &clk_hw->hw);
|
||||
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
if (IS_ERR(clk))
|
||||
kfree(clk_hw);
|
||||
else
|
||||
omap2_init_clk_hw_omap_clocks(clk);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *ti_clk_register_interface(struct ti_clk *setup)
|
||||
{
|
||||
const struct clk_hw_omap_ops *ops = &clkhwops_iclk_wait;
|
||||
u32 reg;
|
||||
struct clk_omap_reg *reg_setup;
|
||||
struct ti_clk_gate *gate;
|
||||
|
||||
gate = setup->data;
|
||||
reg_setup = (struct clk_omap_reg *)®
|
||||
reg_setup->index = gate->module;
|
||||
reg_setup->offset = gate->reg;
|
||||
|
||||
if (gate->flags & CLKF_NO_WAIT)
|
||||
ops = &clkhwops_iclk;
|
||||
|
||||
if (gate->flags & CLKF_HSOTGUSB)
|
||||
ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
|
||||
|
||||
if (gate->flags & CLKF_DSS)
|
||||
ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
|
||||
|
||||
if (gate->flags & CLKF_SSI)
|
||||
ops = &clkhwops_omap3430es2_iclk_ssi_wait;
|
||||
|
||||
if (gate->flags & CLKF_AM35XX)
|
||||
ops = &clkhwops_am35xx_ipss_wait;
|
||||
|
||||
return _register_interface(NULL, setup->name, gate->parent,
|
||||
(void __iomem *)reg, gate->bit_shift, ops);
|
||||
}
|
||||
|
||||
static void __init _of_ti_interface_clk_setup(struct device_node *node,
|
||||
const struct clk_hw_omap_ops *ops)
|
||||
{
|
||||
struct clk *clk;
|
||||
const char *parent_name;
|
||||
void __iomem *reg;
|
||||
u8 enable_bit = 0;
|
||||
u32 val;
|
||||
|
||||
reg = ti_clk_get_reg_addr(node, 0);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
||||
enable_bit = val;
|
||||
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
if (!parent_name) {
|
||||
pr_err("%s must have a parent\n", node->name);
|
||||
return;
|
||||
}
|
||||
|
||||
cleanup:
|
||||
kfree(clk_hw);
|
||||
clk = _register_interface(NULL, node->name, parent_name, reg,
|
||||
enable_bit, ops);
|
||||
|
||||
if (!IS_ERR(clk))
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
}
|
||||
|
||||
static void __init of_ti_interface_clk_setup(struct device_node *node)
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
#include "clock.h"
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
|
@ -144,6 +145,39 @@ static struct clk *_register_mux(struct device *dev, const char *name,
|
|||
return clk;
|
||||
}
|
||||
|
||||
struct clk *ti_clk_register_mux(struct ti_clk *setup)
|
||||
{
|
||||
struct ti_clk_mux *mux;
|
||||
u32 flags;
|
||||
u8 mux_flags = 0;
|
||||
struct clk_omap_reg *reg_setup;
|
||||
u32 reg;
|
||||
u32 mask;
|
||||
|
||||
reg_setup = (struct clk_omap_reg *)®
|
||||
|
||||
mux = setup->data;
|
||||
flags = CLK_SET_RATE_NO_REPARENT;
|
||||
|
||||
mask = mux->num_parents;
|
||||
if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
|
||||
mask--;
|
||||
|
||||
mask = (1 << fls(mask)) - 1;
|
||||
reg_setup->index = mux->module;
|
||||
reg_setup->offset = mux->reg;
|
||||
|
||||
if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
|
||||
mux_flags |= CLK_MUX_INDEX_ONE;
|
||||
|
||||
if (mux->flags & CLKF_SET_RATE_PARENT)
|
||||
flags |= CLK_SET_RATE_PARENT;
|
||||
|
||||
return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
|
||||
flags, (void __iomem *)reg, mux->bit_shift, mask,
|
||||
mux_flags, NULL, NULL);
|
||||
}
|
||||
|
||||
/**
|
||||
* of_mux_clk_setup - Setup function for simple mux rate clock
|
||||
* @node: DT node for the clock
|
||||
|
|
@ -194,8 +228,9 @@ static void of_mux_clk_setup(struct device_node *node)
|
|||
|
||||
mask = (1 << fls(mask)) - 1;
|
||||
|
||||
clk = _register_mux(NULL, node->name, parent_names, num_parents, flags,
|
||||
reg, shift, mask, clk_mux_flags, NULL, NULL);
|
||||
clk = _register_mux(NULL, node->name, parent_names, num_parents,
|
||||
flags, reg, shift, mask, clk_mux_flags, NULL,
|
||||
NULL);
|
||||
|
||||
if (!IS_ERR(clk))
|
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
|
|
@ -205,6 +240,37 @@ cleanup:
|
|||
}
|
||||
CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
|
||||
|
||||
struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
|
||||
{
|
||||
struct clk_mux *mux;
|
||||
struct clk_omap_reg *reg;
|
||||
int num_parents;
|
||||
|
||||
if (!setup)
|
||||
return NULL;
|
||||
|
||||
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
||||
if (!mux)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
reg = (struct clk_omap_reg *)&mux->reg;
|
||||
|
||||
mux->shift = setup->bit_shift;
|
||||
|
||||
reg->index = setup->module;
|
||||
reg->offset = setup->reg;
|
||||
|
||||
if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
|
||||
mux->flags |= CLK_MUX_INDEX_ONE;
|
||||
|
||||
num_parents = setup->num_parents;
|
||||
|
||||
mux->mask = num_parents - 1;
|
||||
mux->mask = (1 << fls(mux->mask)) - 1;
|
||||
|
||||
return &mux->hw;
|
||||
}
|
||||
|
||||
static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
|
||||
{
|
||||
struct clk_mux *mux;
|
||||
|
|
|
|||
|
|
@ -218,6 +218,13 @@ struct ti_dt_clk {
|
|||
/* Maximum number of clock memmaps */
|
||||
#define CLK_MAX_MEMMAPS 4
|
||||
|
||||
/* Static memmap indices */
|
||||
enum {
|
||||
TI_CLKM_CM = 0,
|
||||
TI_CLKM_PRM,
|
||||
TI_CLKM_SCRM,
|
||||
};
|
||||
|
||||
typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
|
||||
|
||||
/**
|
||||
|
|
@ -349,4 +356,9 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
|
|||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
|
||||
|
||||
int omap3430_clk_legacy_init(void);
|
||||
int omap3430es1_clk_legacy_init(void);
|
||||
int omap36xx_clk_legacy_init(void);
|
||||
int am35xx_clk_legacy_init(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue