Samsung mach updates for v3.20
- add exynos3250 Supsend to RAM support - recognize MFC v8 devices for exynos5422/5800 - print CPU id/rev during kernel boot -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJUyXuOAAoJEA0Cl+kVi2xqOrwP/3MkfdxApwSVKGo7eg7xNA8i YJNDQM0Fdb1sTIxLD1ZJvz8rso1If/0wHkuWkmfje8zOoBEvL4C6jQq33KvWvtlS v5FqRjjvU8zz2wUBGu9cNkET3M6rKiiMANw8FiZJvVQa3RGL9WtFYtADZxJOy04Y ucbIGjJuha2oHrgWMNTW1OJUIvuJ3x8YGLUdDZVOffUMBqQxrz6UIun6juy/Xjio l8Gx9TJUhAmgMBzEhOV0BCfMWbdhLDZbq6ivfyUL19C5Y1lD6VbNlu2U26dVUQL5 bL3ZJ3F6NZbxQRwsj1TgesJzA6d293N1nFOOvHX3n/lU6vp3E2G+s6MpkC2Jm6xi V9n6iowqkLkLPTCMroVggdWMN0FkVPm37peRFi1+xtLYKfJLYfNz9i2qGYJtJtpz Qc+yJOai/mRLhRBPA3UeoOMeWhQgs6asIUAamEDPg2fUiaOqlZUESnjNaJyXuYDS py/jMQexc0+TAkBiC2lRAYo0yunWaJhNaYyVkLBhyi6LBJieqCRpwrDAaCSBrCoK 1FZaAmIo9cuhDxtIOy7vs4Y7z/PWvwTFrzL643IDwwlKr3cL0PE7+2zGLdtH8BTH HhtzlKGX1P9DdU6B7uBv5F8/33ZaolS8GRf8W+J2kpKzCOnd7AZ1kXvI2DgrHpUC oqUfn++rh1gafzTpB5Qm =MZnm -----END PGP SIGNATURE----- Merge tag 'samsung-update' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc Merge "Samsung mach updates for v3.20" from Kukjin Kim: - add exynos3250 Supsend to RAM support - recognize MFC v8 devices for exynos5422/5800 - print CPU id/rev during kernel boot * tag 'samsung-update' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Add exynos3250 suspend-to-ram support ARM: EXYNOS: Recognize Samsung MFC v8 devices ARM: SAMSUNG: print CPU id on probe Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
ff6a8168d2
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@ -282,6 +282,7 @@ static void __init exynos_reserve(void)
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"samsung,mfc-v5",
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"samsung,mfc-v6",
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"samsung,mfc-v7",
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"samsung,mfc-v8",
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};
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for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
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@ -160,12 +160,14 @@
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#define EXYNOS5_L2RSTDISABLE_VALUE BIT(3)
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#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
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#define S5P_PAD_RET_MMC2_OPTION 0x30c8
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#define S5P_PAD_RET_GPIO_OPTION 0x3108
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#define S5P_PAD_RET_UART_OPTION 0x3128
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#define S5P_PAD_RET_MMCA_OPTION 0x3148
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#define S5P_PAD_RET_MMCB_OPTION 0x3168
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#define S5P_PAD_RET_EBIA_OPTION 0x3188
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#define S5P_PAD_RET_EBIB_OPTION 0x31A8
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#define S5P_PAD_RET_SPI_OPTION 0x31c8
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#define S5P_PS_HOLD_CONTROL 0x330C
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#define S5P_PS_HOLD_EN (1 << 31)
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@ -326,6 +328,7 @@
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(EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80))
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#define EXYNOS3_ARM_COMMON_OPTION 0x2408
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#define EXYNOS3_ARM_L2_OPTION 0x2608
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#define EXYNOS3_TOP_PWR_OPTION 0x2C48
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#define EXYNOS3_CORE_TOP_PWR_OPTION 0x2CA8
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#define EXYNOS3_XUSBXTI_DURATION 0x341C
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@ -91,6 +91,12 @@ static unsigned int exynos_pmu_spare3;
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static u32 exynos_irqwake_intmask = 0xffffffff;
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static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
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{ 73, BIT(1) }, /* RTC alarm */
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{ 74, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
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{ 76, BIT(1) }, /* RTC alarm */
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{ 77, BIT(2) }, /* RTC tick */
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@ -114,6 +120,19 @@ unsigned int exynos_release_ret_regs[] = {
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REG_TABLE_END,
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};
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unsigned int exynos3250_release_ret_regs[] = {
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S5P_PAD_RET_MAUDIO_OPTION,
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S5P_PAD_RET_GPIO_OPTION,
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S5P_PAD_RET_UART_OPTION,
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S5P_PAD_RET_MMCA_OPTION,
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S5P_PAD_RET_MMCB_OPTION,
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S5P_PAD_RET_EBIA_OPTION,
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S5P_PAD_RET_EBIB_OPTION,
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S5P_PAD_RET_MMC2_OPTION,
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S5P_PAD_RET_SPI_OPTION,
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REG_TABLE_END,
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};
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unsigned int exynos5420_release_ret_regs[] = {
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EXYNOS_PAD_RET_DRAM_OPTION,
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EXYNOS_PAD_RET_MAUDIO_OPTION,
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@ -173,6 +192,12 @@ static int exynos_cpu_suspend(unsigned long arg)
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return exynos_cpu_do_idle();
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}
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static int exynos3250_cpu_suspend(unsigned long arg)
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{
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flush_cache_all();
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return exynos_cpu_do_idle();
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}
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static int exynos5420_cpu_suspend(unsigned long arg)
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{
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/* MCPM works with HW CPU identifiers */
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@ -230,6 +255,23 @@ static void exynos_pm_prepare(void)
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pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
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}
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static void exynos3250_pm_prepare(void)
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{
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unsigned int tmp;
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/* Set wake-up mask registers */
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exynos_pm_set_wakeup_mask();
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tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
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tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
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pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
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exynos_pm_enter_sleep_mode();
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/* ensure at least INFORM0 has the resume address */
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pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
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}
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static void exynos5420_pm_prepare(void)
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{
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unsigned int tmp;
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@ -344,6 +386,28 @@ early_wakeup:
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pmu_raw_writel(0x0, S5P_INFORM1);
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}
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static void exynos3250_pm_resume(void)
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{
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u32 cpuid = read_cpuid_part();
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if (exynos_pm_central_resume())
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goto early_wakeup;
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/* For release retention */
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exynos_pm_release_retention();
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pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
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if (call_firmware_op(resume) == -ENOSYS
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&& cpuid == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_restore_register();
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early_wakeup:
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/* Clear SLEEP mode set in INFORM1 */
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pmu_raw_writel(0x0, S5P_INFORM1);
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}
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static void exynos5420_prepare_pm_resume(void)
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{
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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@ -483,6 +547,16 @@ static const struct platform_suspend_ops exynos_suspend_ops = {
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.valid = suspend_valid_only_mem,
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};
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static const struct exynos_pm_data exynos3250_pm_data = {
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.wkup_irq = exynos3250_wkup_irq,
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.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
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.release_ret_regs = exynos3250_release_ret_regs,
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.pm_suspend = exynos_pm_suspend,
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.pm_resume = exynos3250_pm_resume,
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.pm_prepare = exynos3250_pm_prepare,
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.cpu_suspend = exynos3250_cpu_suspend,
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};
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static const struct exynos_pm_data exynos4_pm_data = {
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.wkup_irq = exynos4_wkup_irq,
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.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
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@ -518,6 +592,9 @@ static struct exynos_pm_data exynos5420_pm_data = {
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static struct of_device_id exynos_pmu_of_device_ids[] = {
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{
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.compatible = "samsung,exynos3250-pmu",
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.data = &exynos3250_pm_data,
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}, {
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.compatible = "samsung,exynos4210-pmu",
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.data = &exynos4_pm_data,
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}, {
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@ -40,10 +40,14 @@ void __init s3c64xx_init_cpu(void)
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}
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samsung_cpu_rev = 0;
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pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);
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}
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void __init s5p_init_cpu(void __iomem *cpuid_addr)
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{
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samsung_cpu_id = __raw_readl(cpuid_addr);
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samsung_cpu_rev = samsung_cpu_id & 0xFF;
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pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);
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}
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