Commit Graph

13 Commits

Author SHA1 Message Date
Sanchayan Maity c205389557 ARM: imx: clk-vf610: Add clock for SNVS
Add support for clock gating of the SNVS peripheral.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-13 19:16:26 +08:00
Bhuvanchandra DV 6f540db781 ARM: imx: clk-vf610: Add clock for UART4 and UART5
Add support for clock gating of UART4 and UART5.
We use these UART's in a (not yet mainlined)
device tree.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-13 18:43:09 +08:00
Stefan Agner 60ad8467c1 ARM: imx: pllv3: add shift for frequency multiplier
Add shift capabilties for the frequency multiplier (DIV_SELECT) to
support Vybrid's USB PLL oddity. The PLL3 and PLL7 are the only
PLL control registers which have the DIV_SELECT bit shifted by
one. Be aware, there are known documentation errors in the
reference manual too.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-05 20:53:05 +08:00
Stefan Agner a41820d690 ARM: imx: clk-vf610: get input clocks from assigned clocks
With the clock assignment device tree changes, the clocks get
initialized properly but the search for those clocks fails with
errors:

[    0.000000] i.MX clk 4: register failed with -17
[    0.000000] i.MX clk 5: register failed with -17

This is because the module can't find those clocks anymore, and
tries to initialize fixed clocks with the same name.

Get the clock modules input clocks from the assigned clocks by
default by using of_clk_get_by_name(). If this function returns
not a valid clock, fall back to the old behaviour and search the
input clock from the device tree's /clocks/$name node.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23 14:56:21 +08:00
Stefan Agner c72c553249 ARM: imx: clk-vf610: define PLL's clock tree
So far, the required PLL's (PLL1/PLL2/PLL5) have been initialized
by boot loader and the kernel code defined fixed rates according
to those default configurations. Beginning with the USB PLL7 the
code started to initialize the PLL's itself (using imx_clk_pllv3).

However, since commit dc4805c2e7
(ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver)
imx_clk_pllv3 no longer takes care of the ENABLE and BYPASS bits,
hence the USB PLL were not configured correctly anymore.

This patch not only fixes those USB PLL's, but also makes use of
the imx_clk_pllv3 for all PLL's and alignes the code with the PLL
support of the i.MX6 series.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-04 13:40:14 +08:00
Stefan Agner 21231f81f1 ARM: imx: clk-vf610: Add USBPHY clocks
This commit adds PLL7 which is required for USBPHY1. It also adds
the USB PHY and USB Controller clocks and the gates to enable them.

Acked-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16 10:06:45 +08:00
Stefan Agner 3b18dd7a86 ARM: imx: clk-vf610: introduce clks_init_on
At the end of the boot process, the clock framework might disable
required main PLL's. So far, this was no issue since drivers
requested clocks, which are descended of the main PLL's (e.g.
pll1_pfd1, which provides the system clock).

To archive the full 500MHz system clock, DDR clock need to be a
descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The
bootloader sets up the clocks accordingly before making use of
DDR at all. However, in Linux, there is no driver using PLL2,
which lead to PLL2 being disabled by the clock framework.

With this patch, we make sure that the main system clock and the
DDR clock are initially enabled and are kept enabled.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-09-16 10:06:44 +08:00
Stefan Agner 4349c4298f ARM: imx: clk-vf610: fix FlexCAN clock gating
Extend the clock control for FlexCAN with the second gate which
enable the clocks in the Clock Divider (CCM_CSCDR2) register too.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18 16:11:40 +08:00
Alexander Shiyan 229be9c141 ARM: i.MX clk: Move clock check function in common location
This patch moves clock check function in common i.MX location
and switch i.MX clk drivers to use this new function.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18 16:10:12 +08:00
Liu Ying b78f1e8074 ARM: imx: clk-vf610: Suppress duplicate const sparse warning
There should be no duplicate const specifiers for those static
constant character string arrays defined for clock mux options.
Also, the arrays are only taken as the 5th argument for the
imx_clk_mux() function, which is in the type of 'const char
**parents'.  So, let's remove the 2nd const specifier right
after 'char'.

This patch fixes these sparse warnings:
arch/arm/mach-imx/clk-vf610.c:66:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:67:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:68:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:69:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:70:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:71:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:72:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:73:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:74:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:75:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:76:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:77:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:78:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:79:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:80:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:81:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:83:25: warning: duplicate const
arch/arm/mach-imx/clk-vf610.c:84:25: warning: duplicate const

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-03-05 10:35:08 +08:00
Jingchang Lu daaff6e95b ARM: imx: Add DMAMUX clock for Vybrid vf610 SoC
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-12-09 13:18:31 +08:00
Shawn Guo 4f71612ee3 ARM: imx: fix vf610 enet module clock selection
The fec/enet driver calculates MDC rate with the formula below.

  ref_freq / ((MII_SPEED + 1) x 2)

The ref_freq here is the fec internal module clock, which is missing
from clk-vf610 clock driver right now.  And clk-vf610 driver mistakenly
supplies RMII clock (50 MHz) as the source to fec.  This results in the
situation that fec driver gets ref_freq as 50 MHz, while physically it
runs at 66 MHz (fec module clock physically sources from ipg which runs
at 66 MHz).  That's why software expects MDC runs at 2.5 MHz, while the
measurement tells it runs at 3.3 MHz.  And this causes the PHY KSZ8041
keeps swithing between Full and Half mode as below.

  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half
  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half
  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half

Add the missing module clock for ENET0 and ENET1, and correct the clock
supplying in device tree to fix above issue.

Thanks to Alison Wang <b18965@freescale.com> for debugging the issue.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-07-15 08:28:09 +08:00
Jingchang Lu 1f2c5fd5f0 ARM: imx: add VF610 clock support
Add clock support for Vybrid VF610. It uses dtc macro support to
define all clock IDs in vf610-clock.h to keep clock IDs coherence
between kernel and DT.

Signed-off-by: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-17 15:45:15 +08:00