Commit Graph

1705 Commits

Author SHA1 Message Date
Thomas Gleixner 28a283aae3 bfin: Use proper accessors in trace
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-29 14:47:59 +02:00
Thomas Gleixner 43f2f1154a bfin: Convert irq namespace
Convert to the new function names. Scripted with coccinelle.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: uclinux-dist-devel@blackfin.uclinux.org
2011-03-29 14:47:59 +02:00
Thomas Gleixner 1907d8be2d bfin: Final irq cleanup
Use the trigger type in irq_data and check level type instead of
looking at desc->handle_irq.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: uclinux-dist-devel@blackfin.uclinux.org
2011-03-29 14:47:59 +02:00
Linus Torvalds 05061bf678 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin:
  Blackfin: bf54x: re-enable anomaly 05000353 for all revs
  Blackfin: enable atomic64_t support
  Blackfin: wire up new syncfs syscall
  Blackfin: SMP: flush CoreB cache when shutting down
2011-03-24 08:24:28 -07:00
Akinobu Mita 61f2e7b0f4 bitops: remove minix bitops from asm/bitops.h
minix bit operations are only used by minix filesystem and useless by
other modules.  Because byte order of inode and block bitmaps is different
on each architecture like below:

m68k:
	big-endian 16bit indexed bitmaps

h8300, microblaze, s390, sparc, m68knommu:
	big-endian 32 or 64bit indexed bitmaps

m32r, mips, sh, xtensa:
	big-endian 32 or 64bit indexed bitmaps for big-endian mode
	little-endian bitmaps for little-endian mode

Others:
	little-endian bitmaps

In order to move minix bit operations from asm/bitops.h to architecture
independent code in minix filesystem, this provides two config options.

CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED is only selected by m68k.
CONFIG_MINIX_FS_NATIVE_ENDIAN is selected by the architectures which use
native byte order bitmaps (h8300, microblaze, s390, sparc, m68knommu,
m32r, mips, sh, xtensa).  The architectures which always use little-endian
bitmaps do not select these options.

Finally, we can remove minix bit operations from asm/bitops.h for all
architectures.

Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Roman Zippel <zippel@linux-m68k.org>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Michal Simek <monstr@monstr.eu>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-03-23 19:46:22 -07:00
Akinobu Mita f312eff816 bitops: remove ext2 non-atomic bitops from asm/bitops.h
As the result of conversions, there are no users of ext2 non-atomic bit
operations except for ext2 filesystem itself.  Now we can put them into
architecture independent code in ext2 filesystem, and remove from
asm/bitops.h for all architectures.

Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Jan Kara <jack@suse.cz>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-03-23 19:46:21 -07:00
Akinobu Mita 861b5ae7cd bitops: introduce little-endian bitops for most architectures
Introduce little-endian bit operations to the big-endian architectures
which do not have native little-endian bit operations and the
little-endian architectures.  (alpha, avr32, blackfin, cris, frv, h8300,
ia64, m32r, mips, mn10300, parisc, sh, sparc, tile, x86, xtensa)

These architectures can just include generic implementation
(asm-generic/bitops/le.h).

Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Mikael Starvik <starvik@axis.com>
Cc: David Howells <dhowells@redhat.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Matthew Wilcox <willy@debian.org>
Cc: Grant Grundler <grundler@parisc-linux.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Zankel <chris@zankel.net>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Acked-by: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-03-23 19:46:15 -07:00
Mike Frysinger de55aa33ca Blackfin: bf54x: re-enable anomaly 05000353 for all revs
Even though the anomaly sheet says that the the bootrom is fixed, tests
have shown that the fix itself does not handle all cases.  So until we
get a ROM update, assume the reset code is still broken and we need to
handle things ourselves.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-22 21:06:16 -04:00
Mike Frysinger bee18bebda Blackfin: enable atomic64_t support
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-22 21:03:17 -04:00
Mike Frysinger 4e3d96deff Blackfin: wire up new syncfs syscall
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-22 21:03:16 -04:00
Graf Yang 1e924e2f1e Blackfin: SMP: flush CoreB cache when shutting down
When CoreB wakes up, it needs to read variables that CoreA might have
modified, and might be in CoreB's cache.  So kill CoreB's cache before
going to sleep so that when we wake up, we are in a coherent state.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-22 21:03:16 -04:00
Mike Frysinger 0c082bd158 Blackfin: ip0x: fix unused variable warning
The previous commit that changed this code to the common GPIO layers
forgot to delete the local and now unused "i" variable.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 05:17:02 -04:00
Mike Frysinger 58ee0d3bb1 Blackfin: punt unused HDMA masks
No code uses these, and the short define names are polluting the global
namespace where they collide with things like common irq files.  So just
punt the damned things.  If in the future we need HDMA support, we can
make a standalone header for these things.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:29:17 -04:00
Mike Frysinger a8d0142fb7 Blackfin: wire up new syscalls
Hook up name_to_handle_at, open_by_handle_at, and clock_adjtime.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:05:25 -04:00
Philippe Gerum 1353d050fa Blackfin/ipipe: restore pipeline bits in irqflags
This patch fixes the Blackfin irqflags to make them I-pipe aware anew,
after the introduction of the hard_local_irq_*() API.

Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:11 -04:00
Philippe Gerum 9169b51f8c Blackfin/ipipe: fix deferred pipeline sync for the root stage
This patch makes sure to sync the pipeline for the root stage only
from the outer interrupt level, when resuming kernel code after an
interrupt.

This fixes a bug causing EVT15 to be spuriously popped off upon nested
interrupts, which in turn would cause the preempted kernel code to
resume without supervisor privileges.

Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:11 -04:00
Philippe Gerum 5b5da4c4b8 Blackfin/ipipe: upgrade to I-pipe mainline
This patch introduces Blackfin-specific bits to support the current
tip of the interrupt pipeline development, mainly:

- 2/3-level interrupt maps (sparse IRQs)
- generic virq handling
- sysinfo v2 format for ipipe_get_sysinfo()

Signed-off-by: Philippe Gerum <rpm@xenomai.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:10 -04:00
Michael Hennerich 8944b5a258 Blackfin: cpufreq: fix typos
No functional changes here.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:10 -04:00
Thomas Gleixner 1eb5efa0e4 Blackfin: enable GENERIC_HARDIRQS_NO_DEPRECATED
All chips converted.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:09 -04:00
Mike Frysinger 91796c235d Blackfin: SMP: convert to irq chip functions
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:09 -04:00
Thomas Gleixner 9f51a874ce Blackfin: use accessor functions in show_interrupts()
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:08 -04:00
Thomas Gleixner bc2f6bd802 Blackfin: use proper wrapper functions for modifying irq status
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:08 -04:00
Thomas Gleixner e9502850b9 Blackfin: convert gpio irq_chip to new functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:07 -04:00
Thomas Gleixner 172d2d1d84 Blackfin: convert mac irq_chip to new functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:07 -04:00
Thomas Gleixner dabf64bcc5 Blackfin: convert error irq_chip to new functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:06 -04:00
Thomas Gleixner ff43a67f67 Blackfin: convert internal irq_chip to new functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:06 -04:00
Thomas Gleixner 4f19ea4978 Blackfin: convert core irq_chip to new functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:05 -04:00
Thomas Gleixner b10bbbbce7 Blackfin: use proper wrappers for irq_desc
Fixup the open coded access to irq_desc and use the proper wrappers.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:05 -04:00
Mike Frysinger 511cdcc500 Blackfin: optimize startup code
Take advantage of more Blackfin-specific insns, and only initialize
registers required by the ABI.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:04 -04:00
Sonic Zhang c6345ab1a3 Blackfin: SMP: work around anomaly 05000491
In order to safely work around anomaly 05000491, we have to execute IFLUSH
from L1 instruction sram.  The trouble with multi-core systems is that all
L1 sram is visible only to the active core.  So we can't just place the
functions into L1 and call it directly.  We need to setup a jump table and
place the entry point in external memory.  This will call the right func
based on the active core.

In the process, convert from the manual relocation of a small bit of code
into Core B's L1 to the more general framework we already have in place
for loading arbitrary pieces of code into L1.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:04 -04:00
Graf Yang 6f546bc3ac Blackfin: SMP: implement cpu_freq support
Re-use some of the existing cpu hotplugging code in the process.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:03 -04:00
Mike Frysinger 820b127dae Blackfin: split optimization settings more
We need to place icache flush funcs into L1 inst sram to work around a
hardware anomaly.  But this currently breaks SMP support as the L1 inst
sram is per-core and cannot be called directly.  So in preparation for
making that work, split the two options.

Further, split out the SMP depend so that we can allow some for SMP.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:03 -04:00
Sonic Zhang 567ebfc99d Blackfin: SMP: disable preempt with smp_processor_id to send messages
The smp_processor_id() API requires that preempt be disabled when calling
it, so make sure it is when we go to send messages to other processors.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:02 -04:00
steven miao ab61d2ac5c Blackfin: SMP: delay enabling caches until CPU is initialized
Defer bfin_setup_caches(cpu) to avoid unexpected faults due to the cpu
state not yet being fully initialized.

Signed-off-by: steven miao <realmz6@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:02 -04:00
Mike Frysinger 5f362c91d0 Blackfin: SMP: use standard cache functions
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:01 -04:00
steven miao ef9d8c251a Blackfin: SMP: PERCPU section should be PAGE aligned
Common code checks the alignment of some of the variables and calls BUG()
if they aren't page aligned.

Signed-off-by: steven miao <realmz6@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 04:01:01 -04:00
Mike Frysinger d6b435be4b Blackfin: ADI boards: enable pseudo debug insns support
We use these insns when testing, so enable them by default for all
of our development boards.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 03:49:26 -04:00
Sonic Zhang cdb92f6794 Blackfin: kgdb: drop dead KGDB_THR_PROC_SWAP for SMP systems
Common code no longer defines this, so stop using it.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 03:49:26 -04:00
Andreas Schallenberg adfe6a4882 Blackfin: dnp5370: drop MMC card detect support
The board doesn't actually have a pin hooked up to do card detection,
so punt the code for it.

Signed-off-by: Andreas Schallenberg <Andreas.Schallenberg@3alitydigital.de>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 03:49:25 -04:00
Mike Frysinger b5fc12df90 Blackfin: add bfin_write_{or,and} helpers
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 03:49:24 -04:00
Aaron Wu 4c131c8c23 Blackfin: bf548-ezkit: add CAN1 support
Signed-off-by: Aaron Wu <aaronwu06@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 03:49:24 -04:00
steven miao 55835175a0 Blackfin: bf54x: add kconfig for UART2/3 DMA channel assignments
The BF54x lacks dedicated DMA channels for the UART peripherals and need
to be muxed between others.  So add a kconfig option so people can select
which channels the UARTs will use so they can pick between SPORTs and the
less commonly used EPPI/PIXC peripherals.

Signed-off-by: steven miao <realmz6@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 03:49:23 -04:00
Sonic Zhang 6ce0466d63 Blackfin: SMP: avoid section mismatch warnings
Since coreb_trampoline_start() calls coreb_start(), they need to be in
the same section.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 03:49:22 -04:00
Linus Torvalds 79d8a8f736 Merge branch 'for-2.6.39' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu
* 'for-2.6.39' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu:
  percpu, x86: Add arch-specific this_cpu_cmpxchg_double() support
  percpu: Generic support for this_cpu_cmpxchg_double()
  alpha: use L1_CACHE_BYTES for cacheline size in the linker script
  percpu: align percpu readmostly subsection to cacheline

Fix up trivial conflict in arch/x86/kernel/vmlinux.lds.S due to the
percpu alignment having changed ("x86: Reduce back the alignment of the
per-CPU data section")
2011-03-16 08:22:41 -07:00
Linus Torvalds 420c1c572d Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (62 commits)
  posix-clocks: Check write permissions in posix syscalls
  hrtimer: Remove empty hrtimer_init_hres_timer()
  hrtimer: Update hrtimer->state documentation
  hrtimer: Update base[CLOCK_BOOTTIME].offset correctly
  timers: Export CLOCK_BOOTTIME via the posix timers interface
  timers: Add CLOCK_BOOTTIME hrtimer base
  time: Extend get_xtime_and_monotonic_offset() to also return sleep
  time: Introduce get_monotonic_boottime and ktime_get_boottime
  hrtimers: extend hrtimer base code to handle more then 2 clockids
  ntp: Remove redundant and incorrect parameter check
  mn10300: Switch do_timer() to xtimer_update()
  posix clocks: Introduce dynamic clocks
  posix-timers: Cleanup namespace
  posix-timers: Add support for fd based clocks
  x86: Add clock_adjtime for x86
  posix-timers: Introduce a syscall for clock tuning.
  time: Splitout compat timex accessors
  ntp: Add ADJ_SETOFFSET mode bit
  time: Introduce timekeeping_inject_offset
  posix-timer: Update comment
  ...

Fix up new system-call-related conflicts in
	arch/x86/ia32/ia32entry.S
	arch/x86/include/asm/unistd_32.h
	arch/x86/include/asm/unistd_64.h
	arch/x86/kernel/syscall_table_32.S
(name_to_handle_at()/open_by_handle_at() vs clock_adjtime()), and some
due to movement of get_jiffies_64() in:
	kernel/time.c
2011-03-15 18:53:35 -07:00
Mike Frysinger be1229b4c5 Blackfin: iflush: update anomaly 05000491 workaround
Recent feedback from design says we need three NOPs in the hardware loop.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-04 01:27:01 -05:00
Mike Frysinger bb7b11290a Blackfin: outs[lwb]: make sure count is greater than 0
Some devices will use the outs* funcs with a length of zero, so make sure
we do not write any data in that case.

Reported-by: Gilbert Inho <gneny@edevice.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-04 01:26:55 -05:00
Sonic Zhang 0f66e50af5 serial: bfin_5xx: split uart RX lock from uart port lock to avoid deadlock
The RX lock is used to protect the RX buffer from concurrent access in DMA
mode between the timer and RX interrupt routines.  It is independent from
the uart lock which is used to protect the TX buffer.  It is possible for
a uart TX transfer to be started up from the RX interrupt handler if low
latency is enabled.  So we need to split the locks to avoid deadlocking in
this situation.

In PIO mode, the RX lock is not necessary because the handle_simple_irq
and handle_level_irq functions ensure driver interrupt handlers are called
once on one core.

And now that the RX path has its own lock, the TX interrupt has nothing to
do with the RX path, so disabling it at the same time.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-02-03 14:44:54 -08:00
Torben Hohn 4196b892d5 blackfin: Switch from do_timer() to xtime_update()
xtime_update() takes the xtime_lock itself.

Signed-off-by: Torben Hohn <torbenh@gmx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: johnstul@us.ibm.com
Cc: hch@infradead.org
Cc: yong.zhang0@gmail.com
LKML-Reference: <20110127145931.23248.33917.stgit@localhost>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-01-31 14:55:44 +01:00
Tejun Heo 19df0c2fef percpu: align percpu readmostly subsection to cacheline
Currently percpu readmostly subsection may share cachelines with other
percpu subsections which may result in unnecessary cacheline bounce
and performance degradation.

This patch adds @cacheline parameter to PERCPU() and PERCPU_VADDR()
linker macros, makes each arch linker scripts specify its cacheline
size and use it to align percpu subsections.

This is based on Shaohua's x86 only patch.

Signed-off-by: Tejun Heo <tj@kernel.org>
Cc: Shaohua Li <shaohua.li@intel.com>
2011-01-25 14:26:50 +01:00