Commit Graph

7 Commits

Author SHA1 Message Date
Gabriel FERNANDEZ 20e40edc3e ARM: STi: DT: STiH415: 415 DT Entry for clockgen A9
Patch adds DT entries for clockgen A9

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-05-21 14:27:14 +02:00
Gabriel FERNANDEZ 2db100dfb2 ARM: STi: DT: STiH415: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed clocks
CLK_S_GMAC0_PHY &  CLK_S_ETH1_PH clocks are no longer used.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-05-21 14:27:13 +02:00
Gabriel FERNANDEZ 5aa02b9029 ARM: STi: DT: STiH415: Remove unused CLK_S_ICN_REG_0 fixed clock
CLK_S_ICN_REG_0 clock is no longer used.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-05-21 14:27:12 +02:00
Gabriel FERNANDEZ f317e689cb ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12
Patch adds DT entries for clockgen A0/1/10/11/12

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-05-21 14:27:12 +02:00
Gabriel FERNANDEZ ed3593f986 ARM: STi: DT: STiH41x: Rename CLK_SYSIN into clk_sysin
all-caps node name is not very usual.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2014-05-21 14:27:08 +02:00
Srinivas Kandagatla c80fe3357f ARM: STi: STiH415: Add ethernet support.
This patch adds support to STiH415 SOC, which has two ethernet
snps,dwmac controllers version 3.610. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.

Tested on both B2020 and B2000.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
2014-03-11 10:04:00 +00:00
Srinivas Kandagatla 65ebcc1158 ARM: sti: Add STiH415 SOC support
The STiH415 is the next generation of HD, AVC set-top box processors for
satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9
1.0 GHz, dual-core CPU.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
CC: Stephen Gallimore <stephen.gallimore@st.com>
CC: Stuart Menefy <stuart.menefy@st.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-25 13:26:47 -07:00