Commit Graph

130 Commits

Author SHA1 Message Date
Markus Pargmann 30612cd900 pinctrl: imx1 core driver
Core driver for register formats of imx1/imx21/imx27 processors.

The pins of those processors are grouped into ports. Each port has 32
pins. The pins mux configuration is controlled by registers with 1 or 2
bit per pin, depending on the specific control register.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-29 06:54:37 -07:00
Christian Ruppert 5aad0db1c1 pinctrl: add TB10x pin control driver
The pinmux driver of the Abilis Systems TB10x platform based on ARC700 CPUs.
Used to control the pinmux and is a prerequisite for the GPIO driver.

Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Pierrick Hascoet <pierrick.hascoet@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-16 15:33:51 +02:00
Laxman Dewangan c8ce878206 pincntrl: add support for ams AS3722 pin control driver
The AS3722 is a compact system PMU suitable for mobile phones, tablets etc.

Add a driver to support accessing the GPIO, pinmux and pin configuration
of 8 GPIO pins found on the ams AS3722 through pin control driver and
gpiolib.

The driver will register itself as the pincontrol driver and gpio driver.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-10 17:38:29 +02:00
Sonic Zhang e9a03add0c pinctrl: ADI PIN control driver for the GPIO controller on bf54x and bf60x.
The new ADI GPIO2 controller was introduced since the BF548 and BF60x
processors. It differs a lot from the old one on BF5xx processors. So,
create a pinctrl driver under the pinctrl framework.

- Define gpio ports and pin interrupt controllers as individual platform
  devices.
- Register a pinctrl driver for the whole GPIO ports and pin interrupt
  devices.
- Probe pint devices before port devices. Put device instances into
  the global gpio and pint lists.
- Define peripheral, irq and gpio reservation bit masks for each gpio
  port as runtime resources.
- Save and restore gpio port and pint status MMRs in syscore PM functions.
- Create the plug-in subdrivers to hold the pinctrl soc data for bf54x
  and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data
  in pin controller probe function. Get the pin groups and functions via
  the soc data reference.
- Call gpiochip_add_pin_range() in gpio device probe function to register
  range cross reference between gpio device and pin control device.
- Get range by pinctrl_find_gpio_range_from_pin(), find gpio_port object
  by container_of() and find adi_pinctrl by pin control device name.
- Handle peripheral and gpio requests in pinctrl operation functions.
- Demux gpio IRQs via the irq_domain created by each GPIO port.

v2-changes:
- Remove unlinke() directive.

v3-changes:
- Rename struct adi_pmx to adi_pinctrl.
- Fix the comments of struct gpio_pint.
- Remove unused pin_base in struct gpio_port.
- Change pint_assign into bool type.
- Add comments about the relationship between pint device and port device
to the driver header.
- Use BIT macro to shift bit.
- Remove all bitmap reservation help functions. Inline reservation functions
into the actual code.
- Remove gpio and offset mutual reference help functions.
- Remove all help functions to find gpio_port and adi_pinctrl structs. Get
range by pinctrl_find_gpio_range_from_pin(), find gpio_port object by
container_of() and find adi_pinctrl by pin control device name.
- Pass bool type usage variable to port_setup help function.
- Separate long bit operations into several lines and add comments.
- Use debugfs to output all GPIO request information.
- Avoid to set drvdata to NULL
- Add explanation to function adi_gpio_init_int()
- Call gpiochip_add_pin_range() in gpio device probe function to register
range cross reference between gpio device and pin control device.
- Remove the reference to pin control device from the gpio_port struct.
Remove the reference list to gpio device from the adi_pinctrl struct.
Replace the global adi_pinctrl list with adi_gpio_port_list. Walk through
the gpio list to do power suspend and resume operations.
- Remove the global GPIO base from struct adi_pinctrl, define pin base in
the platform data for each GPIO port device.
- Initialize adi_pinctrl_setup in arch_initcall().
- print the status of triggers, whether it is in GPIO mode, if it is
flagged to be used as IRQ, etc in adi_pin_dbg_show().
- Create the plug-in subdrivers to hold the pinctrl soc data for bf54x
and bf60x. Add soc data into struct adi_pinctrl. Initialize the soc data
in pin controller probe function. Get the pin groups and functions via
the soc data reference.

v4-changes:
- remove useless system_state checking.
- replace dev_err with dev_warn in both irq and gpio pin cases.
- comment on relationship between irq type and invert operation.
- It is not necessary to check the reservation mode of the requested
pin in IRQ chip operation. Remove the reservation map.
- Use existing gpio/pinctrl subsystem debugfs files. Remove pinctrl-adi2
driver specific debugfs output.
- Add linkport group and function information for bf60x.
- Separate uart and ctsrts pins into 2 groups.
- Separate APAPI and alternative ATAPI pins into 2 groups.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-19 14:37:27 +02:00
Laxman Dewangan 0a8d3e2412 pinctrl: palmas: add pincontrol driver
TI Palmas series Power Management IC have multiple pins which can be
configured for different functionality. This pins can be configured
for different function. Also their properties like pull up/down,
open drain enable/disable are configurable.

Add support for pincontrol driver Palmas series device like TPS65913,
TPS80036. The driver supports to be register from DT only.

Changes from V1:
- Add generic property for pins and functions in pinconf-generic.
- Add APIs to map the DT and subnode.
- Move common utils APIs to the pinctrl-utils from this file.
- Update the binding document accordingly.
Changes from V2:
- Add ack by Lee.
- Correct the binding docs.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 21:00:42 +02:00
Laxman Dewangan 1eb207a9ec pinctrl: add utility functions for add map/configs
Some of pincontrol driver needs the utility function to create map
list. The utility function needed for adding mux, configs etc.

In place of duplicating this in each driver, add the common utility
function in common file and use from device specific driver. This will
reduce the duplicating of code across drivers.

Changes from V1:
- Add this files in this patch and add common utility APIs to here.

Changes from V2:
- Nothing in code.
- Added Reviewed by Stephen.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14 21:00:41 +02:00
Linus Torvalds 3dbde57ad9 Pin control changes for the v3.11 kernel cycle:
- A large slew of improvements of the Genric pin configuration
   support, and deployment in four different platforms:
   Rockchip, Super-H PFC, ABx500 and TZ1090. Support BIAS_BUS_HOLD,
   get device tree parsing and debugfs support into shape.
 
 - We also have device tree support with generic naming conventions
   for the generic pin configuration.
 
 - Delete the unused and confusing direct pinconf API. Now state
   transitions is *the* way to control pins and multiplexing.
 
 - New drivers for Rockchip, TZ1090, and TZ1090 PDC.
 
 - Two pin control states related to power management are now
   handled in the device core: "sleep" and "idle", removing a lot
   of boilerplate code in drivers. We do not yet know if this is
   the final word for pin PM, but it already make things a lot
   easier to handle.
 
 - Handle sparse GPIO ranges passing a list of disparate pins, and
   utilize these in the new BayTrail (x86 Atom SoC) driver.
 
 - Make the sunxi (AllWinner) driver handle external interrupts.
 
 - Make it possible for pinctrl-single to handle the case where
   several pins are managed by a single register, and augment it to
   handle sleep modes.
 
 - Cleanups and improvements for the abx500 drivers.
 
 - Move Sirf pin control drivers to their own directory, support
   save/restore of context and add support for the SiRFatlas6 SoC.
 
 - PMU muxing for the Dove pinctrl driver.
 
 - Finalization and support for VF610 in the i.MX6 pinctrl driver.
 
 - Smoothen out various Exynos rough edges.
 
 - Generic cleanups of various kinds.
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Merge tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control changes from Linus Walleij:

 - A large slew of improvements of the Genric pin configuration support,
   and deployment in four different platforms: Rockchip, Super-H PFC,
   ABx500 and TZ1090.  Support BIAS_BUS_HOLD, get device tree parsing
   and debugfs support into shape.

 - We also have device tree support with generic naming conventions for
   the generic pin configuration.

 - Delete the unused and confusing direct pinconf API.  Now state
   transitions is *the* way to control pins and multiplexing.

 - New drivers for Rockchip, TZ1090, and TZ1090 PDC.

 - Two pin control states related to power management are now handled in
   the device core: "sleep" and "idle", removing a lot of boilerplate
   code in drivers.  We do not yet know if this is the final word for
   pin PM, but it already make things a lot easier to handle.

 - Handle sparse GPIO ranges passing a list of disparate pins, and
   utilize these in the new BayTrail (x86 Atom SoC) driver.

 - Make the sunxi (AllWinner) driver handle external interrupts.

 - Make it possible for pinctrl-single to handle the case where several
   pins are managed by a single register, and augment it to handle sleep
   modes.

 - Cleanups and improvements for the abx500 drivers.

 - Move Sirf pin control drivers to their own directory, support
   save/restore of context and add support for the SiRFatlas6 SoC.

 - PMU muxing for the Dove pinctrl driver.

 - Finalization and support for VF610 in the i.MX6 pinctrl driver.

 - Smoothen out various Exynos rough edges.

 - Generic cleanups of various kinds.

* tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
  pinctrl: vt8500: wmt: remove redundant dev_err call in wmt_pinctrl_probe()
  pinctrl: remove bindings for pinconf options needing more thought
  pinctrl: remove slew-rate parameter from tz1090
  pinctrl: set unit for debounce time pinconfig to usec
  pinctrl: more clarifications for generic pull configs
  pinctrl: rip out the direct pinconf API
  pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver
  pinctrl-tz1090: add TZ1090 pinctrl driver
  pinctrl: samsung: Staticize drvdata_list
  pinctrl: rockchip: Add missing irq_gc_unlock() call before return error
  pinctrl: abx500: rework error path
  pinctrl: abx500: suppress hardcoded value
  pinctrl: abx500: factorize code
  pinctrl: abx500: fix abx500_gpio_get()
  pinctrl: abx500: fix abx500_pin_config_set()
  pinctrl: abx500: Add device tree support
  sh-pfc: Guard DT parsing with #ifdef CONFIG_OF
  pinctrl: add Intel BayTrail GPIO/pinctrl support
  pinctrl: fix pinconf_ops::pin_config_dbg_parse_modify kerneldoc
  pinctrl: Staticize local symbols
  ...

Conflicts:
	drivers/net/ethernet/ti/davinci_mdio.c
	drivers/pinctrl/Makefile
2013-07-03 11:48:03 -07:00
Linus Torvalds a6e6d863cf regmap: Updates for v3.11
A small but useful set of regmap updates this time around:
 
 - An abstraction for bitfields within a register map contributed by
   Srinivas Kandagatla, allowing drivers to cope more easily when
   hardware designers randomly move things about (mainly when talking
   to things like system controllers).
 
 - Changes from Lars-Peter Clausen to allow the MMIO regmap to be used from
   hard IRQ context.
 
 - Small improvements to the cache infrastructure and performance,
   including a default cache sync operation so now all regmaps can sync
   easily.
 
 There's also a pinctrl driver making use of the new bitfield API, merged
 here for dependency reasons.  There will be a simple add/add conflict
 with the pinctrl tree as a result.
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Merge tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap

Pull regmap updates from Mark Brown:
 "A small but useful set of regmap updates this time around:

   - An abstraction for bitfields within a register map contributed by
     Srinivas Kandagatla, allowing drivers to cope more easily when
     hardware designers randomly move things about (mainly when talking
     to things like system controllers).

   - Changes from Lars-Peter Clausen to allow the MMIO regmap to be used
     from hard IRQ context.

   - Small improvements to the cache infrastructure and performance,
     including a default cache sync operation so now all regmaps can
     sync easily.

  There's also a pinctrl driver making use of the new bitfield API,
  merged here for dependency reasons.  There will be a simple add/add
  conflict with the pinctrl tree as a result."

* tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap:
  pinctrl: st: Remove unnecessary use of of_match_ptr macro
  pinctrl: st: fix return value check
  pinctrl: st: Add pinctrl and pinconf support.
  regmap: debugfs: Suppress cache for partial register files
  regmap: Add regmap_field APIs
  regmap: core: Cache all registers by default when cache is enabled
  regmap: Implemented default cache sync operation
  regmap: Make regmap-mmio usable from atomic contexts
  regmap: regcache: Fixup locking for custom lock callbacks
  regmap: debugfs: Fix return from regmap_debugfs_get_dump_start
  regmap: debugfs: Don't mark lockdep as broken due to debugfs write
  regmap: rbtree: Use range information to allocate nodes
  regmap: rbtree: Factor out node allocation
  regmap: Make regmap_check_range_table() a public API
  regmap: Add support for discarding parts of the register cache
2013-07-03 11:40:58 -07:00
Srinivas KANDAGATLA 701016c0cb pinctrl: st: Add pinctrl and pinconf support.
This patch add pinctrl support to ST SoCs.

About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.

Each multi-function pin is controlled, driven and routed through the PIO
multiplexing block. Each pin supports GPIO functionality (ALT0) and
multiple alternate functions(ALT1 - ALTx) that directly connect the pin
to different hardware blocks. When a pin is in GPIO mode, Output Enable
(OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
block. Otherwise the PIO multiplexing block configures these parameters
and retiming the signal.

About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
2013-06-25 16:22:19 +01:00
James Hogan b58f0273f0 pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver
Add a pin control driver for the TZ1090's low power pins via the
powerdown controller SOC_GPIO_CONTROL registers.

These pins have individually controlled pull-up, and group controlled
schmitt, slew-rate, drive-strength, and power-on-start (pos).

The pdc_gpio0 and pdc_gpio1 pins can also be muxed onto the
ir_mod_stable_out and ir_mod_power_out functions respectively. If no
function is set they remain in GPIO mode. These muxes can be overridden
by requesting them as GPIOs.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-24 17:21:38 +02:00
James Hogan d5025f9f53 pinctrl-tz1090: add TZ1090 pinctrl driver
Add a pin control driver for the main pins on the TZ1090 SoC. This
doesn't include the low-power pins as they're controlled separately via
the Powerdown Controller (PDC) registers.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-24 17:21:38 +02:00
Mathias Nyman a5d811bbf1 pinctrl: add Intel BayTrail GPIO/pinctrl support
Add support for gpio on Intel BayTrail platforms. BayTrail supports 3 banks
of gpios called SCORE, NCORE ans SUS with 102, 28 and 44 gpio pins.
Supports gpio interrupts and ACPI gpio events

Pins may be muxed to alternate function instead of gpio by firmware.
This driver does not touch the pin muxing and expect firmare
to set pin muxing and pullup/down properties properly.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-18 17:23:40 +02:00
Heiko Stübner d3e5116119 pinctrl: add pinctrl driver for Rockchip SoCs
This driver adds support the Cortex-A9 based SoCs from Rockchip,
so at least the RK2928, RK3066 (a and b) and RK3188.
Earlier Rockchip SoCs seem to use similar mechanics for gpio
handling so should be supportable with relative small changes.
Pull handling on the rk3188 is currently a stub, due to it being
a bit different to the earlier SoCs.

Pinmuxing as well as gpio (and interrupt-) handling tested on
a rk3066a based machine.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16 11:57:32 +02:00
Jingchang Lu 78bafc6618 pinctrl: add VF610 pinctrl driver
Adds Freescale Vybrid VF610 pin controller
driver to IMX common pinctrl driver framework.

Signed-off-by: Jingchang Lu <b35083@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16 11:56:51 +02:00
Barry Song 3370dc916c pinctrl:sirf:re-arch and add support for new SiRFatlas6 SoC
atlas6 is a SoC very similar with primaII, the register layput of
pinctrl is same, but the pads, groups and functions of atlas6 have
different layout with prima2, this patch
1. pull the definition of pads, groups and functions out of the
pinctrl-sirf driver,and put them into soc-specific files
2. add pads, groups and functions tables for atlas6
3. let pads, groups and functions tables become the config data of
   the related dt compatible node, so the pinctrl-sirf can support
   all SiRF SoCs with the config data as private data.

In this patch,we create a sirf dir, and let
the old drivers/pinctrl/pinctrl-sirf.c =
        drivers/pinctrl/sirf/pinctrl-prima2.c +
        drivers/pinctrl/sirf/pinctrl-sirf.c

drivers/pinctrl/sirf/pinctrl-atlas6.c is a newly created file for the
pin layout of atlas6.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16 11:56:49 +02:00
Shawn Guo 4fdf774fc9 pinctrl: enable build of pinctrl-imx6sl driver
The pinctrl-imx6sl is in place.  Enable the build of it.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16 11:56:49 +02:00
Heiko Stuebner af99a75074 pinctrl: Add pinctrl-s3c24xx driver
The s3c24xx pins follow a similar pattern as the other Samsung SoCs and
can therefore reuse the already introduced infrastructure.

The s3c24xx SoCs have one design oddity in that the first 4 external
interrupts do not reside in the eint pending register but in the main
interrupt controller instead. We solve this by forwarding the external
interrupt from the main controller into the irq domain of the pin bank.
The masking/acking of these interrupts is handled in the same way.

Furthermore the S3C2412/2413 SoCs contain another oddity in that they
keep the same 4 eints in the main interrupt controller and eintpend
register and requiring ack operations to happen in both. This is solved
by using different compatible properties for the wakeup eint node which
set a property accordingly.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-05-21 00:56:13 +09:00
Linus Torvalds 6fa52ed33b ARM: arm-soc driver changes for 3.10
This is a rather large set of patches for device drivers that for one
 reason or another the subsystem maintainer preferred to get merged
 through the arm-soc tree. There are both new drivers as well as
 existing drivers that are getting converted from platform-specific
 code into standalone drivers using the appropriate subsystem
 specific interfaces.
 
 In particular, we can now have pinctrl, clk, clksource and irqchip
 drivers in one file per driver, without the need to call into
 platform specific interface, or to get called from platform specific
 code, as long as all information about the hardware is provided
 through a device tree.
 
 Most of the drivers we touch this time are for clocksource. Since
 now most of them are part of drivers/clocksource, I expect that we
 won't have to touch these again from arm-soc and can let the
 clocksource maintainers take care of these in the future.
 
 Another larger part of this series is specific to the exynos platform,
 which is seeing some significant effort in upstreaming and
 modernization of its device drivers this time around, which
 unfortunately is also the cause for the churn and a lot of the
 merge conflicts.
 
 There is one new subsystem that gets merged as part of this series:
 the reset controller interface, which is a very simple interface
 for taking devices on the SoC out of reset or back into reset.
 Patches to use this interface on i.MX follow later in this merge
 window, and we are going to have other platforms (at least tegra
 and sirf) get converted in 3.11. This will let us get rid of
 platform specific callbacks in a number of platform independent
 device drivers.
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver changes from Olof Johansson:
 "This is a rather large set of patches for device drivers that for one
  reason or another the subsystem maintainer preferred to get merged
  through the arm-soc tree.  There are both new drivers as well as
  existing drivers that are getting converted from platform-specific
  code into standalone drivers using the appropriate subsystem specific
  interfaces.

  In particular, we can now have pinctrl, clk, clksource and irqchip
  drivers in one file per driver, without the need to call into platform
  specific interface, or to get called from platform specific code, as
  long as all information about the hardware is provided through a
  device tree.

  Most of the drivers we touch this time are for clocksource.  Since now
  most of them are part of drivers/clocksource, I expect that we won't
  have to touch these again from arm-soc and can let the clocksource
  maintainers take care of these in the future.

  Another larger part of this series is specific to the exynos platform,
  which is seeing some significant effort in upstreaming and
  modernization of its device drivers this time around, which
  unfortunately is also the cause for the churn and a lot of the merge
  conflicts.

  There is one new subsystem that gets merged as part of this series:
  the reset controller interface, which is a very simple interface for
  taking devices on the SoC out of reset or back into reset.  Patches to
  use this interface on i.MX follow later in this merge window, and we
  are going to have other platforms (at least tegra and sirf) get
  converted in 3.11.  This will let us get rid of platform specific
  callbacks in a number of platform independent device drivers."

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
  irqchip: s3c24xx: add missing __init annotations
  ARM: dts: Disable the RTC by default on exynos5
  clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
  ARM: exynos: restore mach/regs-clock.h for exynos5
  clocksource: exynos_mct: fix build error on non-DT
  pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
  irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
  reset: NULL deref on allocation failure
  reset: Add reset controller API
  dt: describe base reset signal binding
  ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
  ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
  ARM: EXYNOS: Enable PMUs for exynos4
  irqchip: exynos-combiner: Correct combined IRQs for exynos4
  irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
  ARM: EXYNOS: fix compilation error introduced due to common clock migration
  clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
  clk: exynos4: export clocks required for fimc-is
  clk: samsung: Fix compilation error
  clk: tegra: fix enum tegra114_clk to match binding
  ...
2013-05-04 12:31:18 -07:00
Linus Torvalds dfab34aa61 ARM: arm-soc device-tree updates for 3.10, part 1
Device-tree updates for 3.10. The bulk of the churn in this branch is due
 to i.MX moving from C-defined pin control over to device tree, which is
 a one-time conversion that will allow greater flexibility down the road.
 
 Besides that, there's PCI-e bindings for Marvell mvebu platforms and a
 handful of cleanups to tegra due to the new include file functionality
 of the device tree compiler.
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device-tree updates from Olof Johansson:
 "Part 1 of device-tree updates for 3.10.  The bulk of the churn in this
  branch is due to i.MX moving from C-defined pin control over to device
  tree, which is a one-time conversion that will allow greater
  flexibility down the road.

  Besides that, there's PCI-e bindings for Marvell mvebu platforms and a
  handful of cleanups to tegra due to the new include file functionality
  of the device tree compiler"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (113 commits)
  arm: mvebu: PCIe Device Tree informations for Armada XP GP
  arm: mvebu: PCIe Device Tree informations for Armada 370 DB
  arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
  arm: mvebu: PCIe Device Tree informations for Armada XP DB
  arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
  arm: mvebu: add PCIe Device Tree informations for Armada XP
  arm: mvebu: add PCIe Device Tree informations for Armada 370
  ARM: sunxi: unify osc24M_fixed and osc24M
  arm: vt8500: Add SDHC support to WM8505 DT
  ARM: dts: Add a 64 bits version of the skeleton device tree
  ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig
  ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board
  ARM: mvebu: Add support for NOR flash device on Armada XP-GP board
  ARM: mvebu: Add Device Bus support for Armada 370/XP SoC
  ARM: dts: imx6dl-wandboard: Add USB Host support
  ARM: dts: imx51 cpu node
  ARM: dts: Add missing imx27-phytec-phycore dtb target
  ARM: dts: Add NFC support for i.MX27 Phytec PCM038 module
  ARM: i.MX51: Add PATA support
  ARM: dts: Add initial support for Wandboard Dual-Lite
  ...
2013-05-02 09:28:03 -07:00
Shawn Guo 3f551d6aca pinctrl: add pinctrl driver for imx6dl
The imx6dl is a derivative of imx6q with very limited difference.  These
two SoCs are so compatible that they can be handled as one platform in
software.  That said, we will not have target SOC_IMX6DL but just
reusing SOC_IMX6Q.   That's why the pinctrl-imx6dl driver is added here
with symbol PINCTRL_IMX6Q controlling the build of it.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09 22:53:38 +08:00
Tomasz Figa 61dd726131 pinctrl: Add pinctrl-s3c64xx driver
This patch adds pinctrl-s3c64xx driver which implements pin control
interface for Samsung S3C64xx SoCs.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09 09:45:10 +02:00
Tony Prisk 170c6152ae pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500
This patch adds support for the GPIO/pinmux controller found on the VIA
VT8500 and Wondermedia WM8xxx-series SoCs.

Each pin within the controller is capable of operating as a GPIO or as
an alternate function. The pins are numbered according to their control
bank/bit so that if new pins are added, the existing numbering is maintained.

All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and
WM8850.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-04 18:00:02 +13:00
Haojian Zhuang 62194200e5 pinctrl: remove pxa pinctrl driver
pinctrl-pxa driver doesn't support well on DT mode. Now pinctrl-single
could support DT mode & pin configuration. Use pinctrl-single driver to
support MMP/PXA silicons instead.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-27 22:19:50 +01:00
Linus Torvalds 7ae1c76ee5 arm-soc: pin muxing for sh-mobile
This is another cleanup series, containing the move of the Renesas
 SH-Mobile pin controller code from arch/arm/mach-shmobile over to the
 generic pinctrl subsystem, changing it over to the common interfaces in
 the process.
 
 Based on agreement between Olof, Paul Mundt, Linus Walleij and Simon,
 we're merging this large branch of pinctrl conversion through arm-soc,
 even though it contains the corresponding conversions for arch/sh. Main
 reason for this is tight dependencies (that will now mostly be broken)
 between the arch/sh and mach-shmobile implementations.
 
 There will be more of this in 3.10 to do device-tree bindings, but this
 is the initial conversion.
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Merge tag 'sh-pinmux' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull sh-mobile pinctrl conversion from Arnd Bergmann:
 "This is another cleanup series, containing the move of the Renesas
  SH-Mobile pin controller code from arch/arm/mach-shmobile over to the
  generic pinctrl subsystem, changing it over to the common interfaces
  in the process.

  Based on agreement between Olof, Paul Mundt, Linus Walleij and Simon,
  we're merging this large branch of pinctrl conversion through arm-soc,
  even though it contains the corresponding conversions for arch/sh.
  Main reason for this is tight dependencies (that will now mostly be
  broken) between the arch/sh and mach-shmobile implementations.

  There will be more of this in 3.10 to do device-tree bindings, but
  this is the initial conversion."

* tag 'sh-pinmux' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (81 commits)
  sh-pfc: sh_pfc_probe() sizeof() fix
  sh-pfc: Move sh_pfc.h from include/linux/ to driver directory
  sh-pfc: Remove pinmux_info definition
  sh: Remove unused sh_pfc_register_info() function
  sh: shx3: pinmux: Use driver-provided pinmux info
  sh: sh7786: pinmux: Use driver-provided pinmux info
  sh: sh7785: pinmux: Use driver-provided pinmux info
  sh: sh7757: pinmux: Use driver-provided pinmux info
  sh: sh7734: pinmux: Use driver-provided pinmux info
  sh: sh7724: pinmux: Use driver-provided pinmux info
  sh: sh7723: pinmux: Use driver-provided pinmux info
  sh: sh7722: pinmux: Use driver-provided pinmux info
  sh: sh7720: pinmux: Use driver-provided pinmux info
  sh: sh7269: pinmux: Use driver-provided pinmux info
  sh: sh7264: pinmux: Use driver-provided pinmux info
  sh: sh7203: pinmux: Use driver-provided pinmux info
  ARM: shmobile: sh73a0: Use driver-provided pinmux info
  ARM: shmobile: sh7372: Use driver-provided pinmux info
  ARM: shmobile: r8a7779: Use driver-provided pinmux info
  ARM: shmobile: r8a7740: Use driver-provided pinmux info
  ...
2013-02-21 15:00:16 -08:00
Linus Walleij 7ac63ac61d Merge branch 'allwinner-sunxi' into devel 2013-02-08 14:26:49 +01:00
Patrice Chotard a8f96e4178 pinctrl/abx500: add AB8540 sub-driver
Add AB8540 sub driver to the ABx500 family, pins, pin groups and
gpio range.

As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.

Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-05 13:54:21 +01:00
Patrice Chotard 09dbec3f74 pinctrl/abx500: add AB9540 sub-driver
Add AB9540 sub driver to the ABx500 family, pins, pin groups and
gpio range.

As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.

Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-05 13:54:20 +01:00
Patrice Chotard 1aa2d8d405 pinctrl/abx500: add AB8505 sub-driver
Add AB8505 sub driver to the ABx5x family.

As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.

Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-05 13:54:19 +01:00
Patrice Chotard 3c93799378 pinctrl/abx500: add AB8500 sub-driver
This adds a subdriver for the AB8500 pinctrl portions.
As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.

Acked-by: Olof Johansson <olof@lixom.net>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-30 20:42:40 +01:00
Patrice Chotard 0493e64930 pinctrl: add abx500 pinctrl driver core
This adds the AB8500 core driver, which will be utilized by
the follow-on drivers for different ABx500 variants.
Sselect the driver from the DBX500_SOC, as this chip is
powering and clocking that SoC.

Cc: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-30 20:42:14 +01:00
Laurent Pinchart 6e54d8d252 sh-pfc: Move driver from drivers/sh/ to drivers/pinctrl/
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-25 09:24:25 +09:00
Maxime Ripard 0e37f88d9a ARM: sunxi: Add pinctrl driver for Allwinner SoCs
The Allwinner SoCs have an IP module that handle both the muxing and the
GPIOs.

This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC used on the board.

This driver only implements the pinctrl part, the gpio part will come
eventually.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22 13:51:15 +01:00
Kukjin Kim 7452b64d01 pinctrl: exynos: change PINCTRL_EXYNOS option
Since pinctrl-exynos can support exynos4 and exynos5 so changed
the option name to PINCTRL_EXYNOS for more clarity.

Cc: Thomas Abraham <Thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18 20:35:06 +01:00
Pritesh Raithatha b6ae7a2653 pinctrl: tegra114: add pinctrl driver for NVIDIA's Tegra114 SoC
This adds a driver for the Tegra114 pinmux, and required
parameterization data for Tegra114.

The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.

This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra114-pinmux".

Originally written by Pritesh.
ldewangan:
	- cleanup the patches,
	- remove non-require tables.
	- Use module_platform_driver() for driver registartion.

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18 16:14:54 +01:00
Linus Torvalds d027db132b ARM: arm-soc: SoC updates for 3.8
This contains the bulk of new SoC development for this merge window.
 
 Two new platforms have been added, the sunxi platforms (Allwinner A1x
 SoCs) by Maxime Ripard, and a generic Broadcom platform for a new
 series of ARMv7 platforms from them, where the hope is that we can
 keep the platform code generic enough to have them all share one mach
 directory. The new Broadcom platform is contributed by Christian Daudt.
 
 Highbank has grown support for Calxeda's next generation of hardware,
 ECX-2000.
 
 clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also
 taken on maintainership of the platform.
 
 Beyond this there has been a bunch of work from a number of people on
 converting more platforms to IRQ domains, pinctrl conversion, cleanup
 and general feature enablement across most of the active platforms.
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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC updates from Olof Johansson:
 "This contains the bulk of new SoC development for this merge window.

  Two new platforms have been added, the sunxi platforms (Allwinner A1x
  SoCs) by Maxime Ripard, and a generic Broadcom platform for a new
  series of ARMv7 platforms from them, where the hope is that we can
  keep the platform code generic enough to have them all share one mach
  directory.  The new Broadcom platform is contributed by Christian
  Daudt.

  Highbank has grown support for Calxeda's next generation of hardware,
  ECX-2000.

  clps711x has seen a lot of cleanup from Alexander Shiyan, and he's
  also taken on maintainership of the platform.

  Beyond this there has been a bunch of work from a number of people on
  converting more platforms to IRQ domains, pinctrl conversion, cleanup
  and general feature enablement across most of the active platforms."

Fix up trivial conflicts as per Olof.

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits)
  mfd: vexpress-sysreg: Remove LEDs code
  irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids
  clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids
  irq: versatile: delete dangling variable
  ARM: sunxi: add missing include for mdelay()
  ARM: EXYNOS: Avoid early use of of_machine_is_compatible()
  ARM: dts: add node for PL330 MDMA1 controller for exynos4
  ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
  ARM: EXYNOS: add UART3 to DEBUG_LL ports
  ARM: S3C24XX: Add clkdev entry for camif-upll clock
  ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers
  ARM: sunxi: Add missing sun4i.dtsi file
  pinctrl: samsung: Do not initialise statics to 0
  ARM i.MX6: remove gate_mask from pllv3
  ARM i.MX6: Fix ethernet PLL clocks
  ARM i.MX6: rename PLLs according to datasheet
  ARM i.MX6: Add pwm support
  ARM i.MX51: Add pwm support
  ARM i.MX53: Add pwm support
  ARM: mx5: Replace clk_register_clkdev with clock DT lookup
  ...
2012-12-12 12:05:15 -08:00
Thomas Abraham f0b9a7e521 pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC
Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller
module in EXYNOS5440 is different from the pin controller found on other
Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is
independent of the Samsung pinctrl framework.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-11-22 13:42:58 +09:00
Linus Walleij e59d969f44 Merge branch 'at91' into devel 2012-11-11 19:12:33 +01:00
Thomas Petazzoni 06763c741b pinctrl: mvebu: move to its own directory
Like the spear platform, the mvebu platform has multiple files: one
core file, and then one file per SoC family. More files will be added
later, as support for mach-orion5x and mach-mv78xx0 SoCs is added to
pinctrl-mvebu. For those reasons, having a separate subdirectory,
drivers/pinctrl/mvebu/ makes sense, and it had already been suggested
by Linus Wallej when the driver was originally submitted.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-11 19:05:57 +01:00
Jean-Christophe PLAGNIOL-VILLARD 6732ae5cb4 ARM: at91: add pinctrl support
This is also include the gpio controller as the IP share both.
Each soc will have to describe the SoC limitation and pin configuration via
DT.

This will allow to do not need to touch the C code when adding new SoC if the
IP version is supported.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2012-10-13 09:21:43 +08:00
Linus Torvalds de390bba79 Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS update from Ralf Baechle:
 "This is the MIPS update for 3.7.

  A fair chunk of them are platform updates to the Cavium Octeon SOC
  (which involves machine generated header files of considerable size),
  Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx
  platforms.

  Support for the commercial MIPS simulator MIPSsim has been removed as
  MIPS Technologies is shifting away from this product and Qemu is
  offering various more powerful platforms.  The generic MIPS code can
  now also probe for no-execute / write-only TLB features implemented
  without the full SmartMIPS extension as permitted by the latest MIPS
  processor architecture.  Lots of small changes to generic code."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits)
  MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
  MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x
  MIPS: BCM63XX: Properly handle mac address octet overflow
  MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.
  MIPS: Replace `-' in defconfig filename wth `_' for consistency.
  MIPS: Wire kcmp syscall.
  MIPS: MIPSsim: Remove the MIPSsim platform.
  MIPS: NOTIFY_RESUME is not needed in TIF masks
  MIPS: Merge the identical "return from syscall" per-ABI code
  MIPS: Unobfuscate _TIF..._MASK
  MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).
  MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
  MIPS: Add base architecture support for RI and XI.
  MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
  MIPS: uasm: Add INS and EXT instructions.
  MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
  MIPS: Make VPE count to be one-based.
  MIPS: Add new end of interrupt functionality for GIC.
  MIPS: Add EIC support for GIC.
  MIPS: Code clean-ups for the GIC.
  ...
2012-10-09 16:08:04 +09:00
Linus Torvalds 5e090ed7af ARM: soc: late platform updates
This branch contains updates to OMAP and Marvell platforms (kirkwood,
 dove, mvebu) that came in after we had done the big multiplatform merges,
 so they were kept separate from the rest, and not separated into the
 traditional topics of cleanup/driver/platform features.
 
 For OMAP, the updates are:
 - Runtime PM conversions for the GPMC and RNG IP blocks
 - Preparation patches for the OMAP common clock framework conversion
 - clkdev alias additions required by other drivers
 - Performance Monitoring Unit (PMU) support for OMAP2, 3, and non-4430 OMAP4
 - OMAP hwmod code and data improvements
 - Preparation patches for the IOMMU runtime PM conversion
 - Preparation patches for OMAP4 full-chip retention support
 
 For Kirkwood/Dove/mvebu:
 
 - New driver for "address decoder controller" for mvebu, which
   is a piece of hardware that configures addressable devices and
   peripherals. First user is the boot rom aperture on armada XP since
   it is needed for SMP support.
 - New device tree bindings for peripherals such as gpio-fan, iconnect
   nand, mv_cesa and the above address decoder controller.
 - Some defconfig updates, mostly to enable new DT boards and a few drivers.
 - New drivers using the pincontrol subsystem for dove, kirkwood and mvebu
 - New clean gpio driver for mvebu
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Merge tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull late ARM soc platform updates from Olof Johansson:
 "This branch contains updates to OMAP and Marvell platforms (kirkwood,
  dove, mvebu) that came in after we had done the big multiplatform
  merges, so they were kept separate from the rest, and not separated
  into the traditional topics of cleanup/driver/platform features.

  For OMAP, the updates are:
   - Runtime PM conversions for the GPMC and RNG IP blocks
   - Preparation patches for the OMAP common clock framework conversion
   - clkdev alias additions required by other drivers
   - Performance Monitoring Unit (PMU) support for OMAP2, 3, and
     non-4430 OMAP4
   - OMAP hwmod code and data improvements
   - Preparation patches for the IOMMU runtime PM conversion
   - Preparation patches for OMAP4 full-chip retention support

  For Kirkwood/Dove/mvebu:
   - New driver for "address decoder controller" for mvebu, which is a
     piece of hardware that configures addressable devices and
     peripherals.  First user is the boot rom aperture on armada XP
     since it is needed for SMP support.
   - New device tree bindings for peripherals such as gpio-fan, iconnect
     nand, mv_cesa and the above address decoder controller.
   - Some defconfig updates, mostly to enable new DT boards and a few
     drivers.
   - New drivers using the pincontrol subsystem for dove, kirkwood and
     mvebu
   - New clean gpio driver for mvebu"

* tag 'soc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (98 commits)
  ARM: mvebu: fix build breaks from multi-platform conversion
  ARM: OMAP4460/4470: PMU: Enable PMU for OMAP4460/70
  ARM: OMAP2+: PMU: Add runtime PM support
  ARM: OMAP4430: PMU: prepare to create PMU device via HWMOD
  ARM: OMAP2+: PMU: Convert OMAP2/3 devices to use HWMOD
  ARM: OMAP3: hwmod data: Add debugss HWMOD data
  ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems
  ARM: OMAP: Add a timer attribute for timers that can interrupt the DSP
  hwrng: OMAP: remove SoC restrictions from driver registration
  ARM: OMAP: split OMAP1, OMAP2+ RNG device registration
  hwrng: OMAP: convert to use runtime PM
  hwrng: OMAP: store per-device data in per-device variables, not file statics
  ARM: OMAP2xxx: hwmod/CM: add RNG integration data
  ARM: OMAP2+: gpmc: minimal driver support
  ARM: OMAP2+: gpmc: Adapt to HWMOD
  ARM: OMAP2/3: hwmod data: add gpmc
  ARM: OMAP4: hwmod data: add mmu hwmod for ipu and dsp
  ARM: OMAP3: hwmod data: add mmu data for iva and isp
  ARM: OMAP: iommu: fix including iommu.h without IOMMU_API selected
  ARM: OMAP4: hwmod data: add missing HWMOD_NO_IDLEST flags to some PRCM IP blocks
  ...
2012-10-07 20:55:16 +09:00
Linus Torvalds 06fe918e9f These are the bulk pinctrl changes for kernel v3.7:
- Add subdrivers for the DB8540 and NHK8815 Nomadik-type ASICs,
   provide platform config for the Nomadik.
 - Add a driver for the i.MX35.
 - Add a driver for the BCM2835, an advanced GPIO expander.
 - Various fixes and clean-ups and minor improvements for the core,
   Nomadik, pinctr-single, sirf drivers.
 - Some platform config for the ux500.
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Merge tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pinctrl changes from Linus Walleij:
 "Some of this stuff is hitting arch/arm/* and have been ACKed by the
  ARM SoC folks, or it's device tree bindings pertaining to the specific
  driver.

  These are the bulk pinctrl changes for kernel v3.7:
   - Add subdrivers for the DB8540 and NHK8815 Nomadik-type ASICs,
     provide platform config for the Nomadik.
   - Add a driver for the i.MX35.
   - Add a driver for the BCM2835, an advanced GPIO expander.
   - Various fixes and clean-ups and minor improvements for the core,
     Nomadik, pinctr-single, sirf drivers.
   - Some platform config for the ux500."

* tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (27 commits)
  pinctrl: add bcm2835 driver
  pinctrl: clarify idle vs sleep states
  pinctrl/nomadik: use irq_find_mapping()
  pinctrl: sirf: add lost chained_irq_enter and exit in sirfsoc_gpio_handle_irq
  pinctrl: sirf: initialize the irq_chip pointer of pinctrl_gpio_range
  pinctrl: sirf: fix spinlock deadlock in sirfsoc_gpio_set_input
  pinctrl: sirf: add missing pins to pinctrl list
  pinctrl: sirf: fix a typo in sirfsoc_gpio_probe
  pinctrl: pinctrl-single: add debugfs pin h/w state info
  ARM: ux500: 8500: update I2C sleep states pinctrl
  pinctrl: Fix potential memory leak in pinctrl_register_one_pin()
  ARM: ux500: tidy up pin sleep modes
  ARM: ux500: fix spi2 pin group
  pinctrl: imx: remove duplicated const
  pinctrl: document semantics vs GPIO
  ARM: ux500: 8500: use hsit_a_2 group for HSI
  pinctrl: use kasprintf() in pinmux_request_gpio()
  pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux
  pinctrl/nomadik : add MC1_a_2 pin MC1 function group list
  pinctrl: pinctrl-single: Make sure we do not change bits outside of mask
  ...
2012-10-02 16:20:20 -07:00
Simon Arlott e1b2dc70cd pinctrl: add bcm2835 driver
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
controller, and pinmux/control device.

Original driver by Simon Arlott.
Rewrite including GPIO chip device by Chris Boot.

Upstreaming changes by Stephen Warren:
* Wrote DT binding documentation.
* Changed brcm,function to an integer to more directly match the
  datasheet, and to match brcm,pins being an integer.
* Implemented pull-up/down pin config.
* Removed read-only DT property and related code. The restriction this
  implemented are driven by the board, not the GPIO HW block, so don't
  really make sense of a HW block binding, were in general incomplete
  (since they could only know about the few pins hard-coded into the
  Raspberry Pi B board design and not the uncommitted GPIOS), and are
  better represented simply by not writing incorrect data into pin
  configuration nodes.
* Don't set GPIO_IN function select in gpio_request_enable() to avoid
  glitches; defer this to gpio_set_direction(). Consequently, removed
  empty bcm2835_pmx_gpio_request_enable().
* Simplified enabled_irq_map[]; make it explicitly 1 entry per bank.
* Lifted use of enabled_irq_map[] outside the per-interrupt loop in
  IRQ handler, thus fixing an issue where the code was indexing into
  enabled_irq_map[] by intra-bank GPIO ID, not global GPIO ID.
* Removed locking in IRQ handler, since all other code uses
  spin_lock_irqsave() and so guarantees it doesn't run concurrently
  with the handler.
* Moved duplicated BUILD_BUG_ON()s into probe(). Also check size of
  bcm2835_gpio_pins[].
* Remove range-checking from bcm2835_pctl_get_groups_count() since we've
  decided to trust the pinctrl core.
* Made bcm2835_pmx_gpio_disable_free() call bcm2835_pinctrl_fsel_set()
  directly for simplicity.
* Fixed body of dt_free_map() to match latest dt_node_to_map().
* Removed GPIO ownership check from bcm2835_pmx_enable() since the pinctrl
  core owns doing this.
* Made irq_chip and pinctrl_gpio_range .name == MODULE_NAME so it's more
  descriptive.
* Simplified remove(); removed call to non-existent
  pinctrl_remove_gpio_range(), remove early return on error.
* Don't force gpiochip's base to 0. Set gpio_range.base to gpiochip's
  base GPIO number.
* Error-handling cleanups in probe().
* Switched to module_platform_driver() rather than open-coding.
* Made pin, group, and function names lower-case.
* s/broadcom/brcm/ in DT property names.
* s/2708/2835/.
* Fixed a couple minor checkpatch warnings, and other minor cleanup.

Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-01 08:05:22 +02:00
Thomas Petazzoni 463e270f76 pinctrl: mvebu: add pinctrl driver for Armada XP
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22 14:50:20 +00:00
Thomas Petazzoni 5f597bb2be pinctrl: mvebu: add pinctrl driver for Armada 370
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22 14:50:19 +00:00
Sebastian Hesselbarth 9d4b1632bc pinctrl: mvebu: kirkwood pinctrl driver
This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22 14:50:17 +00:00
Sebastian Hesselbarth c9f95cedfe pinctrl: mvebu: dove pinctrl driver
This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2012-09-22 14:50:16 +00:00
Sebastian Hesselbarth 7e8d941567 pinctrl: mvebu: pinctrl driver core
This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Conflicts:

	arch/arm/Kconfig
2012-09-22 14:50:14 +00:00
John Crispin e316cb2b16 OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
of up to 32 pins.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
2012-09-13 10:30:58 +02:00
John Crispin 3f8c50c9b1 OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support
Implement support for pinctrl on lantiq/xway socs. The IO core found on these
socs has the registers for pinctrl, pinconf and gpio mixed up in the same
register range. As the gpio_chip handling is only a few lines, the driver also
implements the gpio functionality. This obseletes the old gpio driver that was
located in the arch/ folder.

Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
2012-09-13 10:30:49 +02:00
Thomas Abraham 43b169db18 pinctrl: add exynos4210 specific extensions for samsung pinctrl driver
Add information about the Exynos4210 pin banks and driver data which is
used by the Samsung pinctrl driver. In addition to this, the support for
external gpio and wakeup interrupt support is included and hooked up with
the Samsung pinctrl driver.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 06:07:19 +09:00
Thomas Abraham 30574f0db1 pinctrl: add samsung pinctrl and gpiolib driver
Add a new device tree enabled pinctrl and gpiolib driver for Samsung
SoC's. This driver provides a common and extensible framework for all
Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
driver supports only device tree based instantiation and hence can be
used only on those Samsung platforms that have device tree enabled.

This driver is split into two parts: the pinctrl interface and the gpiolib
interface. The pinctrl interface registers pinctrl devices with the pinctrl
subsystem and gpiolib interface registers gpio chips with the gpiolib
subsystem. The information about the pins, pin groups, pin functions and
gpio chips, which are SoC specific, are parsed from device tree node.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2012-09-07 06:07:19 +09:00
Uwe Kleine-König b9aa8f13ea pinctrl: pinctrl-imx: add imx35 pinctrl driver
This is mostly cut'n'paste from the imx51 pinctrl driver.
The data was generated using sed and awk on
arch/arm/plat-mxc/include/mach/iomux-mx35.h.

Changes since (implicit) v1
 - remove references to file names in binding documentation
 - remove sed commands from comments in driver
 - add explicit numbers for pins and functions

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-03 13:21:37 +02:00
Linus Walleij f79c5ed9da pinctrl/nomadik: add STn8815 ASIC support
This adds support for the STN8815 ASIC for the Nomadik pin
controller.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-03 13:21:37 +02:00
Patrice Chotard 45a1b53195 pinctrl/nomadik: add ASIC DB8450 pinctrl driver
This implements a subdriver for the DB8540 ASIC for the
Nomadik pin controller.

Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-03 13:21:37 +02:00
Tony Lindgren 8b8b091bf0 pinctrl: Add one-register-per-pin type device tree based pinctrl driver
Add one-register-per-pin type device tree based pinctrl driver.

This driver has been tested on omap2+ series of processors,
where there is either an 8 or 16-bit padconf register for each pin.
Support for other similar pinmux controllers can be added.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-07-14 22:33:08 +02:00
Linus Torvalds 813a95e5b4 arm-soc: soc-specific pinctrl changes
With this, five platforms are moving to the relatively new pinctrl
 subsystem for their pin management, replacing the older soc specific
 in-kernel interfaces with common code.
 
 There is quite a bit of net addition of code for each platform being
 added to the pinctrl subsystem. but the payback comes later when adding
 new boards can be done by only providing new device trees instead.
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Merge tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm soc-specific pinctrl changes from Olof Johansson:
 "With this, five platforms are moving to the relatively new pinctrl
  subsystem for their pin management, replacing the older soc specific
  in-kernel interfaces with common code.

  There is quite a bit of net addition of code for each platform being
  added to the pinctrl subsystem.  But the payback comes later when
  adding new boards can be done by only providing new device trees
  instead."

Fix up trivial conflicts in arch/arm/mach-ux500/{Makefile,board-mop500.c}

* tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (61 commits)
  mtd: nand: gpmi: fix compile error caused by pinctrl call
  ARM: PRIMA2: select PINCTRL and PINCTRL_SIRF in Kconfig
  ARM: nomadik: enable PINCTRL_NOMADIK where needed
  ARM: mxs: enable pinctrl support
  video: mxsfb: adopt pinctrl support
  ASoC: mxs-saif: adopt pinctrl support
  i2c: mxs: adopt pinctrl support
  mtd: nand: gpmi: adopt pinctrl support
  mmc: mxs-mmc: adopt pinctrl support
  serial: mxs-auart: adopt pinctrl support
  serial: amba-pl011: adopt pinctrl support
  spi/imx: adopt pinctrl support
  i2c: imx: adopt pinctrl support
  can: flexcan: adopt pinctrl support
  net: fec: adopt pinctrl support
  ARM: ux500: switch MSP to using pinctrl for pins
  ARM: ux500: alter MSP registration to return a device pointer
  ARM: ux500: switch to using pinctrl for uart0
  ARM: ux500: delete custom pin control system
  ARM: ux500: switch over to Nomadik pinctrl driver
  ...
2012-05-22 09:39:42 -07:00
Dong Aisheng 4f6a16bf01 pinctrl: pinctrl-imx: add imx51 pinctrl driver
ChangeLog v1->v2:
* change PIN_FUNC_ID base in binding doc to 0 from 1.

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-20 21:00:41 +02:00
Dong Aisheng 93fbd3c050 pinctrl: pinctrl-imx: add imx53 pinctrl driver
ChangeLog v1->v2:
* change PIN_FUNC_ID base in binding doc to 0 from 1.

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-20 21:00:18 +02:00
Olof Johansson 7af07ad902 ux500 GPIO and pinctrl changes for kernel 3.5
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Merge tag 'ux500-gpio-pins-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/pinctrl

ux500 GPIO and pinctrl changes for kernel 3.5

* tag 'ux500-gpio-pins-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
  ARM: ux500: switch MSP to using pinctrl for pins
  ARM: ux500: alter MSP registration to return a device pointer
  ARM: ux500: switch to using pinctrl for uart0
  ARM: ux500: delete custom pin control system
  ARM: ux500: switch over to Nomadik pinctrl driver
  pinctrl: add sleep state definition
  pinctrl/nomadik: implement pin configuration
  pinctrl/nomadik: implement pin multiplexing
  pinctrl/nomadik: reuse GPIO debug function for pins
  pinctrl/nomadik: break out single GPIO debug function
  pinctrl/nomadik: basic Nomadik pinctrl interface
  pinctrl/nomadik: !CONFIG_OF build error
  gpio: move the Nomadik GPIO driver to pinctrl

Context conflicts resolved in drivers/pinctrl/Kconfig and
drivers/pinctrl/Makefile.

Signed-off-by: Olof Johansson <olof@lixom.net>
2012-05-12 19:57:34 -07:00
Arnd Bergmann 366695ff70 Merge branches 'depends/pinctrl/devel' and 'depends/rmk/clkdev' into spear/pinctrl
The spear/pinctrl branch has hard dependencies on both the
pinctrl branch and the clkdev branch. We merge those here
to fix it up without having to rebase a branch that has
been pulled into other stable branches already.

Conflicts:
	Documentation/driver-model/devres.txt

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-05-12 20:38:42 +02:00
Linus Walleij e98ea774c8 pinctrl/nomadik: basic Nomadik pinctrl interface
This adds a scratch pin control interface to the Nomadik pinctrl
driver, and defines the pins and groups in the DB8500 ASIC. We
define GPIO ranges to cover the pins exposed. The DB8500 has
more pins than this but we restrict the driver to the pins that
can be controlled from the combined GPIO and pin control hardware
to begin with.

ChangeLog v1->v2:
- Base on the latest pinctrl development from
  pinctrl-mergebase-20120418 so we can get rid of legacy
  group count mechanism. Also drop the range checks for group
  index, this is handled by the core now.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-11 11:14:14 +02:00
Linus Walleij 1ae4e59279 gpio: move the Nomadik GPIO driver to pinctrl
I'm moving this driver over to the pinctrl subsystem to convert
the custom pin mux/config scheme over to use pinctrl.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-11 10:33:43 +02:00
Shawn Guo 17723111e6 pinctrl: add pinctrl-mxs support
Add pinctrl support for Freescale MXS SoCs, i.MX23 and i.MX28.
The driver supports device tree probe only.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-02 01:18:27 +02:00
Dong Aisheng d8fe35727a pinctrl: pinctrl-imx: add imx6q pinctrl driver
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-02 01:14:40 +02:00
Dong Aisheng ae75ff8145 pinctrl: pinctrl-imx: add imx pinctrl core driver
The driver has mux and config support while the gpio is still
not supported.
For select input setting, the driver will handle it internally
and do not need user to take care of it.

The pinctrl-imx core driver will parse the dts file and dynamically
create the pinmux functions and groups.

Each IMX SoC pinctrl driver should register pins with a pin register map
including mux register and config register and select input map to core
for proper operations.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-02 01:14:40 +02:00
Viresh Kumar deda8287e1 pinctrl: Add SPEAr pinctrl drivers
This adds pinctrl driver for SPEAr platform. It also updates MAINTAINERS file
for SPEAr pinctrl drivers.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
2012-04-22 22:49:23 +02:00
Stephen Warren eafeb7a44a pinctrl: fix build when CONFIG_OF && !CONFIG_PINCTRL
pinctrl/devicetree.c won't compile when !CONFIG_PINCTRL, since the
pinctrl headers don't declare some types when !PINCTRL. Make sure
pinctrl/Makefile only attempts to compile devicetree.c when OF &&
PINCTRL.

Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18 13:53:10 +02:00
Stephen Warren 57291ce295 pinctrl: core device tree mapping table parsing support
During pinctrl_get(), if the client device has a device tree node, look
for the common pinctrl properties there. If found, parse the referenced
device tree nodes, with the help of the pinctrl drivers, and generate
mapping table entries from them.

During pinctrl_put(), free any results of device tree parsing.

Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18 13:53:10 +02:00
Linus Walleij 394349f778 pinctrl: introduce generic pin config
This is a split-off from the earlier patch set which adds generic
pin configuration for the pin controllers that want it. Since
we may have a system with mixed generic and custom pin controllers,
we pass a boolean in the pin controller ops vtable to indicate
if it is generic.

ChangeLog v1->v5:
- Follow parent patch versioning number system.
- Document the semantic meaning of return values from pin config
  get functions, so we can iterate over pins and check their
  properties from debugfs as part of the generic config code.
- Use proper cast functions in the generic debugfs pin config
  file.
- Expand generic config to optionally cover groups too.
ChangeLog v5->v6:
- Update to match underlying changes.
ChangeLog v6->v7:
- Drop DRIVE_OFF parameter, use bias high impedance for this
- Delete argument for drive modes push-pull, od and os. These
  are now just state transitions.
- Delete slew rate rising/falling due to discussions on on
  proper semantics
- Drop config wakeup, struct irq_chip does this for now, add
  back if need be.
- Set PIN_CONFIG_END to 0x7fff making room for custom config
  parameters from 0x8000 and up.
- Prefix accessor functions with pinconf_
2012-03-12 22:49:02 +01:00
Linus Walleij a6c3b33f02 Merge branch 'pinctrl-tegra-for-next-diet' into for-next 2012-03-06 23:30:15 +01:00
Stephen Warren 971dac7123 pinctrl: add a driver for NVIDIA Tegra
This adds a driver for the Tegra pinmux, and required parameterization
data for Tegra20 and Tegra30.

The driver is initially added with driver name and device tree compatible
value that won't cause this driver to be used. A later change will switch
the pinctrl driver to use the correct values, switch the old pinmux
driver to be disabled, and update all code that uses the old pinmux APIs
to use the new pinctrl APIs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
[squashed "fix case of Tegra30's foo_groups[] arrays"]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-03-06 10:51:46 +01:00
Haojian Zhuang f4e6698329 pinctrl: enable pinmux for mmp series
Support PXA168/PXA910/MMP2 pinmux. Now only support function switch.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
[Rebase and fix some whitespace issues]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-02-01 19:42:35 +01:00
Linus Walleij 3bece55aa5 pinctrl: rename U300 and SIRF pin controllers
For stringent order, rename the pinmux-* pin controllers to
pinctrl-* and also rename the Kconfig symbols and in-kernel
users.

Cc: Rongjun Ying <Rongjun.Ying@csr.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-01-03 09:10:08 +01:00
Linus Walleij ae6b4d8588 pinctrl: add a pin config interface
This add per-pin and per-group pin config interfaces for biasing,
driving and other such electronic properties. The details of passed
configurations are passed in an opaque unsigned long which may be
dereferences to integer types, structs or lists on either side
of the configuration interface.

ChangeLog v1->v2:
- Clear split of terminology: we now have pin controllers, and
  those may support two interfaces using vtables: pin
  multiplexing and pin configuration.
- Break out pin configuration to its own C file, controllers may
  implement only config without mux, and vice versa, so keep each
  sub-functionality of pin controllers separate. Introduce
  CONFIG_PINCONF in Kconfig.
- Implement some core logic around pin configuration in the
  pinconf.c file.
- Remove UNKNOWN config states, these were just surplus baggage.
- Remove FLOAT config state - HIGH_IMPEDANCE should be enough for
  everyone.
- PIN_CONFIG_POWER_SOURCE added to handle switching the power
  supply for the pin logic between different sources
- Explicit DISABLE config enums to turn schmitt-trigger,
  wakeup etc OFF.
- Update documentation to reflect all the recent reasoning.
ChangeLog v2->v3:
- Twist API around to pass around arrays of config tuples instead
  of (param, value) pairs everywhere.
- Explicit drive strength semantics for push/pull and similar
  drive modes, this shall be the number of drive stages vs
  nominal load impedance, which should match the actual
  electronics used in push/pull CMOS or TTY totempoles.
- Drop load capacitance configuration - I probably don't know
  what I'm doing here so leave it out.
- Drop PIN_CONFIG_INPUT_SCHMITT_OFF, instead the argument zero to
  PIN_CONFIG_INPUT_SCHMITT turns schmitt trigger off.
- Drop PIN_CONFIG_NORMAL_POWER_MODE and have a well defined
  argument to PIN_CONFIG_LOW_POWER_MODE to get out of it instead.
- Drop PIN_CONFIG_WAKEUP_ENABLE/DISABLE and just use
  PIN_CONFIG_WAKEUP with defined value zero to turn wakeup off.
- Add PIN_CONFIG_INPUT_DEBOUNCE for configuring debounce time
  on input lines.
- Fix a bug when we tried to configure pins for pin controllers
  without pinconf support.
- Initialized debugfs properly so it works.
- Initialize the mutex properly and lock around config tampering
  sections.
- Check the return value from get_initial_config() properly.
ChangeLog v3->v4:
- Export the pin_config_get(), pin_config_set() and
  pin_config_group() functions.
- Drop the entire concept of just getting initial config and
  keeping track of pin states internally, instead ask the pins
  what state they are in. Previous idea was plain wrong, if the
  device cannot keep track of its state, the driver should do
  it.
- Drop the generic configuration layout, it seems this impose
  too much restriction on some pin controllers, so let them do
  things the way they want and split off support for generic
  config as an optional add-on.
ChangeLog v4->v5:
- Introduce two symmetric driver calls for group configuration,
  .pin_config_group_[get|set] and corresponding external calls.
- Remove generic semantic meanings of return values from config
  calls, these belong in the generic config patch. Just pass the
  return value through instead.
- Add a debugfs entry "pinconf-groups" to read status from group
  configuration only, also slam in a per-group debug callback in
  the pinconf_ops so custom drivers can display something
  meaningful for their pins.
- Fix some dangling newline.
- Drop dangling #else clause.
- Update documentation to match the above.
ChangeLog v5->v6:
- Change to using a pin name as parameter for the
  [get|set]_config() functions, as suggested by Stephen Warren.
  This is more natural as names will be what a developer has
  access to in written documentation etc.
ChangeLog v6->v7:
- Refactor out by-pin and by-name get/set functions, only expose
  the by-name functions externally, expose the by-pin functions
  internally.
- Show supported pin control functionality in the debugfs
  pinctrl-devices file.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-01-03 09:10:04 +01:00
Linus Walleij ca402d37dc pinctrl: move the U300 GPIO driver to pinctrl
This driver will be converted to a dual GPIO + pinctrl driver
since it supports biasing and driving control options. Hopefully
it can serve as an example.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-01-03 09:10:03 +01:00
Uwe Kleine-König 3838d32759 pinctrl: make the "Debug PINCTRL calls" entry actually do something
DEBUG_PINCTRL wasn't used at all and DEBUG_PINMUX doesn't exist.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-12-08 16:17:47 +01:00
Rongjun Ying 393daa814f pinctrl: add a driver for the CSR SiRFprimaII pinmux
This creates a pin controller driver for the SiRFprinaII
pin mux portions.

Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
[Fixup for changed function names and semantics in the v10 patch]
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2011-10-13 12:57:46 +02:00
Linus Walleij 98da352953 pinctrl: add a driver for the U300 pinmux
This adds a driver for the U300 pinmux portions of the system
controller "SYSCON". It also serves as an example of how to use
the pinmux subsystem. This driver also houses the platform data
for the only supported platform.

This deletes the old U300 driver in arch/arm/mach-u300 and
replace it with a driver using the new subsystem.

The new driver is considerably fatter than the old one, but it
also registers all 467 pins of the system and adds the power
and EMIF pin groups and corresponding functions. The idea
is to use this driver as a a reference for other
implementation so it needs to be as complete and verbose
as possible.

Reviewed-by: Barry Song <21cnbao@gmail.com>
[Fixup for changed function names and semantics in the v10 patch]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-10-13 12:57:45 +02:00
Linus Walleij 2744e8afb3 drivers: create a pin control subsystem
This creates a subsystem for handling of pin control devices.
These are devices that control different aspects of package
pins.

Currently it handles pinmuxing, i.e. assigning electronic
functions to groups of pins on primarily PGA and BGA type of
chip packages which are common in embedded systems.

The plan is to also handle other I/O pin control aspects
such as biasing, driving, input properties such as
schmitt-triggering, load capacitance etc within this
subsystem, to remove a lot of ARM arch code as well as
feature-creepy GPIO drivers which are implementing the same
thing over and over again.

This is being done to depopulate the arch/arm/* directory
of such custom drivers and try to abstract the infrastructure
they all need. See the Documentation/pinctrl.txt file that is
part of this patch for more details.

ChangeLog v1->v2:

- Various minor fixes from Joe's and Stephens review comments
- Added a pinmux_config() that can invoke custom configuration
  with arbitrary data passed in or out to/from the pinmux driver

ChangeLog v2->v3:

- Renamed subsystem folder to "pinctrl" since we will likely
  want to keep other pin control such as biasing in this
  subsystem too, so let us keep to something generic even though
  we're mainly doing pinmux now.
- As a consequence, register pins as an abstract entity separate
  from the pinmux. The muxing functions will claim pins out of the
  pin pool and make sure they do not collide. Pins can now be
  named by the pinctrl core.
- Converted the pin lookup from a static array into a radix tree,
  I agreed with Grant Likely to try to avoid any static allocation
  (which is crap for device tree stuff) so I just rewrote this
  to be dynamic, just like irq number descriptors. The
  platform-wide definition of number of pins goes away - this is
  now just the sum total of the pins registered to the subsystem.
- Make sure mappings with only a function name and no device
  works properly.

ChangeLog v3->v4:

- Define a number space per controller instead of globally,
  Stephen and Grant requested the same thing so now maps need to
  define target controller, and the radix tree of pin descriptors
  is a property on each pin controller device.
- Add a compulsory pinctrl device entry to the pinctrl mapping
  table. This must match the pinctrl device, like "pinctrl.0"
- Split the file core.c in two: core.c and pinmux.c where the
  latter carry all pinmux stuff, the core is for generic pin
  control, and use local headers to access functionality between
  files. It is now possible to implement a "blank" pin controller
  without pinmux capabilities. This split will make new additions
  like pindrive.c, pinbias.c etc possible for combined drivers
  and chunks of functionality which is a GoodThing(TM).
- Rewrite the interaction with the GPIO subsystem - the pin
  controller descriptor now handles this by defining an offset
  into the GPIO numberspace for its handled pin range. This is
  used to look up the apropriate pin controller for a GPIO pin.
  Then that specific GPIO range is matched 1-1 for the target
  controller instance.
- Fixed a number of review comments from Joe Perches.
- Broke out a header file pinctrl.h for the core pin handling
  stuff that will be reused by other stuff than pinmux.
- Fixed some erroneous EXPORT() stuff.
- Remove mispatched U300 Kconfig and Makefile entries
- Fixed a number of review comments from Stephen Warren, not all
  of them - still WIP. But I think the new mapping that will
  specify which function goes to which pin mux controller address
  50% of your concerns (else beat me up).

ChangeLog v4->v5:

- Defined a "position" for each function, so the pin controller now
  tracks a function in a certain position, and the pinmux maps define
  what position you want the function in. (Feedback from Stephen
  Warren and Sascha Hauer).
- Since we now need to request a combined function+position from
  the machine mapping table that connect mux settings to drivers,
  it was extended with a position field and a name field. The
  name field is now used if you e.g. need to switch between two
  mux map settings at runtime.
- Switched from a class device to using struct bus_type for this
  subsystem. Verified sysfs functionality: seems to work fine.
  (Feedback from Arnd Bergmann and Greg Kroah-Hartman)
- Define a per pincontroller list of GPIO ranges from the GPIO
  pin space that can be handled by the pin controller. These can
  be added one by one at runtime. (Feedback from Barry Song)
- Expanded documentation of regulator_[get|enable|disable|put]
  semantics.
- Fixed a number of review comments from Barry Song. (Thanks!)

ChangeLog v5->v6:

- Create an abstract pin group concept that can sort pins into
  named and enumerated groups no matter what the use of these
  groups may be, one possible usecase is a group of pins being
  muxed in or so. The intention is however to also use these
  groups for other pin control activities.
- Make it compulsory for pinmux functions to associate with
  at least one group, so the abstract pin group concept is used
  to define the groups of pins affected by a pinmux function.
  The pinmux driver interface has been altered so as to enforce
  a function to list applicable groups per function.
- Provide an optional .group entry in the pinmux machine map
  so the map can select beteween different available groups
  to be used with a certain function.
- Consequent changes all over the place so that e.g. debugfs
  present reasonable information about the world.
- Drop the per-pin mux (*config) function in the pinmux_ops
  struct - I was afraid that this would start to be used for
  things totally unrelated to muxing, we can introduce that to
  the generic struct pinctrl_ops if needed. I want to keep
  muxing orthogonal to other pin control subjects and not mix
  these things up.

ChangeLog v6->v7:

- Make it possible to have several map entries matching the
  same device, pin controller and function, but using
  a different group, and alter the semantics so that
  pinmux_get() will pick all matching map entries, and
  store the associated groups in a list. The list will
  then be iterated over at pinmux_enable()/pinmux_disable()
  and corresponding driver functions called for each
  defined group. Notice that you're only allowed to map
  multiple *groups* to the same
  { device, pin controller, function } triplet, attempts
  to map the same device to multiple pin controllers will
  for example fail. This is hopefully the crucial feature
  requested by Stephen Warren.
- Add a pinmux hogging field to the pinmux mapping entries,
  and enable the pinmux core to hog pinmux map entries.
  This currently only works for pinmuxes without assigned
  devices as it looks now, but with device trees we can
  look up the corresponding struct device * entries when
  we register the pinmux driver, and have it hog each
  pinmux map in turn, for a simple approach to
  non-dynamic pin muxing. This addresses an issue from
  Grant Likely that the machine should take care of as
  much of the pinmux setup as possible, not the devices.
  By supplying a list of hogs, it can now instruct the
  core to take care of any static mappings.
- Switch pinmux group retrieveal function to grab an
  array of strings representing the groups rather than an
  array of unsigned and rewrite accordingly.
- Alter debugfs to show the grouplist handled by each
  pinmux. Also add a list of hogs.
- Dynamically allocate a struct pinmux at pinmux_get() and
  free it at pinmux_put(), then add these to the global
  list of pinmuxes active as we go along.
- Go over the list of pinmux maps at pinmux_get() time
  and repeatedly apply matches.
- Retrieve applicable groups per function from the driver
  as a string array rather than a unsigned array, then
  lookup the enumerators.
- Make the device to pinmux map a singleton - only allow the
  mapping table to be registered once and even tag the
  registration function with __init so it surely won't be
  abused.
- Create a separate debugfs file to view the pinmux map at
  runtime.
- Introduce a spin lock to the pin descriptor struct, lock it
  when modifying pin status entries. Reported by Stijn Devriendt.
- Fix up the documentation after review from Stephen Warren.
- Let the GPIO ranges give names as const char * instead of some
  fixed-length string.
- add a function to unregister GPIO ranges to mirror the
  registration function.
- Privatized the struct pinctrl_device and removed it from the
  <linux/pinctrl/pinctrl.h> API, the drivers do not need to know
  the members of this struct. It is now in the local header
  "core.h".
- Rename the concept of "anonymous" mux maps to "system" muxes
  and add convenience macros and documentation.

ChangeLog v7->v8:

- Delete the leftover pinmux_config() function from the
 <linux/pinctrl/pinmux.h> header.
- Fix a race condition found by Stijn Devriendt in pin_request()

ChangeLog v8->v9:

- Drop the bus_type and the sysfs attributes and all, we're not on
  the clear about how this should be used for e.g. userspace
  interfaces so let us save this for the future.
- Use the right name in MAINTAINERS, PIN CONTROL rather than
  PINMUX
- Don't kfree() the device state holder, let the .remove() callback
  handle this.
- Fix up numerous kerneldoc headers to have one line for the function
  description and more verbose documentation below the parameters

ChangeLog v9->v10:
- pinctrl: EXPORT_SYMBOL needs export.h, folded in a patch
  from Steven Rothwell
- fix pinctrl_register error handling, folded in a patch from
  Axel Lin
- Various fixes to documentation text so that it's consistent.
- Removed pointless comment from drivers/Kconfig
- Removed dependency on SYSFS since we removed the bus in
  v9.
- Renamed hopelessly abbreviated pctldev_* functions to the
  more verbose pinctrl_dev_*
- Drop mutex properly when looking up GPIO ranges
- Return NULL instead of ERR_PTR() errors on registration of
  pin controllers, using cast pointers is fragile. We can
  live without the detailed error codes for sure.

Cc: Stijn Devriendt <highguy@gmail.com>
Cc: Joe Perches <joe@perches.com>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-10-13 12:49:17 +02:00