This adds in the L1I/L1D/L2 cache shape support to their respective
entries in the ELF auxvt, based on the Alpha implementation. We use
this on the userspace libc side for calculating a tightly packed
SHMLBA amongst other things.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
When a get_user(to, from++) is called the pointer increment is performed
after its first usage, in the specific after the __add_ok invokation.
This causes a wrong get_user return value, putting a wrong character
in the destination variable. This patch solves the problem using a new
temporary pointer.
Additionally this reworks the use of the register banks, allowing for
consolidation between the MMU and nommu implementations.
Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com>
Signed-off-by: Giuseppe Condorelli <giuseppe.condorelli@st.com>
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Presently most of the 29-bit physical parts do P1/P2 segmentation
with a 1:1 cached/uncached mapping, jumping between the two to
control the caching behaviour. This provides the basic infrastructure
to maintain this behaviour on 32-bit physical parts that don't map
P1/P2 at all, using a shiny new linker section and corresponding
fixmap entry.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This implements kernel-level atomic rollback built on top of gUSA,
as an alternative non-IRQ based atomicity method. This is generally
a faster method for platforms that are lacking the LL/SC pairs that
SH-4A and later use, and is only supportable on legacy cores.
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
With all of the different CPU types this was getting a but unwieldly.
Since sh64 is now integrated, we don't have to worry about multiple
architectures caring about the header definitions.
Split out the defs for each asm/cpu/ to make rtc-sh slightly less
visually offensive.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Avoid namespace collision with a CCR1 definition. The general
SH code always expects CCR anyways, so there's no point in keeping
the CCR1 naming around.
Fixes up synclink collisions:
drivers/char/pcmcia/synclink_cs.c:283:1: warning: "CCR1" redefined
In file included from include/asm/cache.h:13,
from include/asm/processor_32.h:15,
from include/asm/processor.h:60,
from include/linux/prefetch.h:14,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/char/pcmcia/synclink_cs.c:38:
include/asm/cpu/cache.h:21:1: warning: this is the location of the previous definition
Reported-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This adds support for the SH7263 (SH-2A) CPU.
This particular CPU is a superset of SH7203, adding some additional
peripheral blocks and hooking up additional (reserved on SH7203)
vectors in the INTC block.
No visibly nasty surprises, yet..
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Move the HAVE_ARCH_BUG/HAVE_ARCH_WARN_ON definitions underneath
CONFIG_GENERIC_BUG. This is needed for BUGFLAG_WARNING usage.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The CPU family abstraction already exists, so move out the PXSEG
definition for each one. SH-2A already has this special cased,
and SH-5 will as well.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
When the thread_info->addr_limit changes were introduced, __access_ok()
was missed in the conversion, allowing user processes to perform P1/P2
accesses under certain conditions.
This has already been corrected with the nommu refactoring in later
kernels.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
In the do_execve() path, argument page handling used to explicitly call
flush_dcache_page() for each page, this has since been reworked and
uses flush_kernel_dcache_page() instead, which is presently a nop.
Doing a simple modprobe/rmmod in a loop under busybox consistently
manages to crash without providing a sane flush_kernel_dcache_page()
implementation, so, plug in a simple implementation.
Signed-off-by: Carmelo Amoroso <carmelo73@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
We have nothing to do here, but there are continually drivers that
fail to build without it. Stub it in.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Now that copy_to_user_page()/copy_from_user_page() are wired up, we
can drop the old __copy_xxx() implementations. Now that the page
colouring scheme has changed via kmap_coherent(), we can avoid the
flush in these specific helpers.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This moves copy_{to,from}_user_page() out-of-line on SH-4 and
converts for the kmap_coherent() API. Based on the MIPS
implementation.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
With the kmap_coherent() API in place, this is trivial to implement,
and lets us avoid the cache flush in certain cases.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The ST40 stuff in-tree hasn't built for some time, and hasn't been
updated for over 3 years. ST maintains their own out-of-tree changes
and rebases occasionally, and that's ultimately where all of the ST40
users go anyways.
In order for the ST40 code to be brought up to date most of the stuff
removed in this changeset would have to be rewritten anyways, so there's
very little benefit in keeping the remnants around either.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The common linux/ptrace.h already defines PTRACE_O_TRACESYSGOOD so there is no
need to have arches do it. This also keeps glibc-2.7 from breaking since it
has an enum for the PTRACE_O_* flags.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
While using separate IRQ stacks can cut down on stack consumption,
many users can also use 4k stacks directly without the additional
need of separate stacks for soft and hardirqs.
With this split, we support the same rationale for 4KSTACKS as
m68knommu, with the IRQSTACKS abstraction as per ppc64.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
As noted by David:
pte_page() is a macro defined as follows;
include/asm-sh/pgtable.h
#define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK)
include/asm-sh/page.h
#define phys_to_page(phys) (pfn_to_page(phys >> PAGE_SHIFT))
So as you can see the phys_to_page() macro doesn't wrap the 'phys'
parameter in parentheses so we end up with;
pte_val(x)&PTE_PHYS_MASK >> PAGE_SHIFT
Which is not what we wanted as '>>' has a higher precedence than bitwise
AND. I dug into the git repository and I believe this bug was added with
this commit (104b8deaa5);
2006-03-27 KAMEZAWA Hiroyuki [PATCH] unify pfn_to_page: sh pfn_to_page
-#define phys_to_page(phys) (mem_map + (((phys)-__MEMORY_START) >>
PAGE_SHIFT))
-#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) +
__MEMORY_START)
+#define phys_to_page(phys) (pfn_to_page(phys >> PAGE_SHIFT))
+#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
Reported-by: David ADDISON <david.addison@st.com>
Reported-by: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Change the page member of the scatterlist structure to be an unsigned
long, and encode more stuff in the lower bits:
- Bits 0 and 1 zero: this is a normal sg entry. Next sg entry is located
at sg + 1.
- Bit 0 set: this is a chain entry, the next real entry is at ->page_link
with the two low bits masked off.
- Bit 1 set: this is the final entry in the sg entry. sg_next() will return
NULL when passed such an entry.
It's thus important that sg table users use the proper accessors to get
and set the page member.
Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
Fix the various misspellings of "system", controller", "interrupt" and
"[un]necessary".
Signed-off-by: Robert P. J. Day <rpjday@mindspring.com>
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Joe Perches
Paul Mundt
Stuart Menefy
Yuichi Nakamura
Carmelo Amoroso
Heiko Schocher
Jiri Olsa
Mike Frysinger
Jens Axboe
Robert P. J. Day