Commit Graph

8 Commits

Author SHA1 Message Date
Hans de Goede ef6d24cc7f pinctrl: sun4i: GPIOs configured as irq must be set to input before reading
On sun4i-a10, when GPIOs are configured as external interrupt the value for
them in the data register does not seem to get updated, so set their mux to
input (and restore afterwards) when reading the pin.

Missed edges seem to be buffered, so this does not introduce a race
condition.

I've also tested this on sun5i-a13 and sun7i-a20 and those do not seem to
be affected, the input value representation in the data register does seem
to correctly get updated to the actual pin value while in irq mode there.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 10:56:46 +01:00
Maxime Ripard 4f6bd5cfc6 pinctrl: sunxi: Add PN bank base pin
The A80 R-PIO controller has one more bank that what we've seen so far, add the
PN pin bank.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-30 15:55:26 +01:00
Maxime Ripard aebdc8abc9 pinctrl: sunxi: Implement multiple interrupt banks support
The A23 and A31 support multiple interrupt banks. Support it by adding a linear
domain covering all the banks. It's trickier than it should because there's an
interrupt per bank, so we have multiple interrupts using the same domain.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:12 +02:00
Maxime Ripard 8966ada2d4 pinctrl: sunxi: Declare the number of interrupt banks in the descriptor
Declare in the description structure associated to the compatible the number of
interrupt banks the device has. For now, we're not doing anything with it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:11 +02:00
Maxime Ripard 6e1c30239f pinctrl: sunxi: Add macro definition for pinctrl with more than one interrupt
The A31 and A23, unlike the other Allwinner SoCs, have several interrupts banks
and parent interrupts, while the other only have up to 32 interrupts in a
single bank and a single parent interrupt.

Start supporting it by introducing a function macro to declare irq functions
and their banks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-19 09:35:11 +02:00
Maxime Ripard 2284ba6b7d pinctrl: sunxi: Libraryse the driver
This will allow to have multiple drivers using the same core code, and
eventually, retire pinctrl-sunxi-pins.h

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:24 -07:00
Maxime Ripard d10acc6353 pinctrl: sunxi: Replace hardcoded pin defines by a macro
We previously had an evergrowing (and exhaustive) list of the pins that could
be used on any Allwinner SoCs. These defines were then used by each pinctrl
driver to declare the list of functions for this pin. Since it's pretty much
all boilerplate, we can remove it just by a single macro.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:44 -07:00
Maxime Ripard 5f9107774f pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directory
This will allow to create numerous files without crippling the main pinctrl
directory.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:43 -07:00