Commit Graph

1590 Commits

Author SHA1 Message Date
Linus Torvalds eb3d3ec567 Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into next
Pull ARM updates from Russell King:

 - Major clean-up of the L2 cache support code.  The existing mess was
   becoming rather unmaintainable through all the additions that others
   have done over time.  This turns it into a much nicer structure, and
   implements a few performance improvements as well.

 - Clean up some of the CP15 control register tweaks for alignment
   support, moving some code and data into alignment.c

 - DMA properties for ARM, from Santosh and reviewed by DT people.  This
   adds DT properties to specify bus translations we can't discover
   automatically, and to indicate whether devices are coherent.

 - Hibernation support for ARM

 - Make ftrace work with read-only text in modules

 - add suspend support for PJ4B CPUs

 - rework interrupt masking for undefined instruction handling, which
   allows us to enable interrupts earlier in the handling of these
   exceptions.

 - support for big endian page tables

 - fix stacktrace support to exclude stacktrace functions from the
   trace, and add save_stack_trace_regs() implementation so that kprobes
   can record stack traces.

 - Add support for the Cortex-A17 CPU.

 - Remove last vestiges of ARM710 support.

 - Removal of ARM "meminfo" structure, finally converting us solely to
   memblock to handle the early memory initialisation.

* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits)
  ARM: ensure C page table setup code follows assembly code (part II)
  ARM: ensure C page table setup code follows assembly code
  ARM: consolidate last remaining open-coded alignment trap enable
  ARM: remove global cr_no_alignment
  ARM: remove CPU_CP15 conditional from alignment.c
  ARM: remove unused adjust_cr() function
  ARM: move "noalign" command line option to alignment.c
  ARM: provide common method to clear bits in CPU control register
  ARM: 8025/1: Get rid of meminfo
  ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type
  ARM: 8066/1: correction for ARM patch 8031/2
  ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation
  ARM: 8065/1: remove last use of CONFIG_CPU_ARM710
  ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction
  ARM: 8047/1: rwsem: use asm-generic rwsem implementation
  ARM: l2c: trial at enabling some Cortex-A9 optimisations
  ARM: l2c: add warnings for stuff modifying aux_ctrl register values
  ARM: l2c: print a warning with L2C-310 caches if the cache size is modified
  ARM: l2c: remove old .set_debug method
  ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this
  ...
2014-06-05 15:57:04 -07:00
Russell King bd63ce27d9 Merge branch 'devel-stable' into for-next 2014-06-05 12:36:22 +01:00
Russell King 1fb333489f Merge branches 'alignment', 'fixes', 'l2c' (early part) and 'misc' into for-next 2014-06-05 12:35:52 +01:00
Naoya Horiguchi c177c81e09 hugetlb: restrict hugepage_migration_support() to x86_64
Currently hugepage migration is available for all archs which support
pmd-level hugepage, but testing is done only for x86_64 and there're
bugs for other archs.  So to avoid breaking such archs, this patch
limits the availability strictly to x86_64 until developers of other
archs get interested in enabling this feature.

Simply disabling hugepage migration on non-x86_64 archs is not enough to
fix the reported problem where sys_move_pages() hits the BUG_ON() in
follow_page(FOLL_GET), so let's fix this by checking if hugepage
migration is supported in vma_migratable().

Signed-off-by: Naoya Horiguchi <n-horiguchi@ah.jp.nec.com>
Reported-by: Michael Ellerman <mpe@ellerman.id.au>
Tested-by: Michael Ellerman <mpe@ellerman.id.au>
Acked-by: Hugh Dickins <hughd@google.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Miller <davem@davemloft.net>
Cc: <stable@vger.kernel.org>	[3.12+]
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-06-04 16:53:51 -07:00
Linus Torvalds d27050641e DeviceTree for 3.16:
- Another round of clean-up of FDT related code in architecture code.
   This removes knowledge of internal FDT details from most architectures
   except powerpc.
 - Conversion of kernel's custom FDT parsing code to use libfdt.
 - DT based initialization for generic serial earlycon. The introduction
   of generic serial earlycon support went in thru tty tree.
 - Improve the platform device naming for DT probed devices to ensure
   unique naming and use parent names instead of a global index.
 - Fix a race condition in of_update_property.
 - Unify the various linker section OF match tables and fix several
   function prototype errors.
 - Update platform_get_irq_byname to work in deferred probe cases.
 - 2 binding doc updates
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Merge tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next

Pull DeviceTree updates from Rob Herring:
 - Another round of clean-up of FDT related code in architecture code.
   This removes knowledge of internal FDT details from most
   architectures except powerpc.
 - Conversion of kernel's custom FDT parsing code to use libfdt.
 - DT based initialization for generic serial earlycon.  The
   introduction of generic serial earlycon support went in through the
   tty tree.
 - Improve the platform device naming for DT probed devices to ensure
   unique naming and use parent names instead of a global index.
 - Fix a race condition in of_update_property.
 - Unify the various linker section OF match tables and fix several
   function prototype errors.
 - Update platform_get_irq_byname to work in deferred probe cases.
 - 2 binding doc updates

* tag 'devicetree-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (58 commits)
  of: handle NULL node in next_child iterators
  of/irq: provide more wrappers for !CONFIG_OF
  devicetree: bindings: Document micrel vendor prefix
  dt: bindings: dwc2: fix required value for the phy-names property
  of_pci_irq: kill useless variable in of_irq_parse_pci()
  of/irq: do irq resolution in platform_get_irq_byname()
  of: Add a testcase for of_find_node_by_path()
  of: Make of_find_node_by_path() handle /aliases
  of: Create unlocked version of for_each_child_of_node()
  lib: add glibc style strchrnul() variant
  of: Handle memory@0 node on PPC32 only
  pci/of: Remove dead code
  of: fix race between search and remove in of_update_property()
  of: Use NULL for pointers
  of: Stop naming platform_device using dcr address
  of: Ensure unique names without sacrificing determinism
  tty/serial: pl011: add DT based earlycon support
  of/fdt: add FDT serial scanning for earlycon
  of/fdt: add FDT address translation support
  serial: earlycon: add DT support
  ...
2014-06-04 10:02:38 -07:00
Linus Torvalds ff806d034e Merge branch 'for-v3.16' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping into next
Pull CMA and DMA-mapping fixes from Marek Szyprowski:
 "A few fixes for dma-mapping and CMA subsystems"

* 'for-v3.16' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping:
  CMA: correct unlock target
  drivers/base/dma-contiguous.c: erratum of dev_get_cma_area
  arm: dma-mapping: add checking cma area initialized
  arm: dma-iommu: Clean up redundant variable
  cma: Remove potential deadlock situation
2014-06-03 11:51:51 -07:00
Russell King 20e7e36433 ARM: ensure C page table setup code follows assembly code (part II)
This does the same as the previous commit, but for the S bit, which also
needs to match the initial value which the assembly code used for the
same reasons.  Again, we add a check for SMP to ensure that the page
tables are correctly setup for SMP.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-02 12:52:43 +01:00
Russell King ca8f0b0a54 ARM: ensure C page table setup code follows assembly code
Fix a long standing bug where, for ARMv6+, we don't fully ensure that
the C code sets the same cache policy as the assembly code.  This was
introduced partially by commit 11179d8ca2 ([ARM] 4497/1: Only allow
safe cache configurations on ARMv6 and later) and also by adding SMP
support.

This patch sets the default cache policy based on the flags used by the
assembly code, and then ensures that when a cache policy command line
argument is used, we verify that on ARMv6, it matches the initial setup.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-02 09:23:54 +01:00
Russell King 0aeb3408ca ARM: remove global cr_no_alignment
cr_no_alignment is really only used by the alignment code.  Since we no
longer change the setting of cr_alignment after boot, we can localise
this to alignment.c

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-02 09:20:18 +01:00
Russell King 3cb099f089 ARM: remove CPU_CP15 conditional from alignment.c
alignment.c will not be built unless CPU_CP15 is set:

config CPU_CP15
        bool

config CPU_CP15_MMU
        bool
        select CPU_CP15

config ALIGNMENT_TRAP
        bool
        depends on CPU_CP15_MMU

So there's no point having conditionals on CPU_CP15 within this code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-02 09:20:16 +01:00
Russell King c6e13600d3 ARM: remove unused adjust_cr() function
adjust_cr() is not used anymore, so let's get rid of it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-02 09:20:14 +01:00
Russell King 175352a51c ARM: move "noalign" command line option to alignment.c
Keep all bits of alignment handling together.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-02 09:20:13 +01:00
Russell King b4b20ad881 ARM: provide common method to clear bits in CPU control register
Several places open-code this manipulation, let's consolidate this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-02 09:20:11 +01:00
Laura Abbott 1c2f87c225 ARM: 8025/1: Get rid of meminfo
memblock is now fully integrated into the kernel and is the prefered
method for tracking memory. Rather than reinvent the wheel with
meminfo, migrate to using memblock directly instead of meminfo as
an intermediate.

Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-01 01:17:12 +01:00
Thomas Petazzoni 1c8c3cf0b5 ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type
Due to a design incompatibility between the PCIe Marvell controller
and the Cortex-A9, stressing PCIe devices with a lot of traffic
quickly causes a deadlock.

One part of the workaround for this is to have all PCIe regions mapped
as strongly-ordered (MT_UNCACHED) instead of the default
MT_DEVICE. While the arch_ioremap_caller() mechanism allows
sub-architecture code to override ioremap(), used to map PCIe memory
regions, there isn't such a mechanism to override the behavior of
pci_ioremap_io().

This commit adds the arch_pci_ioremap_mem_type variable, initialized
to MT_DEVICE by default, and that sub-architecture code can
override. We have chosen to expose a single variable rather than
offering the possibility of overriding the entire pci_ioremap_io(),
because implementing pci_ioremap_io() requires calling functions
(get_mem_type()) that are private to the arch/arm/mm/ code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-01 01:15:04 +01:00
Russell King 8ef418c717 ARM: l2c: trial at enabling some Cortex-A9 optimisations
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:50:41 +01:00
Russell King 560be6136b ARM: l2c: add warnings for stuff modifying aux_ctrl register values
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:50:38 +01:00
Russell King 314e47b7b6 ARM: l2c: print a warning with L2C-310 caches if the cache size is modified
As we have now removed all instances of the L2C-310 having its cache
size "modified" via platform/SoC code, discourage new cases showing
up by printing a warning.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:50:37 +01:00
Russell King 678ea28b7c ARM: l2c: remove old .set_debug method
We no longer need or require the .set_debug method; we handle everything
it used to do via the .write_sec method instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:50:35 +01:00
Russell King de7e75326c ARM: l2c: provide common PL310 early resume code
Provide a common assembly implementation for PL310 resume code.  Certain
platforms need to re-initialise the L2C cache early as it may preserve
data across a S2RAM cycle, and therefore must be enabled along with the
L1 cache and MMU.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:49:01 +01:00
Russell King a4b041a0e2 ARM: l2c: always enable non-secure access to lockdown registers
Since we always write to these during the cache initialisation, it is
a good idea to always have the non-secure access bit set.  Set it in
core code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:57 +01:00
Russell King 3a43b581da ARM: l2c: always enable low power modes
Always enable the L2C low power modes on L2C-310 R3P0 and newer parts.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:54 +01:00
Russell King 4374d64933 ARM: l2c: add automatic enable of early BRESP
The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted.  Early
BRESP allows the L2C-310 to send the write response as soon as the
store buffer accepts the write address.

Cortex-A9 processors can signal to the L2C-310 that they wish to be
notified early, and if this optimisation is enabled, the L2C-310 can
signal an early write response.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:50 +01:00
Russell King ddf7d79bc7 ARM: l2c: move L2 cache register saving to a more sensible location
Move the L2 cache register saving to a more sensible location - after
the cache has been enabled, and fixups have been run.  We move the
saving of the auxiliary control register into the ->save function as
well which makes everything operate in a sane and maintainable way.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:47 +01:00
Russell King d9d1f3e2d7 ARM: l2c: check that DT files specify the required "cache-unified" property
This is a required property, and should always be specified.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:45 +01:00
Russell King 1a5a954ce0 ARM: l2c: fix register naming
We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess.  Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices.  Provide full auxiliary control register definitions.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:43 +01:00
Russell King a8875a092a ARM: l2c: implement L2C-310 erratum 752271 in core L2C code
Rather than having SoCs work around L2C erratum themselves, move them
into core code.  This erratum affects the double linefill feature which
needs to be disabled for r3p0 to r3p1-50rel0.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:41 +01:00
Russell King 8abd259f65 ARM: l2c: provide generic hook to intercept writes to secure registers
When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort.  Platforms normally have to call
firmware to work around this.  Provide a hook for them to intercept
any L2C secure register write.

l2c_write_sec() avoids writes to secure registers which are already set
to the appropriate value, thus avoiding the overhead of needlessly
calling into the secure monitor.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:39 +01:00
Russell King c0fe18ba30 ARM: l2c: move errata configuration options to arch/arm/mm/Kconfig
Move the L2C-310 errata configuration options to arch/arm/mm/Kconfig
along side the option which enables support for this device.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:37 +01:00
Russell King 0493aef4da ARM: l2c: move way size calculation data into l2c_init_data
Move the way size calculation data (base of way size) out of the
switch statement into the provided initialisation data.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:34 +01:00
Russell King 5f47c38704 ARM: l2c: add decode for L2C-220 cache ways
Rather than assuming these are always 8-way, it can be decoded from the
auxillary register in the same manner as L2C-210.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:33 +01:00
Russell King 051334bdc5 ARM: l2c: move type string into l2c_init_data structure
Rather than decoding this from the ID register, store it in the
l2c_init_data structure.  This simplifies things some more, and
allows us to better provide further details as to how we're
driving the cache.  We print the cache ID value anyway should we
need to precisely identify the cache hardware.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:30 +01:00
Russell King cf9ea8f130 ARM: l2c: remove obsolete l2x0 ops for non-OF init
non-OF initialisation has never been used with any cache controller
which isn't an ARM cache controller, so we can safely get rid of the
old (and buggy) l2x0_*-based operations structure.

This is also the last reference to:
- l2x0_clean_line()
- l2x0_inv_line()
- l2x0_flush_line()
- l2x0_flush_all()
- l2x0_clean_all()
- l2x0_inv_all()
- l2x0_inv_range()
- l2x0_clean_range()
- l2x0_flush_range()
- l2x0_enable()
- l2x0_resume()
so kill those functions too.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:28 +01:00
Russell King 9081114837 ARM: l2c: convert Broadcom L2C-310 to new code
The Broadcom L2C-310 devices use ARMs L2C-310 R2P3 or later.  These
require no errata workarounds, and so we can directly call the l2c210
functions from their methods.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:26 +01:00
Russell King 733c6bbafd ARM: l2c: add L2C-220 specific handlers
The L2C-220 is different from the L2C-210 and L2C-310 in that every
operation is a background operation: this means we have to use
spinlocks to protect all operations, and we have to wait for every
operation to complete.

Should a second operation be attempted while a previous operation
is in progress, the response will be an imprecise abort.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:24 +01:00
Russell King f777332ba7 ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementations
Where no errata affect the L2C-310 handlers, they are functionally
equivalent to L2C-210.  Re-use the L2C-210 handlers for the L2C-310
part.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:21 +01:00
Russell King ebd4219f10 ARM: l2c: implement L2C-310 erratum 588369 as a method override
Implement L2C-310 erratum 588369 by overriding the invalidate range
and flush range methods in the outer_cache operations structure.
This allows us to sensibly contain the erratum code in one place
without affecting other locations/implemetations.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:19 +01:00
Russell King 99ca1772e5 ARM: l2c: implement L2C-310 erratum 727915 as a method override
Implement L2C-310 erratum 727915 by overriding the flush_all method
in the outer_cache operations structure.  This allows us to sensibly
contain the erratum code in one place without affecting other
locations or implementations.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:17 +01:00
Russell King 6a28cf59ff ARM: l2c: add L2C-210 specific handlers
Add L2C-210 specific cache operation handlers.  These are tailored to
the requirements of the L2C-210 cache controller, which doesn't
require any workarounds.  We avoid using the way operations during
normal operation, which means we can avoid locking: the only time
we use the way operations are during initialisation, and when
disabling the cache.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:15 +01:00
Russell King bda0b74e6a ARM: l2c: move pl310_set_debug() into l2c-310 code
Move the pl310_set_debug() into the l2c-310 code area, and don't hide
it with ifdefs.  Rename it to l2c310_set_debug().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:13 +01:00
Russell King faf9b2e701 ARM: l2c: simplify l2x0 unlocking code
The l2x0 unlocking code is only called from l2x0_enable() now, so move
the logic entirely into that function and simplify it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:11 +01:00
Russell King 09a5d180ed ARM: l2c: clean up save/resume functions
Rename the pl310 save/resume functions to have a l2c310 prefix - this
is it's official name.  Use a local cached copy of the l2x0_base
virtual address, and also realise that many of the resume function
tails are the same as the enable functions, so make a call to the
enable function instead of duplicating that code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:08 +01:00
Russell King b98556f26d ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OF
Add the save/resume code hooks to the non-OF implementations as well.
There's no reason for the non-OF implementations to be any different
from the OF implementations.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:05 +01:00
Russell King cdef8689ef ARM: l2c: clean up L2 cache initialisation messages
Make one of them purely "English", and the other purely technical.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:03 +01:00
Russell King 75461f5c84 ARM: l2c: implement fixups for L2 cache controller quirks/errata
Rather than putting quirk handling in __l2c_init(), move it out to a
separate function which individual implementations can specify.  This
helps to localise the quirks to those implementations which require
them.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:01 +01:00
Russell King 40266d6f41 ARM: l2c: move aurora broadcast setup to enable function
Rather than having this hacked into the OF initialiation function, we
can handle this via the enable function instead.  While here, clean
up that code and comments a little.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:59 +01:00
Russell King 9a07f27bc5 ARM: l2c: only write the auxiliary control register if required
Avoid unnecessary writes to the auxiliary control register if the
register already contains the required value.  This allows us to
avoid invoking the platforms secure monitor code unnecessarily.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:57 +01:00
Russell King 17f3f99fab ARM: l2c: write auxctrl register before unlocking
We should write the auxillary control register before unlocking: the
write may be necessary to enable non-secure access to the lock
registers.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:54 +01:00
Russell King 3b8bad5758 ARM: l2c: provide enable method
Providing an enable method gives L2 cache controllers a chance to do
special handling at enable time.  This allows us to remove a hack in
l2x0_unlock() for Marvell Aurora L2 caches.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:51 +01:00
Russell King da3627fbda ARM: l2c: group implementation specific code together
Back in the mists of time, someone decided that it would be a good idea
to group like functions together - so all the save functions in one
place, all the resume functions in another, all the OF parsing functions
some place else.

This makes it difficult to get an overview on what a particular
implementation is doing - grouping an implementations specific functions
together makes more sense, because you can see what it's doing without
the clutter of other implementations.

Organise it according to implementation.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:50 +01:00