Commit Graph

528 Commits

Author SHA1 Message Date
Russell King 7dd8c4f352 [ARM] fix StrongARM-11x0 page copy implementation
Which had the 'from' and 'to' pages reversed.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-01-24 11:41:17 +00:00
Nicolas Pitre 98007c230e [ARM] 5364/1: allow flush_ioremap_region() to be used from modules
Without this, the pxa2xx-flash driver cannot be used as a module.

Reported-by: Chris Lawrence <chrisdl@netspace.net.au>

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-01-12 13:51:03 +00:00
David Howells 9c93af1ede NOMMU: Rename ARM's struct vm_region
Rename ARM's struct vm_region so that I can introduce my own global version
for NOMMU.  It's feasible that the ARM version may wish to use my global one
instead.

The NOMMU vm_region struct defines areas of the physical memory map that are
under mmap.  This may include chunks of RAM or regions of memory mapped
devices, such as flash.  It is also used to retain copies of file content so
that shareable private memory mappings of files can be made.  As such, it may
be compatible with what is described in the banner comment for ARM's vm_region
struct.

Signed-off-by: David Howells <dhowells@redhat.com>
2009-01-08 12:04:47 +00:00
Russell King c613bbba6f Merge branch 'mxc-pu-imxfb' of git://pasiphae.extern.pengutronix.de/git/imx/linux-2.6 into devel 2008-12-17 20:04:45 +00:00
Russell King 7e1548a597 Merge branch 'omap3-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel 2008-12-15 22:13:26 +00:00
Russell King 67306da610 [ARM] Ensure linux/hardirqs.h is included where required
... for the removal of it from asm-generic/local.h

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-12-15 10:34:48 +00:00
Julia Lawall 6ce1b871db [ARM] eliminate NULL test and memset after alloc_bootmem
As noted by Akinobu Mita in patch b1fceac2b9,
alloc_bootmem and related functions never return NULL and always return a
zeroed region of memory.  Thus a NULL test or memset after calls to these
functions is unnecessary.

This was fixed using the following semantic patch.
(http://www.emn.fr/x-info/coccinelle/)

// <smpl>
@@
expression E;
statement S;
@@

E = \(alloc_bootmem\|alloc_bootmem_low\|alloc_bootmem_pages\|alloc_bootmem_low_pages\|alloc_bootmem_node\|alloc_bootmem_low_pages_node\|alloc_bootmem_pages_node\)(...)
... when != E
(
- BUG_ON (E == NULL);
|
- if (E == NULL) S
)

@@
expression E,E1;
@@

E = \(alloc_bootmem\|alloc_bootmem_low\|alloc_bootmem_pages\|alloc_bootmem_low_pages\|alloc_bootmem_node\|alloc_bootmem_low_pages_node\|alloc_bootmem_pages_node\)(...)
... when != E
- memset(E,0,E1);
// </smpl>

Signed-off-by: Julia Lawall <julia@diku.dk>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-12-14 12:05:03 +00:00
Russell King baa745a337 [ARM] Fix alignment fault handling for ARMv6 and later CPUs
On ARMv6 and later CPUs, it is possible for userspace processes to
get stuck on a misaligned load or store due to the "ignore fault"
setting; unlike previous CPUs, retrying the instruction without
the 'A' bit set does not always cause the load to succeed.

We have no real option but to default to fixing up alignment faults
on these CPUs, and having the CPU fix up those misaligned accesses
which it can.

Reported-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-12-07 09:44:55 +00:00
Russell King c5b84b3bb0 Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel
Conflicts:

	arch/arm/mach-pxa/pxa25x.c
2008-12-02 22:07:40 +00:00
Eric Miao 59c7bcd4d6 [ARM] pxa: add base PXA935 support due to CPUID change
PXA935 has changed its implementor ID from Intel to Marvell, this
patch modifies arch/arm/boot/compressed/head.S and proc-xsc3.S to
support a smooth bootup.

Signed-off-by: Eric Miao <eric.miao@marvell.com>
2008-12-02 14:42:40 +08:00
Russell King 657e1de8e7 Merge branch 'for-rmk-realview' of git://linux-arm.org/linux-2.6 into devel 2008-12-01 17:53:45 +00:00
Jon Callan 4c3ea37171 RealView: Add Cortex-A9 support to the EB board
This patch adds the necessary definitions and Kconfig entries to enable
Cortex-A9 (ARMv7 SMP) tiles on the RealView/EB board.

Signed-off-by: Jon Callan <Jon.Callan@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-12-01 14:54:56 +00:00
Russell King 37efe6427d [ARM] use asm/sections.h
Update to use the asm/sections.h header rather than declaring these
symbols ourselves.  Change __data_start to _data to conform with the
naming found within asm/sections.h.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-12-01 11:53:07 +00:00
Russell King 87c52578bd [ARM] Remove linux/sched.h from asm/cacheflush.h and asm/uaccess.h
... and fix those drivers that were incorrectly relying upon
that include.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-29 18:49:55 +00:00
Russell King 5bed1fb328 [ARM] Remove unnecessary mach/hardware.h includes in arch/arm/mm
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28 23:20:39 +00:00
Russell King 7ef4de17cc Merge branch 'highmem' into devel
Conflicts:

	arch/arm/mach-clps7500/include/mach/memory.h
2008-11-28 15:39:02 +00:00
Nicolas Pitre 252d4c276d [ARM] remove bogus #ifdef CONFIG_HIGHMEM in show_pte()
The restriction on !CONFIG_HIGHMEM is unneeded since page tables are
currently never allocated with highmem pages, and actually disable PTE
dump whenever highmem is configured.  Let's have a dynamic test to better
describe the current limitation instead.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28 15:36:47 +00:00
Nicolas Pitre 9210807cb5 [ARM] prevent the vmalloc cmdline argument from eating all memory
Commit 8d5796d2ec allows for the vmalloc
area to be resized from the kernel cmdline.  Make sure it cannot overlap
with RAM entirely.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28 15:36:47 +00:00
Nicolas Pitre 6db015e49c [ARM] mem_init() cleanups
Make free_area() arguments pfn based, and return number of freed pages.
This will simplify highmem initialization later.

Also, codepages, datapages and initpages are actually codesize, datasize
and initsize.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28 15:36:46 +00:00
Nicolas Pitre a1bbaec0cd [ARM] split highmem into its own memory bank
Doing so will greatly simplify the bootmem initialization code as each
bank is therefore entirely lowmem or highmem with no crossing between
those zones.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28 15:36:45 +00:00
Nicolas Pitre 4b5f32cee0 [ARM] rationalize memory configuration code some more
Currently there are two instances of struct meminfo: one in
kernel/setup.c marked __initdata, and another in mm/init.c with
permanent storage.  Let's keep only the later to directly populate
the permanent version from arm_add_memory().

Also move common validation tests between the MMU and non-MMU cases
into arm_add_memory() to remove some duplication.  Protection against
overflowing the membank array is also moved in there in order to cover
the kernel cmdline parsing path as well.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28 15:36:44 +00:00
Nicolas Pitre 43ae286b7d [ARM] fix a couple clear_user_highpage assembly constraints
In all cases the kaddr is assigned an input register even though it is
modified in the assembly code.  Let's assign a new variable to the
modified value and mark those inline asm with volatile otherwise they
get optimized away because the output variable is otherwise not used.

Also fix a few conversion errors in copypage-feroceon.c and
copypage-v4mc.c.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-28 15:36:43 +00:00
Russell King 303c644365 [ARM] clearpage: provide our own clear_user_highpage()
For similar reasons as copy_user_page(), we want to avoid the
additional kmap_atomic if it's unnecessary.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-27 23:53:48 +00:00
Russell King 063b0a4207 [ARM] copypage: provide our own copy_user_highpage()
We used to override the copy_user_page() function.  However, this
is not only inefficient, it also causes additional complexity for
highmem support, since we convert from a struct page to a kernel
direct mapped address and back to a struct page again.

Moreover, with highmem support, we end up pointlessly setting up
kmap entries for pages which we're going to remap.  So, push the
kmapping down into the copypage implementation files where it's
required.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-27 23:53:47 +00:00
Russell King d73e60b714 [ARM] copypage: convert assembly files to C
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-27 23:53:46 +00:00
Russell King f412b09f4e Merge branch 'for-rmk' of git://linux-arm.org/linux-2.6 into devel 2008-11-27 12:42:48 +00:00
Russell King c750815e2d [ARM] Arrange for platforms to select appropriate CPU support
Rather than:

	config CPU_BLAH
		bool
		depends on ARCH_FOO || MACH_BAR
		default y if ARCH_FOO || MACH_BAR

arrange for ARCH_FOO and MACH_BAR to select CPU_BLAH directly.

Acked-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Andrew Victor <linux@maxim.org.za>
Acked-by: Brian Swetland <swetland@google.com>
Acked-by: Eric Miao <eric.miao@marvell.com>
Acked-by: Nicolas Bellido <ml@acolin.be>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-27 12:38:00 +00:00
Russell King 59f0cb0fdd [ARM] remove memzero()
As suggested by Andrew Morton, remove memzero() - it's not supported
on other architectures so use of it is a potential build breaking bug.
Since the compiler optimizes memset(x,0,n) to __memzero() perfectly
well, we don't miss out on the underlying benefits of memzero().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-27 12:37:59 +00:00
Catalin Marinas 8553cb67d2 Modern processors may need to drain the WB before WFI
Since WFI may cause the processor to enter a low-power mode, data may
still be in the write buffer. This patch adds a DSB (or DWB) to the
cpu_(v6|v7)_do_idle functions before the WFI.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-11-10 14:14:11 +00:00
Russell King ebb4c65869 [ARM] iop: iop3xx needs registers mapped uncached+unbuffered
Mikael Pettersson reported:

   The 2.6.28-rc kernels fail to detect PCI device 0000:00:01.0
   (the first ethernet port) on my Thecus n2100 XScale box.

   There is however still a strange "ghost" device that gets partially
   detected in 2.6.28-rc2 vanilla.

The IOP321 manual says:

  The user designates the memory region containing the OCCDR as
  non-cacheable and non-bufferable from the IntelR XScaleTM core.
  This guarantees that all load/stores to the OCCDR are only of
  DWORD quantities.

Ensure that the OCCDR is so mapped.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-09 11:18:36 +00:00
Nicolas Pitre 72bc2b1ad6 [ARM] 5329/1: Feroceon: fix feroceon_l2_inv_range
Same fix as commit c7cf72dcadb: when 'start' and 'end' are less than a
cacheline apart and 'start' is unaligned we are done after cleaning and
invalidating the first cacheline.

Cc: <stable@kernel.org>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-08 23:08:54 +00:00
Russell King 878708f290 Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/xscaleiop 2008-11-06 18:04:23 +00:00
Dan Williams c7cf72dcad [ARM] xsc3: fix xsc3_l2_inv_range
When 'start' and 'end' are less than a cacheline apart and 'start' is
unaligned we are done after cleaning and invalidating the first
cacheline.  So check for (start < end) which will not walk off into
invalid address ranges when (start > end).

This issue was caught by drivers/dma/dmatest.

2.6.27 is susceptible.

Cc: <stable@kernel.org>
Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Lothar WaÃ<9f>mann <LW@KARO-electronics.de>
Cc: Lennert Buytenhek <buytenh@marvell.com>
Cc: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-11-06 10:48:29 -07:00
Russell King b1cce6b1b2 [ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like.  While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.

Tested on:
	OMAP34xx (ARMv7),
	OMAP24xx (ARMv6),
	OMAP16xx (ARM926T, ARMv5),
	PXA311 (Xscale3),
	PXA272 (Xscale),
	PXA255 (Xscale),
	IXP42x (Xscale),
	S3C2410 (ARM920T, ARMv4T),
	ARM720T (ARMv4T)
	StrongARM-110 (ARMv4)

Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-06 17:45:32 +00:00
Russell King ab4f2ee130 [ARM] fix naming of MODULE_START / MODULE_END
As of 73bdf0a60e, the kernel needs
to know where modules are located in the virtual address space.
On ARM, we located this region between MODULE_START and MODULE_END.
Unfortunately, everyone else calls it MODULES_VADDR and MODULES_END.
Update ARM to use the same naming, so is_vmalloc_or_module_addr()
can work properly.  Also update the comment on mm/vmalloc.c to
reflect that ARM also places modules in a separate region from the
vmalloc space.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-06 17:13:47 +00:00
Jon Callan 73b63efaac ARMv7: Add SMP initialisation to proc-v7.S
This patch adds the SMP/nAMP mode setting to __v7_setup and also sets
TTBR to shared page table walks if SMP is enabled. The PTWs are also
marked inner cacheable for both SMP and UP modes (setting this is fine
even if the CPU doesn't support the feature).

Signed-off-by: Jon Callan <Jon.Callan@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-11-06 13:23:09 +00:00
Catalin Marinas 6b07d7fea0 ARMv7: Do not set TTBR0 in __v7_setup
This register is set in __enable_mmu in the head.S file.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-11-06 13:23:08 +00:00
Catalin Marinas c30c2f99e1 ARMv7: Add extra barriers for flush_cache_all compressed/head.S
The flush_cache_all function on ARMv7 is implemented as a series of
cache operations by set/way. These are not guaranteed to be ordered with
previous memory accesses, requiring a DMB. This patch also adds barriers
for the TLB operations in compressed/head.S

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-11-06 13:23:07 +00:00
Dan Williams 6bee00dbbc [ARM] xsc3: revert writethrough memory-type encoding change
Commit 40df2d1d "[ARM] Update Xscale and Xscale3 PTE mappings" was
fingered by git-bisect for a boot failure on iop13xx.  The change made
L_PTE_MT_WRITETHROUGH mappings L2-uncacheable.  Russell points out that
this mapping is used for the vector page.  Given the regression, and the
fact this page is used often, restore the old behaviour.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-10-24 10:21:45 -07:00
Catalin Marinas f80a3bb252 [ARM] 5318/1: Swap the PRRR and NMRR values in proc-v7.S
A typo caused these values to be swapped leading to incorrect memory
type attributes.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-22 19:40:21 +01:00
Russell King f20e3b5fe7 Merge branch 'for-rmk' of git://git.android.com/kernel into devel 2008-10-22 19:34:09 +01:00
Brian Swetland 1637de0c9b [ARM] msm: rename ARCH_MSM7X00A to ARCH_MSM
The MSM architecture covers a wider family of chips than just the MSM7X00A.
Move to a more generic name, in perparation for supporting the specific
SoC variants as sub-architectures (ARCH_MSM7X01A, ARCH_MSM722X, etc).  This
gives us ARCH_MSM for the (many) common peripherals.

This also removes the unused/obsolete config item MSM7X00A_IDLE.

Signed-off-by: Brian Swetland <swetland@google.com>
2008-10-22 02:39:32 -07:00
Anders Grafström e4d2a5985a [ARM] 5310/1: Fix cache flush functions for ARMv4
ARMv4 (ARM720T) cache flush functions are broken in 2.6.19+ kernels.
The issue was introduced by commit f12d0d7c77
This patch corrects the CPU_CP15 ifdef statements so that they actually
do something.

Signed-off-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-17 13:44:27 +01:00
Russell King b6825d2df5 Merge branch 'omap-all' into devel
Conflicts:

	arch/arm/mach-omap2/gpmc.c
	arch/arm/mach-omap2/irq.c
2008-10-14 22:24:42 +01:00
Russell King 6defd90433 Merge branch 'for-rmk' of git://git.marvell.com/orion
Merge branch 'orion-devel' into devel
2008-10-09 21:33:07 +01:00
Russell King 6a4690c22f Merge branch 'ptebits' into devel
Conflicts:

	arch/arm/Kconfig
2008-10-09 21:31:56 +01:00
Syed Mohammed, Khasim 2885f00049 ARM: OMAP3: Add minimal Beagle board support
Add minimal Beagle board support. Based on earlier patches
by Syed Mohammed Khasim with some fixes from linux-omap tree.

Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 17:51:42 +03:00
Catalin Marinas 000b502592 [ARM] 5229/3: Replace some ARMv7 opcodes with the instruction name
These instructions were placed in the code directly as opcodes because
early compilers didn't support them. Toolchains supporting ARMv7
understand these instructions and the patch puts the mnemonics back.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-03 11:32:09 +01:00
Russell King b7a69ac303 [ARM] mm: finish ARM sparsemem support
... including some comments about the ordering required to bring
sparsemem up.  You have to repeatedly guess, test, reguess, try
again and again to work out what the right ordering is.  Many
hours later...

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 17:24:04 +01:00
Russell King d2a38ef9c1 [ARM] mm: provide helpers for accessing membanks
Provide helpers for getting physical addresses or pfns from the
meminfo array, and use them.  Move for_each_nodebank() to
asm/setup.h alongside the meminfo structure definition.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 17:22:02 +01:00
Russell King 5ec9407dd1 [ARM] Don't include asm/elf.h in asm code
asm code really wants asm/hwcap.h, so include that instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:10 +01:00
Russell King db5b716947 [ARM] Remove MT_DEVICE_IXP2000 and associated definitions
As of the previous commit, MT_DEVICE_IXP2000 encodes to the same
PTE bit encoding as MT_DEVICE, so it's now redundant.  Convert
MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:06 +01:00
Russell King 40df2d1d85 [ARM] Update Xscale and Xscale3 PTE mappings
Use 'shared device' mappings for devices, and use the standard
bit combinations for Xscale3.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:04 +01:00
Russell King 40d192b63d [ARM] remove 'prot_pte_ext' from memory type table
This member is now redundant; the memory type is encoded in the Linux
PTE bits.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:02 +01:00
Russell King 3f69c0c1af [ARM] Convert ARMv7 to use TEX remapping
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:01 +01:00
Russell King 639b0ae7f5 [ARM] Convert ARMv6 and ARMv7 to use new memory types
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:00 +01:00
Russell King 9e8b5199a7 [ARM] Convert Xscale and Xscale3 to use new memory types
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:40:58 +01:00
Russell King bb30f36f9b [ARM] Introduce new PTE memory type bits
Provide L_PTE_MT_xxx definitions to describe the memory types that we
use in Linux/ARM.  These definitions are carefully picked such that:

1. their LSBs match what is required for pre-ARMv6 CPUs.
2. they all have a unique encoding, including after modification
   by build_mem_type_table() (the result being that some have more
   than one combination.)

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:40:56 +01:00
Russell King da0916539d [ARM] Convert set_pte_ext implementions to macros
There are actually only four separate implementations of set_pte_ext.
Use assembler macros to insert code for these into the proc-*.S files.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:40:52 +01:00
Russell King 6c5da7aced [ARM] mm: move vmalloc= parsing to arch/arm/mm/mmu.c
There's no point scattering this around the tree, the parsing
of the parameter might as well live beside the code which uses
it.  That also means we can make vmalloc_reserve a static
variable.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30 21:34:16 +01:00
Russell King eca73214c9 [ARM] mm: move validation of membanks to one place
The newly introduced sanity_check_meminfo() function should be
used to collect all validation of the meminfo array, which we
have in bootmem_init().  Move it there.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30 21:34:15 +01:00
Nicolas Pitre 99c6bb390c [ARM] Feroceon: small cleanups to L2 cache code
- Make sure that coprocessor instructions for range ops are contiguous
  and not reordered.

- s/invalidate_and_disable_dcache/flush_and_disable_dcache/

- Don't re-enable I/D caches if they were not enabled initially.

- Change some masks to shifts for better generated code.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Lennert Buytenhek <buytenh@marvell.com>
2008-09-30 13:41:54 -04:00
Nicolas Pitre da46c79a54 [ARM] 5272/1: remove conditional compilation in show_pte()
The PTRS_PER_PMD != 1 condition can be evaluated with C code and
optimized at compile time.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30 16:41:04 +01:00
Russell King 309dbbabee [ARM] dma: don't touch cache on dma_*_for_cpu()
As per the dma_unmap_* calls, we don't touch the cache when a DMA
buffer transitions from device to CPU ownership.  Presently, no
problems have been identified with speculative cache prefetching
which in itself is a new feature in later architectures.  We may
have to revisit the DMA API later for these architectures anyway.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30 11:01:36 +01:00
Russell King 2638b4dbe7 [ARM] dma: Reduce to one dma_sync_sg_* implementation
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-29 10:40:16 +01:00
Russell King 01135d92c1 [ARM] dma: Reduce to one dma_map_sg()/dma_unmap_sg() implementation
No point having two of these; dma_map_page() can do all the work
for us.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25 23:39:24 +01:00
Ronen Shitrit 4360bb4192 [ARM] Kirkwood: add support for L2 cache WB/WT selection
Feroceon L2 cache can work in eighther write through or write back mode
on Kirkwood. Add the option to configure this mode according to Kconfig.

Signed-off-by: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-09-25 16:29:21 -04:00
Russell King afd1a321c4 [ARM] Update dma_map_sg()/dma_unmap_sg() API
Update the ARM DMA scatter gather APIs for the scatterlist changes.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25 20:48:45 +01:00
Russell King 0ddbccd118 [ARM] dma: rename consistent.c to dma-mapping.c
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25 15:59:19 +01:00
Lennert Buytenhek 1ad77a876d [ARM] 5241/1: provide ioremap_wc()
This patch provides an ARM implementation of ioremap_wc().

We use different page table attributes depending on which CPU we
are running on:

- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
  possible mapping types (CB=00/01/10/11).  We can't use any of the
  cached memory types (CB=10/11), since that breaks coherency with
  peripheral devices.  Both CB=00 and CB=01 are suitable for _wc, and
  CB=01 (Uncached/Buffered) allows the hardware more freedom than
  CB=00, so we'll use that.

  (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
  but isn't allowed to merge them, but there is no other mapping type
  we can use that allows the hardware to delay and merge stores, so
  we'll go with CB=01.)

- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
  difference that on these platforms, CB=01 actually _does_ allow
  merging stores.  (If you want noncoalescing bufferable behavior
  on Xscale v1/v2, you need to use XCB=101.)

- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
  mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
  in ARMv6 parlance).

  The ARMv6 ARM explicitly says that any accesses to Normal memory can
  be merged, which makes Normal memory more suitable for _wc mappings
  than Device or Strongly Ordered memory, as the latter two mapping
  types are guaranteed to maintain transaction number, size and order.
  We use the Uncached variety of Normal mappings for the same reason
  that we can't use C=1 mappings on ARMv5.

  The xsc3 Architecture Specification documents TEXCB=00100 as being
  Uncacheable and allowing coalescing of writes, which is also just
  what we need.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06 13:13:44 +01:00
Russell King fced80c735 [ARM] Convert asm/io.h to linux/io.h
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06 12:10:45 +01:00
Russell King 33fa9b1328 [ARM] Convert asm/uaccess.h to linux/uaccess.h
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06 11:35:55 +01:00
Russell King 5ed5fdf50c [ARM] clean up a load of old declarations
... some of which are now in linux/*.h headers.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06 11:23:30 +01:00
Russell King 012d1f4af1 [ARM] move initrd code from kernel/setup.c to mm/init.c
This quietens some sparse warnings about phys_initrd_start and
phys_initrd_size.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06 10:57:03 +01:00
Russell King 09d9bae064 [ARM] sparse: fix several warnings
arch/arm/kernel/process.c:270:6: warning: symbol 'show_fpregs' was not declared. Should it be static?

This function isn't used, so can be removed.

arch/arm/kernel/setup.c:532:9: warning: symbol 'len' shadows an earlier one
arch/arm/kernel/setup.c:524:6: originally declared here

A function containing two 'len's.

arch/arm/mm/fault-armv.c:188:13: warning: symbol 'check_writebuffer_bugs' was not declared. Should it be static?
arch/arm/mm/mmap.c:122:5: warning: symbol 'valid_phys_addr_range' was not declared. Should it be static?
arch/arm/mm/mmap.c:137:5: warning: symbol 'valid_mmap_phys_addr_range' was not declared. Should it be static?

Missing includes.

arch/arm/kernel/traps.c:71:77: warning: Using plain integer as NULL pointer
arch/arm/mm/ioremap.c:355:46: error: incompatible types in comparison expression (different address spaces)

Sillies.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-05 14:11:24 +01:00
Catalin Marinas 93ed397011 [ARM] 5227/1: Add the ENDPROC declarations to the .S files
This declaration specifies the "function" type and size for various
assembly functions, mainly needed for generating the correct branch
instructions in Thumb-2.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:34 +01:00
Russell King 46097c7dd8 [ARM] cachetype: move definitions to separate header
Rather than pollute asm/cacheflush.h with the cache type definitions,
move them to asm/cachetype.h, and include this new header where
necessary.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:24 +01:00
Russell King 0ba8b9b273 [ARM] cputype: separate definitions, use them
Add asm/cputype.h, moving functions and definitions from asm/system.h
there.  Convert all users of 'processor_id' to the more efficient
read_cpuid_id() function.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:23 +01:00
Russell King 8a5544c887 [ARM] add proc-macros.S include to proc-arm940 and proc-arm946
... otherwise these fail to build.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-12 19:54:08 +01:00
Lennert Buytenhek 60296c71f6 [ARM] prevent crashing when too much RAM installed
This patch will truncate and/or ignore memory banks if their kernel
direct mappings would (partially) overlap with the vmalloc area or
the mappings between the vmalloc area and the address space top, to
prevent crashing during early boot if there happens to be more RAM
installed than we are expecting.

Since the start of the vmalloc area is not at a fixed address (but
the vmalloc end address is, via the per-platform VMALLOC_END define),
a default area of 128M is reserved for vmalloc mappings, which can
be shrunk or enlarged by passing an appropriate vmalloc= command line
option as it is done on x86.

On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000,
two 512M RAM banks and vmalloc=128M (the default), this patch gives:

	Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap).
	Memory: 512MB 352MB = 864MB total

On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000,
two 256M RAM banks and vmalloc=768M, this patch gives:

	Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap).
	Ignoring RAM at 10000000-1fffffff (vmalloc region overlap).

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Riku Voipio <riku.voipio@iki.fi>
2008-08-09 15:38:15 +02:00
Lennert Buytenhek 6f088f1d21 [ARM] Move include/asm-arm/plat-orion to arch/arm/plat-orion/include/plat
This patch performs the equivalent include directory shuffle for
plat-orion, and fixes up all users.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-09 13:44:58 +02:00
Russell King a09e64fbc0 [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-07 09:55:48 +01:00
Russell King 4fb8af10d0 Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixes 2008-08-07 09:55:03 +01:00
Russell King be50972935 [ARM] Remove asm/hardware.h, use asm/arch/hardware.h instead
Remove includes of asm/hardware.h in addition to asm/arch/hardware.h.
Then, since asm/hardware.h only exists to include asm/arch/hardware.h,
update everything to directly include asm/arch/hardware.h and remove
asm/hardware.h.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-07 09:40:08 +01:00
Linus Torvalds 7e31aa11fc Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 5182/1: pxa: Fix pcm990 compilation
  [ARM] Fix explicit asm(-arm)?/arch-foo references
  [ARM] move include/asm-arm to arch/arm/include/asm
  [ARM] Remove explicit dependency for misc.o from compressed/Makefile
  [ARM] initrd: claim initrd memory exclusively
  [ARM] pxa: add support for L2 outer cache on XScale3 (attempt 2)
  [ARM] 5180/1: at91: Fix at91_nand -> atmel_nand rename fallout
  [ARM] add Sascha Hauer as Freescale i.MX Maintainer
  [ARM] i.MX: add missing clock functions exports
  [ARM] i.MX: remove set_imx_fb_info() export
  [ARM] mx1ads: make mmc platform data available for modules
  [ARM] mx2: add missing Kconfig dependency
2008-08-03 10:39:02 -07:00
Russell King 4baa992243 [ARM] move include/asm-arm to arch/arm/include/asm
Move platform independent header files to arch/arm/include/asm, leaving
those in asm/arch* and asm/plat* alone.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-02 21:32:35 +01:00
Russell King b962a286e5 [ARM] initrd: claim initrd memory exclusively
Claim the initrd memory exclusively, and order other memory
reservations beforehand.  This allows us to determine whether
the initrd memory was overwritten, and disable the initrd in
that case.

This avoids a 'bad page state' bug.

Tested-by: Ralph Siemsen <ralphs@netwinder.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-07-30 21:24:56 +01:00
Eric Miao 905a09d57a [ARM] pxa: add support for L2 outer cache on XScale3 (attempt 2)
(20072fd0c9 lost most of its changes
somehow, came from a mbox archive applied with git-am.  No idea
what happened.  This puts back the missing bits.  --rmk)

The initial patch from Lothar, and Lennert make it into a cleaner
one, modified and tested on PXA320 by Eric Miao.

This patch moves the L2 cache operations out of proc-xsc3.S into
dedicated outer cache support code.

CACHE_XSC3L2 can be deselected so no L2 cache specific code will be
linked in, and that L2 enable bit will not be set, this applies to
the following cases:

    a. _only_ PXA300/PXA310 support included and no L2 cache wanted
    b. PXA320 support included, but want L2 be disabled

So the enabling of L2 depends on two things:

    - CACHE_XSC3L2 is selected
    - and L2 cache is present

Where the latter is only a safeguard (previous testing shows it works
OK even when this bit is turned on).

IXP series of processors with XScale3 cannot disable L2 cache for the
moment since they depend on the L2 cache for its coherent memory, so
IXP may always select CACHE_XSC3L2.

Other L2 relevant bits are always turned on (i.e. the original code
enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side
effects. Specifically, these bits are:

   - OC bits in TTBASE register (table walk outer cache attributes)
   - LLR Outer Cache Attributes (OC) in Auxiliary Control Register

Signed-off-by: Lothar WaÃ<9f>mann <LW@KARO-electronics.de>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-07-28 23:13:09 +01:00
Ingo Molnar cb28a1bbdb Merge branch 'linus' into core/generic-dma-coherent
Conflicts:

	arch/x86/Kconfig

Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-29 00:07:55 +02:00
Sascha Hauer 221d62c188 [ARM] mx2: add missing Kconfig dependency
It seems this small label was lost in the last merge. Without it
no CPU type is selected for the MX2 family of processors. And a build
will fail badly...

Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2008-07-28 11:23:30 +02:00
Russell King 53cdb27a93 [ARM] Fix shared mmap when more than two maps of the same file exist
The shared mmap code works fine for the test case, which only checked
for two shared maps of the same file.  However, three shared maps
result in one mapping remaining cached, resulting in stale data being
visible via that mapping.  Fix this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-07-27 10:35:54 +01:00
Johannes Weiner 9109fb7b35 mm: drop unneeded pgdat argument from free_area_init_node()
free_area_init_node() gets passed in the node id as well as the node
descriptor.  This is redundant as the function can trivially get the node
descriptor itself by means of NODE_DATA() and the node's id.

I checked all the users and NODE_DATA() seems to be usable everywhere
from where this function is called.

Signed-off-by: Johannes Weiner <hannes@saeurebad.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-24 10:47:16 -07:00
Johannes Weiner b61bfa3c46 mm: move bootmem descriptors definition to a single place
There are a lot of places that define either a single bootmem descriptor or an
array of them.  Use only one central array with MAX_NUMNODES items instead.

Signed-off-by: Johannes Weiner <hannes@saeurebad.de>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Kyle McMartin <kyle@parisc-linux.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: David S. Miller <davem@davemloft.net>
Cc: Yinghai Lu <yhlu.kernel@gmail.com>
Cc: Christoph Lameter <cl@linux-foundation.org>
Cc: Mel Gorman <mel@csn.ul.ie>
Cc: Andy Whitcroft <apw@shadowen.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-07-24 10:47:14 -07:00
Dmitry Baryshkov 1fe532685a ARM: support generic per-device coherent dma mem
Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-18 21:14:01 +02:00
Russell King 044e5f45e4 Merge branch 'pxa' into devel
Conflicts:

	arch/arm/configs/em_x270_defconfig
	arch/arm/configs/xm_x270_defconfig
2008-07-13 12:05:49 +01:00
Russell King f0006314d3 Merge branch 'imx' into devel
Conflicts:

	arch/arm/mm/Kconfig
2008-07-10 16:41:50 +01:00
Russell King a177ba3b7a Merge branches 'at91', 'dyntick', 'ep93xx', 'iop', 'ixp', 'misc', 'orion', 'omap-reviewed', 'rpc', 'rtc' and 's3c' into devel 2008-07-10 16:38:50 +01:00
sedji gaouaou 613526677a [ARM] 5130/4: Support for the at91sam9g20
Support for the at91sam9g20 : Atmel 400Mhz ARM 926ej-s SOC.

AT91sam9g20 is an evolution of the at91sam9260 with a faster clock
speed.
We created a new board for this device but based the chip support
directly on 9260 files with little updates.
Here is the chip page on Atmel wabsite:
http://atmel.com/dyn/products/product_card.asp?part_id=4337

Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
Signed-off-by: Justin Waters <justin.waters@timesys.com>
Acked-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-07-10 12:13:47 +01:00
Eric Miao 20072fd0c9 [ARM] pxa: add support for L2 outer cache on XScale3
The initial patch from Lothar, and Lennert make it into a cleaner
one, modified and tested on PXA320 by Eric Miao.

This patch moves the L2 cache operations out of proc-xsc3.S into
dedicated outer cache support code.

CACHE_XSC3L2 can be deselected so no L2 cache specific code will be
linked in, and that L2 enable bit will not be set, this applies to
the following cases:

    a. _only_ PXA300/PXA310 support included and no L2 cache wanted
    b. PXA320 support included, but want L2 be disabled

So the enabling of L2 depends on two things:

    - CACHE_XSC3L2 is selected
    - and L2 cache is present

Where the latter is only a safeguard (previous testing shows it works
OK even when this bit is turned on).

IXP series of processors with XScale3 cannot disable L2 cache for the
moment since they depend on the L2 cache for its coherent memory, so
IXP may always select CACHE_XSC3L2.

Other L2 relevant bits are always turned on (i.e. the original code
enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side
effects. Specifically, these bits are:

   - OC bits in TTBASE register (table walk outer cache attributes)
   - LLR Outer Cache Attributes (OC) in Auxiliary Control Register

Signed-off-by: Lothar WaÃ<9f>mann <LW@KARO-electronics.de>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-07-09 21:38:33 +01:00
Saeed Bishara 188237e28d [ARM] Feroceon: don't disable BPU on boot
On Feroceon platforms that have a branch prediction unit, bit 11 of the
cp15 control register controls the BPU.  This patch keeps the old value
of this bit instead of always clearing it.

Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-07-07 18:38:24 -04:00
Juergen Beisert 1bd55a436f i.MX2 family: Add basic mach support
This patch adds basic mach support for the mx2 processor family, based
on the original freescale code and adapted to mainline kernel coding
style.

This part adds the global build only.

Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
2008-07-05 10:03:02 +02:00
Catalin Marinas 826cbdaff2 [ARM] 5092/1: Fix the I-cache invalidation on ARMv6 and later CPUs
This patch adds the I-cache invalidation in update_mmu_cache if the
corresponding vma is marked as executable. It also invalidates the
I-cache if a thread migrates to a CPU it never ran on.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-07-03 16:39:57 +01:00
Stanislav Samsonov 794d15b25d [ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.

This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.

Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:10 +02:00
Lennert Buytenhek 0a17c7bc0b [ARM] Feroceon: 88fr571-vd support
Add support for the Feroceon 88fr571-vd CPU core as found in e.g.
the Marvell Discovery Duo family of ARM SoCs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:08 +02:00
Saeed Bishara 651c74c74b [ARM] add Marvell Kirkwood (88F6000) SoC support
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.

This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.

Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:06 +02:00
Lennert Buytenhek 9c2af6c57c [ARM] Feroceon: 88fr131 support
Add support for the Shiva 88fr131 CPU core as found in e.g. the
Marvell Kirkwood family of ARM SoCs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:05 +02:00
Lennert Buytenhek 99c6dc117d [ARM] Feroceon: L2 cache support
This patch adds support for the unified Feroceon L2 cache controller
as found in e.g. the Marvell Kirkwood and Marvell Discovery Duo
families of ARM SoCs.

Note that:

- Page table walks are outer uncacheable on Kirkwood and Discovery
  Duo, since the ARMv5 spec provides no way to indicate outer
  cacheability of page table walks (specifying it in TTBR[4:3] is
  an ARMv6+ feature).

  This requires adding L2 cache clean instructions to
  proc-feroceon.S (dcache_clean_area(), set_pte()) as well as to
  tlbflush.h ({flush,clean}_pmd_entry()).  The latter case is handled
  by defining a new TLB type (TLB_FEROCEON) which is almost identical
  to the v4wbi one but provides a TLB_L2CLEAN_FR flag.

- The Feroceon L2 cache controller supports L2 range (i.e. 'clean L2
  range by MVA' and 'invalidate L2 range by MVA') operations, and this
  patch uses those range operations for all Linux outer cache
  operations, as they are faster than the regular per-line operations.

  L2 range operations are not interruptible on this hardware, which
  avoids potential livelock issues, but can be bad for interrupt
  latency, so there is a compile-time tunable (MAX_RANGE_SIZE) which
  allows you to select the maximum range size to operate on at once.
  (Valid range is between one cache line and one 4KiB page, and must
  be a multiple of the line size.)

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:04 +02:00
Stanislav Samsonov 836a8051d5 [ARM] Feroceon: L1 cache range operation support
This patch adds support for the L1 D cache range operations that
are supported by the Marvell Discovery Duo and Marvell Kirkwood
ARM SoCs.

Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:03 +02:00
Lennert Buytenhek 777f9bebad [ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.

This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:02 +02:00
Ke Wei ab6d15d506 [ARM] Feroceon: allow more old Feroceon IDs
There are a couple more Feroceon-based SoCs out in the field that use
different Variant and Architecture fields in their Main ID registers
-- this patch tweaks the processor match/mask in proc-feroceon.S to
catch those SoCs as well.

Signed-off-by: Ke Wei <kewei@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:45:00 +02:00
Nicolas Pitre 6c386e58aa [ARM] Feroceon: speed up flushing of the entire cache
Flushing the L1 D cache with a test/clean/invalidate loop is very
easy in software, but it is not the quickest way of doing it, as
there is a lot of overhead involved in re-scanning the cache from
the beginning every time we hit a dirty line.

This patch makes proc-feroceon.S use "clean+invalidate by set/way"
loops according to possible cache configuration of Feroceon CPUs
(either direct-mapped or 4-way set associative).

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 22:44:58 +02:00
Lennert Buytenhek ee0dd84005 [ARM] Feroceon: annotate 88fr531-vd CPU entries
Annotate the entries for the 88fr531-vd CPU core in
arch/arm/boot/compressed/head.S and arch/arm/mm/proc-feroceon.S
with the full name of the core.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <linux@arm.linux.org.uk>
2008-06-22 22:44:42 +02:00
Lennert Buytenhek e7068ad337 [ARM] Orion: fix various whitespace and coding style issues
More cosmetic cleanup:
- Replace 8-space indents by proper tab indents.
- In structure initialisers, use a trailing comma for every member.
- Collapse "},\n{" in structure initialiers to "}, {".

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <linux@arm.linux.org.uk>
2008-06-22 22:44:39 +02:00
Lennert Buytenhek b3a8b751c1 [ARM] 5034/1: fix arm{925,926,940,946} dma_flush_range() in WT mode
The CPU's dma_flush_range() operation needs to clean+invalidate the
given memory area if the cache is in writeback mode, or do just the
invalidate part if the cache is in writethrough mode, but the current
proc-arm{925,926,940,946} (incorrectly) do a cache clean in the
latter case.  This patch fixes that.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-05-17 22:55:14 +01:00
Aneesh Kumar K.V 3653f3abe3 arm: Export empty_zero_page for ZERO_PAGE usage in modules.
ext4 uses ZERO_PAGE(0) to zero out blocks.  We need to export
different symbols in different arches for the usage of ZERO_PAGE
in modules.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: "Theodore Ts'o" <tytso@mit.edu>
2008-04-29 08:11:12 -04:00
Linus Torvalds d973664992 Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (26 commits)
  [ARM] pxa: fix 1c104e0e4f
  [ARM] serial: s3c2410: platform_get_irq() may return signed unnoticed
  [ARM] am79c961a: platform_get_irq() may return signed unnoticed
  [ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page()
  [ARM] Feroceon: fix function alignment in proc-feroceon.S
  [ARM] Orion: catch a couple more alternative spellings of PCIe
  [ARM] Orion: fix orion-ehci platform resource end addresses
  [ARM] Orion: fix ->map_irq() PCIe bus number check
  [ARM] Orion: fix ioremap() optimization
  [ARM] feroceon: remove CONFIG_CPU_CACHE_ROUND_ROBIN check
  [ARM] feroceon: remove CONFIG_CPU_DCACHE_WRITETHROUGH check
  kprobes/arm: fix decoding of arithmetic immediate instructions
  kprobes/arm: fix cache flush address for instruction stub
  [ARM] 5022/1: Race in ARM MMCI PL18x driver, V2
  [ARM] 5021/1: at91: buildfix for sam9263 + PM
  [ARM] 5018/1: RealView: Fix the ARM11MPCore Oprofile compilation
  [ARM] 5016/1: AT91: typo in mci configuration for at91cap at91sam9263
  [ARM] 5017/1: pxa3xx: Report unsupported wakeup sources in pxa3xx_set_wake()
  [ARM] 5020/1: magician: remove __devinit marker from pasic3_leds_info
  [ARM] 5014/1: Cleanup reset state before entering suspend or resetting.
  ...
2008-04-29 15:18:06 -07:00
Benjamin Herrenschmidt b70d3a2c59 iomap: fix 64 bits resources on 32 bits
Almost all implementations of pci_iomap() in the kernel, including the generic
lib/iomap.c one, copies the content of a struct resource into unsigned long's
which will break on 32 bits platforms with 64 bits resources.

This fixes all definitions of pci_iomap() to use resource_size_t.  I also
"fixed" the 64bits arch for consistency.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: <linux-arch@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-04-29 08:06:02 -07:00
Lennert Buytenhek 0ed1507183 [ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page()
This patch implements a set of Feroceon-specific
{copy,clear}_user_page() routines that perform more optimally than
the generic implementations.  This also deals with write-allocate
caches (Feroceon can run L1 D in WA mode) which otherwise prevents
Linux from booting.

[nico: optimized the code even further]

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Sylver Bruneau <sylver.bruneau@googlemail.com>
Tested-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-04-28 16:06:51 -04:00
Nicolas Pitre 6b29e681aa [ARM] Feroceon: fix function alignment in proc-feroceon.S
One overzealous .align 10 fixed, and a few .align5 added.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-04-28 16:02:36 -04:00
Lennert Buytenhek c5a1e8f709 [ARM] feroceon: remove CONFIG_CPU_CACHE_ROUND_ROBIN check
Since the Feroceon cache replacement policy is always pseudorandom
(and the relevant control register bit is ignored), remove the
CONFIG_CPU_CACHE_ROUND_ROBIN check from proc-feroceon.S.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-04-28 15:55:57 -04:00
Lennert Buytenhek a7039bd6da [ARM] feroceon: remove CONFIG_CPU_DCACHE_WRITETHROUGH check
Since the Feroceon doesn't have a global WT override bit like
ARM926 does, remove all code relating to this mode of operation
from proc-feroceon.S.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-04-28 15:55:28 -04:00
Catalin Marinas 4a1fd556c1 [ARM] fix 48d7927bdf
The proc-*.S files have the _prefetch_abort pointer placed at the end
of the processor structure but the cpu-multi32.h defines it in the
second position. The patch also fixes the support for XSC3 and the
MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-04-24 10:06:45 +01:00
Russell King d1964dab60 Merge branches 'arm', 'at91', 'ep93xx', 'iop', 'ks8695', 'misc', 'mxc', 'ns9x', 'orion', 'pxa', 'sa1100', 's3c' and 'sparsemem' into devel 2008-04-19 17:17:25 +01:00
Johannes Weiner c48b2e90ae [ARM] remove redundant display of free swap space in show_mem()
Signed-off-by: Johannes Weiner <hannes@saeurebad.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-04-19 11:28:10 +01:00
Catalin Marinas ba9279519b Allow the L2X0 outer cache support to be configurable
By default, this option was selected by the platform Kconfig. This
patch adds "depends on" to L2X0 so that it can be enabled/disabled
manually.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:17 +01:00
Bahadir Balban bc02c58bd1 RealView: Add the configuration and build changes for PB1176
This patch enables the building of Linux for the PB1176 platform.

Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:16 +01:00
Bahadir Balban 78fdcb4287 RealView: Enable the configuration options for PB11MPCore
This patch adds the PB11MPCore support to the corresponding Kconfig
and Makefile to enable building.

Signed-off-by: Bahadir Balban <bahadir.balban@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:14 +01:00
Catalin Marinas 41267e208e RealView: Allow ARMv7 support for RealView/EB
This patch changes the CPU_V7 configuration dependency to allow
MACH_REALVIEW_EB.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:12 +01:00
Catalin Marinas b7b0ba942f RealView: Move the SCU initialisation out of __v6_setup
This patch moves the SCU initialisation from __v6_setup to the
smp_prepare_cpus() function as it relies on platform-specific
settings. Changes to get_core_count() are mainly for allowing cleaner
code with the upcoming PB11MPCore patches.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:08 +01:00
Paul Brook 48d7927bdf Add a prefetch abort handler
This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with some renaming by Catalin Marinas.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:07 +01:00
Catalin Marinas d7f864be83 ARMv7: Add support for the ThumbEE state saving/restoring
This patch adds the detection and handling of the ThumbEE extension on
ARMv7 CPUs.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2008-04-18 22:43:06 +01:00
Lennert Buytenhek 9dd0b194bf Orion: orion -> orion5x rename
Do a global s/orion/orion5x/ of the Orion 5x-specific bits (i.e.
not the plat-orion bits.)

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-03-27 14:51:41 -04:00
Arnaud Patard 391c569daa [ARM] 4864/1: Enable write buffer coalescing on IOP
Some bootloaders are disabling write buffer coalescing. Enable it back
under linux.

Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-03-20 15:59:30 +00:00
Uwe Kleine-König 0c82d83cb0 [ARM] Fix freeing of page tables for ARM in free_pgd_slow
Since 2f569af (CONFIG_HIGHPTE vs. sub-page page tables.) pte_free() calls
pte_lock_deinit() and dec_zone_page_state().  So free_pgd_slow must not call
the latter two when calling the first.

Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-03-01 20:23:57 +00:00
Alexandre Rusev 9ae3ae0beb [ARM] 4839/1: fixes kernel Oops in /dev/mem device driver for memory map with PHYS_OFF
"cat /dev/mem" may cause kernel Oops for boards with PHYS_OFFSET != 0
because character device is mapped to addresses starting from zero
and there is no protection against such situation.
Patch just add this.

Signed-off-by: Alexandre Rusev <arusev@ru.mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-02-29 22:47:20 +00:00
Bernhard Walle 72a7fe3967 Introduce flags for reserve_bootmem()
This patchset adds a flags variable to reserve_bootmem() and uses the
BOOTMEM_EXCLUSIVE flag in crashkernel reservation code to detect collisions
between crashkernel area and already used memory.

This patch:

Change the reserve_bootmem() function to accept a new flag BOOTMEM_EXCLUSIVE.
If that flag is set, the function returns with -EBUSY if the memory already
has been reserved in the past.  This is to avoid conflicts.

Because that code runs before SMP initialisation, there's no race condition
inside reserve_bootmem_core().

[akpm@linux-foundation.org: coding-style fixes]
[akpm@linux-foundation.org: fix powerpc build]
Signed-off-by: Bernhard Walle <bwalle@suse.de>
Cc: <linux-arch@vger.kernel.org>
Cc: "Eric W. Biederman" <ebiederm@xmission.com>
Cc: Vivek Goyal <vgoyal@in.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-02-07 08:42:25 -08:00
Benjamin Herrenschmidt 5e5419734c add mm argument to pte/pmd/pud/pgd_free
(with Martin Schwidefsky <schwidefsky@de.ibm.com>)

The pgd/pud/pmd/pte page table allocation functions get a mm_struct pointer as
first argument.  The free functions do not get the mm_struct argument.  This
is 1) asymmetrical and 2) to do mm related page table allocations the mm
argument is needed on the free function as well.

[kamalesh@linux.vnet.ibm.com: i386 fix]
[akpm@linux-foundation.org: coding-syle fixes]
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: <linux-arch@vger.kernel.org>
Signed-off-by: Kamalesh Babulal <kamalesh@linux.vnet.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-02-05 09:44:18 -08:00
Russell King c00d4ffdba Merge branch 'orion' into devel
* orion: (26 commits)
  [ARM] Orion: implement power-off method for QNAP TS-109/209
  [ARM] Orion: add support for QNAP TS-109/TS-209
  [ARM] Orion: I2C support
  [I2C] i2c-mv64xxx: Don't set i2c_adapter.retries
  [I2C] Split mv643xx I2C platform support
  [ARM] Orion: enable CONFIG_RTC_DRV_M41T80 for D-Link DNS-323
  [ARM] Orion defconfig
  [ARM] Orion: add support for Orion/MV88F5181 based D-Link DNS-323
  [ARM] Orion: MV88F5181 support bits
  [ARM] Orion: Buffalo/Revogear Kurobox Pro support
  [ARM] OrionNAS RD board support
  [ARM] Orion: support for Marvell Orion-2 (88F5281) Development Board
  [ARM] Orion: common platform setup for Gigabit Ethernet port
  [ARM] Orion: platform device registration for UART, USB and NAND
  [ARM] Orion: system timer support
  [ARM] Orion edge GPIO IRQ support
  [ARM] Orion: IRQ support
  [ARM] Orion: provide GPIO method for enabling hardware assisted blinking
  [ARM] Orion: GPIO support
  [ARM] Orion: programable address map support
  ...

Conflicts:

	arch/arm/Kconfig
	arch/arm/Makefile

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-28 13:21:30 +00:00
Russell King d0d42df2a4 Merge branches 'at91', 'ep93xx', 'iop', 'kprobes', 'ks8695', 'misc', 'msm', 's3c2410', 'sa1100' and 'vfp' into devel
* at91: (24 commits)
  [ARM] 4615/4: sam926[13]ek buttons updated
  [ARM] 4765/1: [AT91] AT91CAP9A-DK board support
  [ARM] 4764/1: [AT91] AT91CAP9 core support
  [ARM] 4738/1: at91sam9261: Remove udc pullup enabling in board initialisation
  [ARM] 4761/1: [AT91] Board-support for NEW_LEDs
  [ARM] 4760/1: [AT91] SPI CS0 errata on AT91RM9200
  [ARM] 4759/1: [AT91] Buttons on CSB300
  [ARM] 4758/1: [AT91] LEDs
  [ARM] 4757/1: [AT91] UART initialization
  [ARM] 4756/1: [AT91] Makefile cleanup
  [ARM] 4755/1: [AT91] NAND update
  [ARM] 4754/1: [AT91] SSC library support
  [ARM] 4753/1: [AT91] Use DMA_BIT_MASK
  [ARM] 4752/1: [AT91] RTT, RTC and WDT peripherals on SAM9
  [ARM] 4751/1: [AT91] ISI peripheral on SAM9263
  [ARM] 4750/1: [AT91] STN LCD displays on SAM9261
  [ARM] 4734/1: at91sam9263ek: include IRQ for Ethernet PHY
  [ARM] 4646/1: AT91: configurable HZ, default to 128
  [ARM] 4688/1: at91: speed-up irq processing
  [ARM] 4657/1: AT91: Header definition update
  ...

* ep93xx:
  [ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations
  [ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type
  [ARM] 4669/1: ep93xx: simplify GPIO code and cleanups
  [ARM] 4668/1: ep93xx: implement new GPIO API

* iop:
  [ARM] 4770/1: GLAN Tank: correct physmap_flash_data width field
  [ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device
  [ARM] 4708/1: iop: update defconfigs for 2.6.24

* kprobes:
  ARM kprobes: let's enable it
  ARM kprobes: special hook for the kprobes breakpoint handler
  ARM kprobes: prevent some functions involved with kprobes from being probed
  ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack
  ARM kprobes: add the kprobes hook to the page fault handler
  ARM kprobes: core code
  ARM kprobes: instruction single-stepping support

* ks8695:
  [ARM] 4603/1: KS8695: debugfs interface to view pin state
  [ARM] 4601/1: KS8695: PCI support

* misc:
  [ARM] remove duplicate includes
  [ARM] CONFIG_DEBUG_STACK_USAGE
  [ARM] 4689/1: small comment wrap fix
  [ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix
  [ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h
  [ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS
  [SERIAL] 21285: Report baud rate back via termios
  [ARM] Remove pointless casts from void pointers,
  [ARM] Misc minor interrupt handler cleanups
  [ARM] Remove at91_lcdc.h
  [ARM] ARRAY_SIZE() cleanup
  [ARM] Update mach-types

* msm:
  [ARM] msm: dma support for MSM7X00A
  [ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A)
  [ARM] msm: irq and timer support for ARCH_MSM7X00A
  [ARM] msm: core platform support for ARCH_MSM7X00A

* s3c2410: (33 commits)
  [ARM] 4795/1: S3C244X: Add armclk and setparent call
  [ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code
  [ARM] 4793/1: S3C24XX: Add IRQ->GPIO pin mapping function
  [ARM] 4792/1: S3C24XX: Remove warnings from debug-macro.S
  [ARM] 4791/1: S3C2412: Make fclk a parent of msysclk
  [ARM] 4790/1: S3C2412: Fix parent selection for msysclk.
  [ARM] 4789/1: S3C2412: Add missing CLKDIVN register values
  [ARM] 4788/1: S3C24XX: Fix paramet to s3c2410_dma_ctrl if S3C2410_DMAF_AUTOSTART used.
  [ARM] 4787/1: S3C24XX: s3c2410_dma_request() should return the allocated channel number
  [ARM] 4786/1: S3C2412: Add SPI FIFO controll constants
  [ARM] 4785/1: S3C24XX: Add _SHIFT definitions for S3C2410_BANKCON registers
  [ARM] 4784/1: S3C24XX: Fix GPIO restore glitches
  [ARM] 4783/1: S3C24XX: Add s3c2410_gpio_getpull()
  [ARM] 4782/1: S3C24XX: Define FIQ_START for any FIQ users
  [ARM] 4781/1: S3C24XX: DMA suspend and resume support
  [ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX
  [ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call
  [ARM] 4778/1: S3C2412: Add armclk and init from DVS state
  [ARM] 4777/1: S3C24XX: Ensure clk_set_rate() checks the set_rate method for the clk
  [ARM] 4775/1: s3c2410: fix compilation error if only s3c2442 cpu is selected
  ...

* sa1100:
  [ARM] sa1100: add clock source support

* vfp:
  [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support
  [ARM] 4583/1: ARMv7: Add VFPv3 support
  [ARM] 4582/2: Add support for the common VFP subarchitecture
2008-01-28 13:21:21 +00:00
Nicolas Pitre 785d3cd286 ARM kprobes: prevent some functions involved with kprobes from being probed
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-01-26 15:25:17 +00:00
Nicolas Pitre 25ce1dd71b ARM kprobes: add the kprobes hook to the page fault handler
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2008-01-26 15:25:16 +00:00
Tzachi Perelstein d910a0aa21 [ARM] Feroceon: support old cores with ARM926 ID
This enables the usage of some old Feroceon cores
for which the CPU ID is equal to the ARM926 ID.
Relevant for Feroceon-1850 and old Feroceon-2850.

Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-26 15:03:41 +00:00
Assaf Hoffman e50d64097b [ARM] Marvell Feroceon CPU core support
The Feroceon is a family of independent ARMv5TE compliant CPU core
implementations, supporting a variable depth pipeline and out-of-order
execution.  The Feroceon is configurable with VFP support, and the
later models in the series are superscalar with up to two instructions
per clock cycle.

This patch adds the initial low-level cache/TLB handling for this core.

Signed-off-by: Assaf Hoffman <hoffman@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-26 15:03:38 +00:00
Andrew Victor 2b3b3516b6 [ARM] 4764/1: [AT91] AT91CAP9 core support
Add support for Atmel's AT91CAP9 Customizable Microcontroller family.
  <http://www.atmel.com/products/AT91CAP/Default.asp>

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-01-26 15:01:13 +00:00
Brian Swetland 3042102a28 [ARM] msm: core platform support for ARCH_MSM7X00A
- core header files for arch-msm
- Kconfig and Makefiles to enable ARCH_MSM7X00A builds
- MSM7X00A specific arch_idle
- peripheral iomap and irq number definitions

Signed-off-by: Brian Swetland <swetland@google.com>
2008-01-26 14:39:14 +00:00
Russell King 6d6a54d1e4 [ARM] remove useless setting of VM_RESERVED
remap_pfn_range() takes care of setting the appropriate VM_*
flags itself; there's no need for callers of remap_pfn_range()
to set VM_RESERVED before it is called.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-11-11 10:55:25 +00:00
Russell King 0214f9221a [ARM] Fix FIQ issue with ARM926
Jon Eibertzon writes:
> We have noticed that the I-cache is disabled while waiting for
> interrupt in cpu_arm926_do_idle in arch/arm/mm/proc-arm926.S
> and we are curious to know why, because this causes us a great
> performance hit when executing in FIQ-handlers. Is it assumed
> here that every individual FIQ-handler re-enables the I-cache?

The I-cache disable is an errata workaround, so the solution is to
disable FIQs across the section with the I-cache disabled.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-31 15:21:40 +00:00
Alexey Dobriyan 19c5870c0e Use helpers to obtain task pid in printks (arch code)
One of the easiest things to isolate is the pid printed in kernel log.
There was a patch, that made this for arch-independent code, this one makes
so for arch/xxx files.

It took some time to cross-compile it, but hopefully these are all the
printks in arch code.

Signed-off-by: Alexey Dobriyan <adobriyan@openvz.org>
Signed-off-by: Pavel Emelyanov <xemul@openvz.org>
Cc: <linux-arch@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-19 11:53:43 -07:00
Serge E. Hallyn b460cbc581 pid namespaces: define is_global_init() and is_container_init()
is_init() is an ambiguous name for the pid==1 check.  Split it into
is_global_init() and is_container_init().

A cgroup init has it's tsk->pid == 1.

A global init also has it's tsk->pid == 1 and it's active pid namespace
is the init_pid_ns.  But rather than check the active pid namespace,
compare the task structure with 'init_pid_ns.child_reaper', which is
initialized during boot to the /sbin/init process and never changes.

Changelog:

	2.6.22-rc4-mm2-pidns1:
	- Use 'init_pid_ns.child_reaper' to determine if a given task is the
	  global init (/sbin/init) process. This would improve performance
	  and remove dependence on the task_pid().

	2.6.21-mm2-pidns2:

	- [Sukadev Bhattiprolu] Changed is_container_init() calls in {powerpc,
	  ppc,avr32}/traps.c for the _exception() call to is_global_init().
	  This way, we kill only the cgroup if the cgroup's init has a
	  bug rather than force a kernel panic.

[akpm@linux-foundation.org: fix comment]
[sukadev@us.ibm.com: Use is_global_init() in arch/m32r/mm/fault.c]
[bunk@stusta.de: kernel/pid.c: remove unused exports]
[sukadev@us.ibm.com: Fix capability.c to work with threaded init]
Signed-off-by: Serge E. Hallyn <serue@us.ibm.com>
Signed-off-by: Sukadev Bhattiprolu <sukadev@us.ibm.com>
Acked-by: Pavel Emelianov <xemul@openvz.org>
Cc: Eric W. Biederman <ebiederm@xmission.com>
Cc: Cedric Le Goater <clg@fr.ibm.com>
Cc: Dave Hansen <haveblue@us.ibm.com>
Cc: Herbert Poetzel <herbert@13thfloor.at>
Cc: Kirill Korotaev <dev@sw.ru>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-19 11:53:37 -07:00
Will Schmidt dcca2bde4f During VM oom condition, kill all threads in process group
We have had complaints where a threaded application is left in a bad state
after one of it's threads is killed when we hit a VM: out_of_memory
condition.

Killing just one of the process threads can leave the application in a bad
state, whereas killing the entire process group would allow for the
application to restart, or be otherwise handled, and makes it very obvious
that something has gone wrong.

This change allows the entire process group to be taken down, rather
than just the one thread.

Signed-off-by: Will Schmidt <will_schmidt@vnet.ibm.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Ian Molton <spyro@f2s.com>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Cc: Mikael Starvik <starvik@axis.com>
Cc: David Howells <dhowells@redhat.com>
Cc: Andi Kleen <ak@suse.de>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Roman Zippel <zippel@linux-m68k.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Matthew Wilcox <willy@debian.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
Cc: Richard Curnow <rc@rc0.org.uk>
Cc: William Lee Irwin III <wli@holomorphy.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-16 09:42:52 -07:00