Commit Graph

1641 Commits

Author SHA1 Message Date
Linus Walleij b99e6fb865 pinctrl: fix allmodconfig noise
There was some mess in the dependencies in the pinctrl
Kconfig for compile tests under allmodconfig. Mea Culpa.

Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-15 10:02:42 +02:00
Linus Torvalds 07e492eb89 This is the bulk of pin control changes for the v4.1 development
cycle:
 
 New drivers:
   - Intel Sunrisepoint
   - AMD KERNCZ GPIO
   - Broadcom Cygnus IOMUX
 
 New subdrivers:
   - Marvell MVEBU Armada 39x SoCs
   - Samsung Exynos 5433
   - nVidia Tegra 210
   - Mediatek MT8135
   - Mediatek MT8173
   - AMLogic Meson8b
   - Qualcomm PM8916
 
 On top of this cleanups and development history for the above
 drivers as issues were fixed after merging.
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Merge tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pincontrol updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.1 development
  cycle.  Nothing really exciting this time: we basically added a few
  new drivers and subdrivers and stabilized them in linux-next.  Some
  cleanups too.  With sunrisepoint Intel has a real fine fully featured
  pin control driver for contemporary hardware, and the AMD driver is
  also for large deployments.  Most of the others are ARM devices.

  New drivers:
    - Intel Sunrisepoint
    - AMD KERNCZ GPIO
    - Broadcom Cygnus IOMUX

  New subdrivers:
    - Marvell MVEBU Armada 39x SoCs
    - Samsung Exynos 5433
    - nVidia Tegra 210
    - Mediatek MT8135
    - Mediatek MT8173
    - AMLogic Meson8b
    - Qualcomm PM8916

  On top of this cleanups and development history for the above drivers
  as issues were fixed after merging"

* tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits)
  pinctrl: sirf: move sgpio lock into state container
  pinctrl: Add support for PM8916 GPIO's and MPP's
  pinctrl: bcm2835: Fix support for threaded level triggered IRQs
  sh-pfc: r8a7790: add EtherAVB pin groups
  pinctrl: Document "function" + "pins" pinmux binding
  pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support
  pinctrl: fsl: imx: Check for 0 config register
  pinctrl: Add support for Meson8b
  documentation: Extend pinctrl docs for Meson8b
  pinctrl: Cleanup Meson8 driver
  Fix inconsistent spinlock of AMD GPIO driver which can be recognized by static analysis tool smatch. Declare constant Variables with Sparse's suggestion.
  pinctrl: at91: convert __raw to endian agnostic IO
  pinctrl: constify of_device_id array
  pinctrl: pinconf-generic: add dt node names to error messages
  pinctrl: pinconf-generic: scan also referenced phandle node
  pinctrl: mvebu: add suspend/resume support to Armada XP pinctrl driver
  pinctrl: st: Display pin's function when printing pinctrl debug information
  pinctrl: st: Show correct pin direction also in GPIO mode
  pinctrl: st: Supply a GPIO get_direction() call-back
  pinctrl: st: Move st_get_pio_control() further up the source file
  ...
2015-04-14 17:58:15 -07:00
Linus Torvalds d0bbe0dd35 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
Pull trivial tree from Jiri Kosina:
 "Usual trivial tree updates.  Nothing outstanding -- mostly printk()
  and comment fixes and unused identifier removals"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial:
  goldfish: goldfish_tty_probe() is not using 'i' any more
  powerpc: Fix comment in smu.h
  qla2xxx: Fix printks in ql_log message
  lib: correct link to the original source for div64_u64
  si2168, tda10071, m88ds3103: Fix firmware wording
  usb: storage: Fix printk in isd200_log_config()
  qla2xxx: Fix printk in qla25xx_setup_mode
  init/main: fix reset_device comment
  ipwireless: missing assignment
  goldfish: remove unreachable line of code
  coredump: Fix do_coredump() comment
  stacktrace.h: remove duplicate declaration task_struct
  smpboot.h: Remove unused function prototype
  treewide: Fix typo in printk messages
  treewide: Fix typo in printk messages
  mod_devicetable: fix comment for match_flags
2015-04-14 09:50:27 -07:00
Linus Walleij 1dfe0d159d pinctrl: sirf: move sgpio lock into state container
Instead of referring to a global static variable for the sgpio
locking, use the state container to contain the lock.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-09 10:16:13 +02:00
Ivan T. Ivanov 7414b0993c pinctrl: Add support for PM8916 GPIO's and MPP's
Add compatible string definitions and supported pin functions.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-08 17:00:18 +02:00
Charles Keepax b8a19382ac pinctrl: bcm2835: Fix support for threaded level triggered IRQs
Currently, the driver uses handle_simple_irq for all IRQ types and hard
codes the acknowledge for different IRQ types into the handler. It is
better to use the IRQ core as intended and let it handle the differences
between the various types of IRQ. For example the current system does
not work for threaded level triggered IRQs as these need to be masked
until the threaded handler has run.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-08 16:41:59 +02:00
Sergei Shtylyov 19ef697d1e sh-pfc: r8a7790: add EtherAVB pin groups
Add EtherAVB pin groups to R8A7790 PFC driver.

Based on original patch by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 15:21:26 +02:00
Mika Westerberg 7981c0015a pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support
This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a
Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO
interrupts).

The driver is split into core and platform parts so that the same core
driver can be reused in other drivers for other Intel GPIO hardware that is
based on the same host controller design.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 15:15:23 +02:00
Markus Pargmann 16837f9588 pinctrl: fsl: imx: Check for 0 config register
0 is used in all pinfunction definitions when a config register is not
available, for example imx25-pinfunc.h. If a configuration value is used
for such a pinfunction the driver will always write it to the
configuration register if it is not -1. For a 0 configuration register
the configuration value is written to offset 0x0. This can lead to a
crashing/hanging system without any warning message.

This patch checks for 0 config register and sets the internal value to
-1. If the configuration value is not NO_PADCTL this leads to an error
message that applying the configuration failed.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 15:11:00 +02:00
Carlo Caione 0fefcb6876 pinctrl: Add support for Meson8b
This patch adds support for the AmLogic Meson8b SoC.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 11:44:40 +02:00
Carlo Caione faa246debf documentation: Extend pinctrl docs for Meson8b
Add the compatible string for Meson8b in Meson pinctrl documentation
and add new information for Meson8b in source code comments.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 11:42:38 +02:00
Carlo Caione 0cf6f3c2b5 pinctrl: Cleanup Meson8 driver
This patch introduces a new PIN macro and few small modifications to
simplify and shorten the Meson pinctrl drivers and cleanup the support
file for the AmLogic Meson8 SoC.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 11:40:42 +02:00
Ken Xue 25a853d037 Fix inconsistent spinlock of AMD GPIO driver which can be
recognized by static analysis tool smatch. Declare constant
Variables with Sparse's suggestion.

Signed-off-by: Ken Xue <Ken.Xue@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 11:36:49 +02:00
Ben Dooks d480239ba4 pinctrl: at91: convert __raw to endian agnostic IO
Use endian agnostic _relaxed IO accessors instead of the __raw ones.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Cc: Andrew Victor <linux@maxim.org.za>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-07 11:05:53 +02:00
Fabian Frederick baa9946e32 pinctrl: constify of_device_id array
of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)

Signed-off-by: Fabian Frederick <fabf@skynet.be>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Acked-by: Lee Jones <lee@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-27 09:58:35 +01:00
Baruch Siach 4024efb404 pinctrl: pinconf-generic: add dt node names to error messages
This makes the error message much more useful.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-27 09:53:10 +01:00
Baruch Siach c7289500e2 pinctrl: pinconf-generic: scan also referenced phandle node
Make pinconf_generic_dt_node_to_map() also scan the dt pin configuration node
directly referenced by phandle, not only its child nodes.

The "parent scan" feature needs a few other changes:

   * Move the pinconf_generic_dt_node_to_map() error handling code to a common
     place, under the 'exit' label.

   * Move the pins/groups strings count earlier in
     pinconf_generic_dt_subnode_to_map(), to allow us to bail out early when
     these properties are missing or wrong

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-27 09:51:22 +01:00
Thomas Petazzoni 12149a20b8 pinctrl: mvebu: add suspend/resume support to Armada XP pinctrl driver
This commit adds suspend/resume support to the Armada XP pinctrl
driver, by simply saving and restoring the MPP registers.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-27 09:35:08 +01:00
Lee Jones a8381faca5 pinctrl: st: Display pin's function when printing pinctrl debug information
Great for easily determining which mode a pin is operating in.
This patch was particularly helpful when debugging a recent GPIO/
Pinctrl disparity issue.

Before:
    $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
      pin 33 (PIO4[1]):[OE:0,PU:0,OD:0]
             [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]

After [GPIO]:
    $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
      pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] GPIO
             [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]

After [Alt]:
    $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
      pin 33 (PIO4[1]):[OE:0,PU:0,OD:0] Alt Fn 2
             [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-25 16:39:17 +01:00
Lee Jones e2ed0e88ec pinctrl: st: Show correct pin direction also in GPIO mode
Until now ST's pinconf_dbg_show() call-back has displayed the PIO
alternate function direction, which is only relevant if a pin is
operating in an alternate function mode i.e not GPIO mode.  If a
pin is in GPIO mode its direction is both set and status is
obtained by a completely different/unrelated bunch of registers.

This change ensures that the correct pin direction is shown, even
if a pin is operating in GPIO mode.

Reported-by: Olivier Clergeaud <olivier.clergeaud@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-25 16:38:06 +01:00
Lee Jones 1e702ec2aa pinctrl: st: Supply a GPIO get_direction() call-back
ST's hardware differentiates between GPIO mode and Pinctrl alternate
functions.  When a pin is in GPIO mode, there are dedicated registers
to set and obtain direction status.  However, If a pin's alternate
function is in use then the direction is set and status is derived
from a bunch of syscon registers.  The issue is; until now there was
a lack of parity between the two.

For example:

Catting the two following information sources could result in
conflicting information (output has been snipped for simplicity):

 $ cat /sys/kernel/debug/gpio
  GPIOs 32-39, platform/961f080.pin-controller-sbc, PIO4:
   gpio-33  (?                   ) out hi

 $ cat /sys/kernel/debug/pinctrl/<pin-controller>/pinconf-pins
  pin 33 (PIO4[1]):[OE:0,PU:0,OD:0]
         [retime:0,invclk:0,clknotdat:0,de:0,rt-clk:0,rt-delay:0]

In this example GPIO-33 is a GPIO controlled LED, which is set for
output, as you'd expect.  However, when the same information is
drafted from Pinctrl, it clearly states that OE (Output Enable) is
not set i.e. the pin is set for input.  This is because OE normally
only represents alternate functions and has no bearing on how the
pin operates when in Alt-0 (GPIO mode).

This patch changes the current semantics and provides a parity link
between the two subsystems.  The get_direction() call-back firstly
determines which function a pin is operating in, then uses the
appropriate helpers for that mode.

Reported-by: Olivier Clergeaud <olivier.clergeaud@st.com>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-25 16:37:03 +01:00
Lee Jones f89e68fc3b pinctrl: st: Move st_get_pio_control() further up the source file
st_get_pio_control() will be used by subsequent calls which are
to be located above its original position.  This is required to
prevent the need for an unnecessary forward-declaration/prototype.

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-25 16:36:07 +01:00
Lee Jones c2a4bf4708 pinctrl: st: Introduce a 'get pin function' call
This call fetches the numerical function value a specified pin is
currently operating in.  Function zero is more often than not the
GPIO function.  Greater than zero values represent an alternative
function.  You'd need to either look those up in the Device Tree
sources or the Programmer's Manual.

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-25 16:35:10 +01:00
Stefan Agner e4c02dced9 pinctrl: tegra: use signed bitfields for optional fields
Optional fields are set to -1 by various preprocessor macros. Make
sure the fields can actually store them.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-19 09:20:17 +01:00
Axel Lin 86d64dce9e pinctrl: mediatek: mt8135/mt8173: Constify of_device_id table
Also make the table a bit compact.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 13:09:37 +01:00
Axel Lin 0206caa81c pinctrl: mediatek: mtk-common: Use devm_kcalloc at appropriate places
Prefer devm_kcalloc over devm_kzalloc with multiply.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 13:08:08 +01:00
Axel Lin 0dae530ccf pinctrl: mediatek: mt8135/mt8173: Fix build error due to missing include file
Fix below build error:
  CC      drivers/pinctrl/mediatek/pinctrl-mt8135.o
In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0:
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error: pinctrl-mtk-common.h: No such file or directory
compilation terminated.
make[3]: *** [drivers/pinctrl/mediatek/pinctrl-mt8135.o] Error 1
make[2]: *** [drivers/pinctrl/mediatek] Error 2
make[1]: *** [drivers/pinctrl] Error 2
make: *** [drivers] Error 2

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 13:06:09 +01:00
Yingjoe Chen 4a8ade1f6b pinctrl: mediatek: Adjust mt8173 pinctrl kconfig
ARM64 maintainer doesn't want to add MACH_* for each SoC.
Adjust mt8173 pinctrl kconfig entry so user can manually select it.

Also make PINCTRL_MT8135 selectable when COMPILE_TEST is enabled.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 13:00:16 +01:00
Axel Lin 61a3557671 pinctrl: mediatek: mtk-common: Remove kfree
Remove erroneous kfree for memory allocated by devm_kzalloc

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 12:57:48 +01:00
Guenter Roeck d48c532eb4 pinctrl: mediatek: Fix include directive
Fix the following build failure:

In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0:
drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error:
	pinctrl-mtk-common.h: No such file or directory

seen when building arm:multi_v7_defconfig.

Fixes: 94097d89c145 ("pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.")
Cc: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 10:58:21 +01:00
Hans de Goede ef6d24cc7f pinctrl: sun4i: GPIOs configured as irq must be set to input before reading
On sun4i-a10, when GPIOs are configured as external interrupt the value for
them in the data register does not seem to get updated, so set their mux to
input (and restore afterwards) when reading the pin.

Missed edges seem to be buffered, so this does not introduce a race
condition.

I've also tested this on sun5i-a13 and sun7i-a20 and those do not seem to
be affected, the input value representation in the data register does seem
to correctly get updated to the actual pin value while in irq mode there.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 10:56:46 +01:00
Geert Uytterhoeven 9895afae1b pinctrl: sh-pfc: Remove r8a7790 platform_device_id entry
The r8a7790 platform is now DT-only, the driver doesn't need to match
platform devices by name anymore. Remove the corresponding
platform_device_id entry.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:18:33 +01:00
Geert Uytterhoeven 889439cddc pinctrl: sh-pfc: Remove emev2 platform_device_id entry
The emev2 platform is now DT-only, the driver doesn't need to match
platform devices by name anymore. Remove the corresponding
platform_device_id entry.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:16:53 +01:00
Geert Uytterhoeven 1f34de05e7 pinctrl: sh-pfc: Use u32 to store register addresses
Currently all PFC registers lie in low 32-bit address space. Hence use
u32 instead of unsigned long to store PFC register addresses in pinctrl
tables.  All calculations of virtual addresses use a phys_addr_t
intermediate, so we know where to add an offset if the 32-bit assumption
ever becomes false.

While this doesn't impact 32-bit builds, it would save ca. 7 KiB on a
64-bit shmobile_defconfig kernel.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:15:40 +01:00
Geert Uytterhoeven 17c7cbb0e7 pinctrl: sh-pfc: Use reg_width instead of reg as sentinel
All other loops over sh_pfc_soc_info.data_regs[] use
pinmux_data_reg.regwidth as the sentinel, which is safer as zero is
never a valid regwidth value (reg could be zero if we start using it to
store an offset).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:14:45 +01:00
Geert Uytterhoeven cef28a2894 pinctrl: sh-pfc: Use unsigned int for register/field widths and offsets
As register and field widths and offsets are in the range 1..32, use
unsigned int (mostly replacing unsigned long) to store them in local
variables and for passing them around.

Move to one variable per line, move variables to the beginning of the
block where they are used, and drop superfluous initializations while we
are at it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:13:47 +01:00
Geert Uytterhoeven dc70071550 pinctrl: sh-pfc: Store register/field widths in u8 instead of unsigned long
Register and field widths are in the range 1..32. Storing them in the
pinctrl data in (arrays of) unsigned long wastes space.

This decreases the size of a (32-bit) shmobile_defconfig kernel
supporting 7 SoCs by 26460 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:12:47 +01:00
Ken Xue dbad75dd1f pinctrl: add AMD GPIO driver support.
KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM.
Current driver patch only support GPIO in x86.

Signed-off-by: Ken Xue <Ken.Xue@amd.com>
[Moved back to <linux/gpio.h> header]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:21 +01:00
Abhilash Kesavan 45937b5b5e pinctrl: exynos: Remove eint_gpio_init call-back for exynos7 alive pinctrl block
The alive pin controller on exynos7 does not support external gpio
interrupts. Hence, remove the eint_gpio_init call-back for it. This
fixes the following error message seen during exynos7 boot-up:
"samsung-pinctrl 10580000.pinctrl: irq number not available"

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:19 +01:00
Ray Jui b64333ce76 pinctrl: cygnus: add gpio/pinconf driver
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver
that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO
controller, the chipCommonG GPIO controller, and the always-on GPIO
controller. Basic PINCONF configurations such as bias pull up/down, and
drive strength are also supported in this driver.

Pins from the ASIU GPIO controller can be individually muxed to GPIO
function, through interaction with the Cygnus IOMUX controller

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Tested-by: Dmitry Torokhov <dtor@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:19 +01:00
Hongzhou Yang c445cac307 pinctrl: mediatek: fix build error
Due to pinconf_generic_parse_dt_config() API changes in pinctrl
devel branch, add one parameter to fix build error.

Also fix warning:
drivers/pinctrl/mediatek/pinctrl-mtk-common.c:718:3: warning:
too many arguments for format [-Wformat-extra-args]
      dev_err(&pdev->dev, "only support pins-are-numbered format\n", ret);
      ^

by removing extra parameter when calling dev_err in mtk_pctrl_init.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:17 +01:00
Yingjoe Chen 3221f40b76 pinctrl: mediatek: emulate GPIO interrupt on both-edges
MTK EINT does not support generating interrupt on both edges.
Emulate this by changing edge polarity while enable irq,
set types and interrupt handling. This follows an example of
drivers/gpio/gpio-mxc.c.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:16 +01:00
Hongzhou Yang 30f010f5c4 arm64: mediatek: Add Pinctrl/GPIO/EINT driver for mt8173.
Add mt8173 support using mediatek common pinctrl driver.
MT8173 have a different ies_smt setting register than mt8135,
so adding this support to common code.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:16 +01:00
Maoguang Meng d9819eb9cd pinctrl: mediatek: Add EINT support to MTK pinctrl driver.
MTK SoC support external interrupt(EINT) from most SoC pins.
Add EINT support to pinctrl driver.

Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com>
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:15 +01:00
Hongzhou Yang a6df410d42 pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs.

The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control.

This driver include common driver and mt8135 part.
The common driver include the pinctrl driver and GPIO driver.
The mt8135 part contain its special device data.

Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:14 +01:00
Geert Uytterhoeven fc88936ad3 pinctrl: sh-pfc: Use u32 to store register data
As PFC registers are either 8, 16, or 32 bits wide, use u32 (mostly
replacing unsigned long) to store (parts of) register values and masks.

Switch the shadow register operations from {set,clear}_bit() to plain C
bit operations, as the former can operate on long data only.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:13 +01:00
Ray Jui cbd159ed4f pinctrl: cygnus: add initial IOMUX driver support
This adds the initial driver support for the Broadcom Cygnus IOMUX
controller. The Cygnus IOMUX controller supports group based mux
configuration but allows certain pins to be muxed to GPIO individually

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Tested-by: Dmitry Torokhov <dtor@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:13 +01:00
Ray Jui b17f2f9b86 pinctrl: bcm: consolidate Broadcom pinctrl drivers
Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/*

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:12 +01:00
Stefan Agner 4691dd0148 pinctrl: imx: do not implicitly set pin regs to -1
Commit 3dac1918a4 ("pinctrl: imx: detect uninitialized pins") needs
the values in struct imx_pin_reg to be -1. This has been done in a
rather unorthodox way by setting the memory to 0xff using memset...
Use a proper for loop to initialize the whole array with -1.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:02:11 +01:00
Boris Brezillon bd8733738c pinctrl: at91: move lock/unlock_as_irq calls into request/release
The gpiochip_lock_as_irq call can fail and return an error,
while the irq_startup is not expected to fail (returns an
unsigned int which is not checked by irq core code).

irq_request/release_resources functions have been created
to address this problem.

Move gpiochip_lock/unlock_as_irq calls into
irq_request/release_resources functions to prevent using a
gpio as an irq if the gpiochip_lock_as_irq call failed.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-18 02:01:36 +01:00