Commit Graph

4 Commits

Author SHA1 Message Date
Milo Kim 66cd89df8c pinctrl: sunxi: Remove unsupported PWM channel pinmux in H3
H3 has single PWM channel. The second PWM channel is not supported,
so the pinctrl function should be removed.

Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-08 01:08:23 +02:00
Icenowy Zheng bc0f566a98 pinctrl: sunxi: fix nand0 function name for sun8i
In sun4/5/6/7i, all the pin function related to NAND0 controller is
named "nand0". However, in sun8i, some of the functions are named as
"nand". This patch renamed them to "nand0", for the consistency.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-07-05 15:45:55 +02:00
Krzysztof Adamski 111f2b8732 pinctrl: sunxi: H3 requires irq_read_needs_mux
It seems that on H3, just like on A10, when GPIOs are configured as
external interrupt data registers does not contain their value.  When
value is read, GPIO function must be temporary switched to input for
reads.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-11 14:29:13 +01:00
Jens Kuske e87623cb3b pinctrl: sunxi: Add H3 PIO controller support
The H3 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-11 10:15:33 +01:00