KVM capabilities can be a per-VM property, though ARM/ARM64 currently
does not pass on the VM pointer to the architecture specific
capability handlers.
Add a "struct kvm*" parameter to those function to later allow proper
per-VM capability reporting.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Eric Auger <eric.auger@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
We merged two patches that both enabled CONFIG_PWM, leading to a harmless
warning:
arch/arm64/configs/defconfig:352:warning: override: reassigning to symbol PWM
This removes one of the two identical lines to avoid the warning.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
A slew of updates for Tegra210 support: PMIC and regulator additions,
which in turn allow a bunch of features to be enabled. Some assemblies
of the Jetson TX1 come with a DSI panel that is now supported. For all
other assemblies, this set of changes enables the HDMI output. Jetson
TX1 can now also make use of the XUSB controller.
PMIC and regulator support is also added for Smaug, which will allow a
number of interesting feature additions in future releases.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJXh6TbAAoJEN0jrNd/PrOh5oIP/1y4Qmn/et6hR62t6qbvRIGW
muaa+YTCI/kUscPdzissnkEytcEnVDHeRscybgB9LAz2q6r5Hudqsf/nLggpoUak
4dbOFcWc4UBcfzF+/glgByrtpe6m6gnjw7m/LSkKENHl4+pCGtOwo9jsJlwvnPZ0
H2MQ/UMgCvCGprxiY6l115g1GelamgPGJ1ZPLjGfEGa42mzRb1vHuFtzsI+qFIZc
Qi6leSBd+NJCiAgp1Sfzmx/XV3uasuXNmv91t3vJWJly0AbQMF0s3PlMfDIRH9ZP
YaltAXfFXzzsZJ1yKENnFz34DnWY07x2VKkaf+8jBweur7/TgOaciAg9SQd5rSPm
oHE5gLDo/82FOlfA+6rQ05b3KbQgFiwh1MlO3bODx3rSm/+wNc6Otv7rPQ0nBbG3
sGzqMudSLxr6azqCardk29l95dTFHtR0OvHmkwQVSffvHLp2Q1htQrONZM0au9ZH
QKGl1HSwEdpF5fDaacYwxNQV+zgLrGNH1UbIi/b6OHI0sVRZc/iyKo31vAIBQPmE
audMiMKj68FmI+m8AyBLIl9xsDCfLA+m3KlBO/2mVNm7fTNh344SJbx/QV6rTHP3
FtPC4Usmf9xwBdULDeRdV60yvQXqcpa0rBE8PzuZ3/siJP8eFjzLrI8bYXhtSJo+
cJx7V6o0Y0sc5PjNPA3y
=3zUA
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.8-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/late
Merge "arm64: tegra: Device tree changes for v4.8-rc1" from Thierry Reding:
A slew of updates for Tegra210 support: PMIC and regulator additions,
which in turn allow a bunch of features to be enabled. Some assemblies
of the Jetson TX1 come with a DSI panel that is now supported. For all
other assemblies, this set of changes enables the HDMI output. Jetson
TX1 can now also make use of the XUSB controller.
PMIC and regulator support is also added for Smaug, which will allow a
number of interesting feature additions in future releases.
* tag 'tegra-for-4.8-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Enable HDMI on Jetson TX1
arm64: tegra: Add sor1_src clock
arm64: tegra: Add XUSB powergates on Tegra210
arm64: tegra: Add DPAUX pinctrl bindings
arm64: tegra: Add ACONNECT bus node for Tegra210
arm64: tegra: Add audio powergate node for Tegra210
arm64: tegra: Add regulators for Tegra210 Smaug
arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
arm64: tegra: Enable XUSB controller on Jetson TX1
arm64: tegra: Enable debug serial on Jetson TX1
arm64: tegra: Add Tegra210 XUSB controller
arm64: tegra: Add Tegra210 XUSB pad controller
arm64: tegra: Add DSI panel on Jetson TX1
arm64: tegra: p2597: Add SDMMC power supplies
arm64: tegra: Add PMIC support on Jetson TX1
Merge "ARM64: DT: Hisilicon Hi6220 updates for 4.8" from Wei Xu:
- Add pl031 rtc0 and rtc1 support for hi6220 SoC
* tag 'hi6220-dt-for-4.8-2' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hi6220: Add pl031 RTC support
clk: hi6220: Add RTC clock for pl031
The sor1 IP block needs the sor1_src clock to configure the clock tree
depending on whether it's running in HDMI or DP mode.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra210 XUSB subsystem has 3 power partitions which are XUSBA
(super-speed logic), XUSBB (USB device logic) and XUSBC (USB host
logic). Populate the device-tree nodes for these XUSB partitions.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the DPAUX pinctrl states for the DPAUX nodes defining all three
possible states of "aux", "i2c" and "off". Also add the 'i2c-bus'
node for the DPAUX nodes so that the I2C driver core does not attempt
to parse the pinctrl state nodes.
Populate the nodes for the pinctrl clients of the DPAUX pin controller.
There are two clients for each DPAUX instance, namely the SOR and one of
the I2C adapters. The SOR clients may used the DPAUX pins in either AUX
or I2C modes and so for these devices we don't define any of the generic
pinctrl states (default, idle, etc) because the SOR driver will directly
set the state needed. For I2C clients only the I2C mode is used and so
we can simplify matters by using the generic pinctrl states for default
and idle.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the ACONNECT bus node for Tegra210 which is used to interface to
the various devices in the Audio Processing Engine (APE).
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add regulators to the Tegra210 Smaug DTS file including support for the
MAX77620 PMIC.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for
the XUSB pad controller. For some Tegra210 boards, this is causing USB
connect and disconnect events to go undetected. Fix this by changing the
interrupt number for the XUSB mailbox to 40.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable the XUSB controller on Jetson TX1. One of the USB 3.0 lanes goes
to an internal ethernet interface, while a second USB 3.0 lane supports
the USB-A receptacle on the I/O board.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a chosen node to the device tree that contains a stdout-path
property which defines the debug serial port.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a device tree node for the Tegra XUSB controller. It contains a
phandle to the XUSB pad controller for control of the PHYs assigned
to the USB ports.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add power supplies for the SD/MMC card slot. Note that vmmc-supply is
currently restricted to 3.3 V because we don't support switching the
mode yet.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a device tree node for the MAX77620 PMIC found on the p2180
processor module (Jetson TX1). Also add supporting power supplies,
such as the main 5 V system supply.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable a bunch of configuration options to enable PMIC, regulators, DSI,
HDMI, XUSB and the GPU on Jetson TX1 as well as a few new features that
are now functional on the Google Pixel C.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJXg7cpAAoJEN0jrNd/PrOhZxQP/ivrqi+21lLdzFzIyuVgtOOe
i+5mVoqfrIx/QCXsRqzgRj4PiTttGaUJKPRLxp3z6bJLRnFRrcuCPF7hTN8Ln+nr
XXMO2rAanvWJ00rYFmqTF/9j4zkHyfbpEjugSh7yO5nrT7QupYQe0RAE7C6d4tGa
QyAr5FZChSPBYIKSKPZ9A+Fhn+cUCTJT0AJdcwcM4W42HR4cgaMniFniK3KJHqZp
3jw3PDgh5+hW7x2axOrhGxWi49lToUytsmCOYaW6x0OuKmiUfRLoBW5+LGhg/xVt
ZZQTyFrIoCiNM1xqufMNwC9tOurtE7D7CHaSxWuTSOa0mljDPgsacRiz3HLpZqFd
3MRlT3vGeeG2XPBMxOdJYrpqn9RP59mex8rDNKOqDEBWHRPfJkCkfy9/uM1qYYl6
8aMehNITnvfqCr+Y7AQHp/Vz2PJRwo8vK0eksrL/K2j7hgFwYAyKDm3qmcwpLooQ
4rQEb0iH5IU4DCL56IqmI0yuHiF2EbxeNjbvywyUJZRPBCCzETCTD1VzaUUO3A2e
5daZIwGwvt5/ZEf+rv99JRa8FNzscpnsivLaiC9u6I3nGUb8J/oZDZmAeP0NDzG9
N6BftJpAuQ5CTLYKna4ADNjF+L2pk/vNWR5EW2aP13BFIiQ99iiJFhJcUbvelkVy
ED4DXclrwVLP/QBYS9QJ
=483Z
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.8-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/arm64
Merge "arm64: tegra: Default configuration updates for v4.8-rc1" from Thierry Reding:
Enable a bunch of configuration options to enable PMIC, regulators, DSI,
HDMI, XUSB and the GPU on Jetson TX1 as well as a few new features that
are now functional on the Google Pixel C.
* tag 'tegra-for-4.8-arm64-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: Update default configuration
1. Adjust the voltage of CPU buck regulator so scaling could work.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXg72DAAoJEME3ZuaGi4PX/4oP/0pqr0rdy7mllqGccFtPSrR5
zezxSuPlgTpFOlQNF1xMGZuArPZ+KeqkHJzqCDBNzeDia9jqjsKpO2HliRGsOpoy
QZ/vh8aJxORBxwSRm6j+4Pg887Q6dyKivT0xL0mOdGS/b8DZZpOPHf4LVA2TKPJD
3V6igtvLLaNKGCZI1d4ZAMKR/fvZhLWkTIYk7llxX70Fv4YYH0WURLRcRDQvB5FX
G99+fzJfsyABTlquieS1Pt5LnHv7K/jKTvxbSc/0pxpz8LvmBWH6odFHJ8d3E+g0
Kw4jq8AEmf5QEu04cO/lpIDvN1nDO+4gd8040GOcd1+2vNXlJsne4CRIWN8PbWFW
wzlJ62xk1qJ41vicGZv3DCrO0yNJI80e1KS9zLfHpjO1nqxC36Zs7P6KbV3eIZsT
bT+eHKC6MwD95YWfOCHpsbRRa8kOFg2TYBfW/Z+Lz0lOCiVJOjSrcYGHLablS7mw
8yPlPcGu1cyWD8nhDYhu9CVUqkZW0ZQc0QK+TZdPzz9374b8rnlvcLwgHqNEy/5P
1/RfmZ1LaJH1hPMfYrA0Wgup9h/ui577q6EMdU2FxivHTUuzraUlWDu+qLSDq/59
qpo06a/CXGDDwwNW63icopP8ayte9iWXZNoE1pzpNXmS6ZnO/O14d2oI2DsdTtYP
LM3uBdhZVewSzdXrfc5G
=ku6i
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Merge "Samsung DeviceTree changes for ARM64 for v4.8" from Krzysztof Kozlowski:
1. Adjust the voltage of CPU buck regulator so scaling could work.
* tag 'samsung-dt64-4.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Modify the voltage range for BUCK2 for exynos7
My static checker complains that this condition looks like it should be
== instead of =. This isn't a fast path, so we don't need to be fancy.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
1. Adds various CoreSight debug components on Juno boards
2. Adds SCPI device power domains and use them for coresight components
3. Adds thermal zones for SCPI sensors on Juno
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJXfNUDAAoJEABBurwxfuKYFnsQAKojeKxW8Otmx3e6/l86tueH
/piDxsDJKts78deI9ueYXbK52hu9muaB43+GF2SIWx2x010ei98dKUSS8D2R5DeX
MQbV1yVY35DyY9eLI1t6irDoTS/LUzwnf6zD6kIYBfH1Vlf375H2kIRSviAbROLR
f7LwBYLYeDyLwCFSAqEq6uhgustkRsh/6EoU2AGpYuCJj00qfNOAAsBpph54TeST
NTvwiWqEjDBrQ9+ANeBDRVUekpIiJsEaJ0NbxzpeVqAdSDfEf7EE9xHL34Q4oLih
Q/8IVhq8YSdHBBxLPqeT5OSD8F+meex050tMmBogURIcAVAmNKKhUmktsXhGuz4w
9k4zE365dNC/K5ssjWngSZqZpU536ga9qYkAqhNXTzFujNVp+0Cg3Z6ap0EsIbJj
F6omOFM6qBxGnUs7ccG+x5CF2IqeamiBOSy8jUDR+UYfhsqdY1HTTCWlJSkylhwi
eNE90fnBJ3qB4rRDDksern+xMcjYfr7aTxzgWu2AS36pWeRXiR0LjOVcC57laEAQ
kPxFGDYKdpY5VfG7VDznJOZNfsDSMRKPNgFKSK9qtdR8gcWUk7S0fIlbEqEVQzdS
E9m+gOom7ocmXDpeqfZf7BIK7i5GAxmmuMUbmEEz3NvZs6t8RoaUuJGQpMhB3Tek
G+MD1ew5cu2CaPstKeij
=bxrw
-----END PGP SIGNATURE-----
Merge tag 'juno-dt-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64
Merge "Juno platform DT updates for v4.8" from Sudeep Holla:
1. Adds various CoreSight debug components on Juno boards
2. Adds SCPI device power domains and use them for coresight components
3. Adds thermal zones for SCPI sensors on Juno
* tag 'juno-dt-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: add thermal zones for scpi sensors
arm64: dts: juno: add SCPI power domains for device power management
arm64: dts: juno: add coresight support
It can be useful for JIT software to be aware of MIDR_EL1 and
REVIDR_EL1 to ascertain the presence of any core errata that could
affect code generation.
This patch exposes these registers through sysfs:
/sys/devices/system/cpu/cpu$ID/regs/identification/midr_el1
/sys/devices/system/cpu/cpu$ID/regs/identification/revidr_el1
where $ID is the cpu number. For big.LITTLE systems, one can have a
mixture of cores (e.g. Cortex A53 and Cortex A57), thus all CPUs need
to be enumerated.
If the kernel does not have valid information to populate these entries
with, an empty string is returned to userspace.
Cc: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Steve Capper <steve.capper@linaro.org>
[suzuki.poulose@arm.com: ABI documentation updates, hotplug notifiers, kobject changes]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
So far the arm64 clock_gettime() vDSO implementation only supported
the following clocks, falling back to the syscall for the others:
- CLOCK_REALTIME{,_COARSE}
- CLOCK_MONOTONIC{,_COARSE}
This patch adds support for the CLOCK_MONOTONIC_RAW clock, taking
advantage of the recent refactoring of the vDSO time functions. Like
the non-_COARSE clocks, this only works when the "arch_sys_counter"
clocksource is in use (allowing us to read the current time from the
virtual counter register), otherwise we also have to fall back to the
syscall.
Most of the data is shared with CLOCK_MONOTONIC, and the algorithm is
similar. The reference implementation in kernel/time/timekeeping.c
shows that:
- CLOCK_MONOTONIC = tk->wall_to_monotonic + tk->xtime_sec +
timekeeping_get_ns(&tk->tkr_mono)
- CLOCK_MONOTONIC_RAW = tk->raw_time + timekeeping_get_ns(&tk->tkr_raw)
- tkr_mono and tkr_raw are identical (in particular, same
clocksource), except these members:
* mult (only mono's multiplier is NTP-adjusted)
* xtime_nsec (always 0 for raw)
Therefore, tk->raw_time and tkr_raw->mult are now also stored in the
vDSO data page.
Cc: Ali Saidi <ali.saidi@arm.com>
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
Reviewed-by: Dave Martin <dave.martin@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Time functions are directly implemented in assembly in arm64, and it
is desirable to keep it this way for performance reasons (everything
fits in registers, so that the stack is not used at all). However, the
current implementation is quite difficult to read and understand (even
considering it's assembly). Additionally, due to the structure of
__kernel_clock_gettime, which heavily uses conditional branches to
share code between the different clocks, it is difficult to support a
new clock without making the branches even harder to follow.
This commit completely refactors the structure of clock_gettime (and
gettimeofday along the way) while keeping exactly the same algorithms.
We no longer try to share code; instead, macros provide common
operations. This new approach comes with a number of advantages:
- In clock_gettime, clock implementations are no longer interspersed,
making them much more readable. Additionally, macros only use
registers passed as arguments or reserved with .req, this way it is
easy to make sure that registers are properly allocated. To avoid a
large number of branches in a given execution path, a jump table is
used; a normal execution uses 3 unconditional branches.
- __do_get_tspec has been replaced with 2 macros (get_ts_clock_mono,
get_clock_shifted_nsec) and explicit loading of data from the vDSO
page. Consequently, clock_gettime and gettimeofday are now leaf
functions, and saving x30 (lr) is no longer necessary.
- Variables protected by tb_seq_count are now loaded all at once,
allowing to merge the seqcnt_read macro into seqcnt_check.
- For CLOCK_REALTIME_COARSE, removed an unused load of the wall to
monotonic timespec.
- For CLOCK_MONOTONIC_COARSE, removed a few shift instructions.
Obviously, the downside of sharing less code is an increase in code
size. However since the vDSO has its own code page, this does not
really matter, as long as the size of the DSO remains below 4 kB. For
now this should be all right:
Before After
vdso.so size (B) 2776 3000
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
Reviewed-by: Dave Martin <dave.martin@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arm64/kernel/{vdso,signal}.c include vdso-offsets.h, as well as any
file that includes asm/vdso.h. Therefore, vdso-offsets.h must be
generated before these files are compiled.
The current rules in arm64/kernel/Makefile do not actually enforce
this, because even though $(obj)/vdso is listed as a prerequisite for
vdso-offsets.h, this does not result in the intended effect of
building the vdso subdirectory (before all the other objects). As a
consequence, depending on the order in which the rules are followed,
vdso-offsets.h is updated or not before arm64/kernel/{vdso,signal}.o
are built. The current rules also impose an unnecessary dependency on
vdso-offsets.h for all arm64/kernel/*.o, resulting in unnecessary
rebuilds. This is made obvious when using make -j:
touch arch/arm64/kernel/vdso/gettimeofday.S && make -j$NCPUS arch/arm64/kernel
will sometimes result in none of arm64/kernel/*.o being
rebuilt, sometimes all of them, or even just some of them.
It is quite difficult to ensure that a header is generated before it
is used with recursive Makefiles by using normal rules. Instead,
arch-specific generated headers are normally built in the archprepare
recipe in the arch Makefile (see for instance arch/ia64/Makefile).
Unfortunately, asm-offsets.h is included in gettimeofday.S, and must
therefore be generated before vdso-offsets.h, which is not the case if
archprepare is used. For this reason, a rule run after archprepare has
to be used.
This commit adds rules in arm64/Makefile to build vdso-offsets.h
during the prepare step, ensuring that vdso-offsets.h is generated
before building anything. It also removes the now-unnecessary
dependencies on vdso-offsets.h in arm64/kernel/Makefile. Finally, it
removes the duplication of asm-offsets.h between arm64/kernel/vdso/
and include/generated/ and makes include/generated/vdso-offsets.h a
target in arm64/kernel/vdso/Makefile.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Michal Marek <mmarek@suse.com>
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This reverts commit 90f777beb7.
While this commit was aimed at fixing the dependencies, with a large
make -j the vdso-offsets.h file is not generated, leading to build
failures.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Enable a couple of drivers that are used on Jetson TX1:
* GPIO_PCA953X, GPIO_PCA953X_IRQ: Two instances of this I2C GPIO
expander are used on Jetson TX1 to expand the number of usable GPIOs
on the I/O board. Enable the driver for this expander along with IRQ
support.
* MFD_MAX77620, REGULATOR_MAX77620, PINCTRL_MAX77620, GPIO_MAX77620,
RTC_DRV_MAX77686: Enable support for the PMIC and various of its
components found on the Jetson TX1 processor module (p2180).
* RTC_DRV_TEGRA: This RTC is usually not hooked up to a battery on
boards, but it can be useful as a wakeup source from suspend to RAM.
* REGULATOR_PWM: The GPU is supplied by a regulator controlled via one
of the Tegra's PWM channels.
* DRM, DRM_NOUVEAU, DRM_TEGRA, DRM_PANEL_SIMPLE: Enable support for an
optional DSI panel on Jetson TX1 as well as the GPU.
* BACKLIGHT_GENERIC, BACKLIGHT_LP855X: The backlight on Jetson TX1, if
shipped with a display module, is driver by an LP8557.
* PHY_TEGRA_XUSB, USB_XHCI_TEGRA: Enable support for XUSB (USB 3.0) on
Jetson TX1.
* PWM, PWM_TEGRA: One of the PWM channels is used to control the
voltage supplied to the GPU.
* NFS_V4_1, NFS_V4_2: Support these newer versions of the NFS protocol
to increase compatibility with distributions.
* MFD_CROS_EC, MFD_CROS_EC_I2C and I2C_CROS_EC_TUNNEL: Used to enable
the ChromeOS Embedded Controller and the I2C tunnel that allows the
EC to function as an I2C bridge.
* BATTERY_BQ27XXX: Support the battery charger and monitor found on
the Google Pixel C.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable more drivers for IP blocks for existing Exynos7 and upcoming
Exynos5433:
1. SPI,
2. Watchdog,
3. USB: DWC3, Exynos EHCI and OHCI,
4. Exynos ADC,
5. Samsung PWM.
These are already used by Exynos7 Espresso board or will be used by
Exynos5433 based board.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJXefulAAoJEHm+PkMAQRiG6nMH/2O1vcZeOtqmx2yCMUeXyKAT
wG88XflXzf3rM7C7TiObEYVf/bbLleJ7saDLEeic7ButD5gyYacIuzylVnrcqfBc
vinz4cOw5kvu9DrRkCKdOfiTAgwYtqQW+syJ8ZK4lPQuSxnPAs+F/FKSOpyUF5FN
Dngr520KjYKBEtn27W9UDPChFRwQoWAlaOC534eusaArCJtHGHHiuq5TEDn2EIo8
pUw2vwx5JiquSHOY34WLU7r+QoilovCQlUSsBQdLlPjfMB1QFtclPYa+5yEMjkT4
wusOUOfS/zK0rV6KnEdc/SkpiVX5C9WpFiWUOdEeJ5mZ+KijVkaOa9K1EDx8jSM=
=7Hwh
-----END PGP SIGNATURE-----
Merge tag 'v4.7-rc6' into patchwork
Linux 4.7-rc6
* tag 'v4.7-rc6': (1245 commits)
Linux 4.7-rc6
ovl: warn instead of error if d_type is not supported
MIPS: Fix possible corruption of cache mode by mprotect.
locks: use file_inode()
usb: dwc3: st: Use explicit reset_control_get_exclusive() API
phy: phy-stih407-usb: Use explicit reset_control_get_exclusive() API
phy: miphy28lp: Inform the reset framework that our reset line may be shared
namespace: update event counter when umounting a deleted dentry
9p: use file_dentry()
lockd: unregister notifier blocks if the service fails to come up completely
ACPI,PCI,IRQ: correct operator precedence
fuse: serialize dirops by default
drm/i915: Fix missing unlock on error in i915_ppgtt_info()
powerpc: Initialise pci_io_base as early as possible
mfd: da9053: Fix compiler warning message for uninitialised variable
mfd: max77620: Fix FPS switch statements
phy: phy-stih407-usb: Inform the reset framework that our reset line may be shared
usb: dwc3: st: Inform the reset framework that our reset line may be shared
usb: host: ehci-st: Inform the reset framework that our reset line may be shared
usb: host: ohci-st: Inform the reset framework that our reset line may be shared
...
Add video encoder node for MT8173
Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
Current bus notifier in ARM64 (__iommu_attach_notifier)
attempts to attach dma_ops to a device on BUS_NOTIFY_ADD_DEVICE
action notification.
This will cause issues on ACPI based systems, where PCI devices
can be added before the IOMMUs the devices are attached to
had a chance to be probed, causing failures on attempts to
attach dma_ops in that the domain for the respective IOMMU
may not be set-up yet by the time the bus notifier is run.
Devices dma_ops do not require to be set-up till the matching
device drivers are probed. This means that instead of running
the notifier attaching dma_ops to devices (__iommu_attach_notifier)
on BUS_NOTIFY_ADD_DEVICE action, it can be run just before the
device driver is bound to the device in question (on action
BUS_NOTIFY_BIND_DRIVER) so that it is certain that its IOMMU
group and domain are set-up accordingly at the time the
notifier is triggered.
This patch changes the notifier action upon which dma_ops
are attached to devices and defer it to driver binding time,
so that IOMMU devices have a chance to be probed and to register
their bus notifiers before the dma_ops attach sequence for a
device is actually carried out.
As a result we also no longer need worry about racing with
iommu_bus_notifier(), or about retrying the queue in case devices
were added too early on DT-based systems, so clean up the notifier
itself plus the additional workaround from 722ec35f7f ("arm64:
dma-mapping: fix handling of devices registered before arch_initcall")
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[rm: get rid of other now-redundant bits]
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/kernel/{vdso,signal}.c include generated/vdso-offsets.h, and
therefore the symbol offsets must be generated before these files are
compiled.
The current rules in arm64/kernel/Makefile do not actually enforce
this, because even though $(obj)/vdso is listed as a prerequisite for
vdso-offsets.h, this does not result in the intended effect of
building the vdso subdirectory (before all the other objects). As a
consequence, depending on the order in which the rules are followed,
vdso-offsets.h is updated or not before arm64/kernel/{vdso,signal}.o
are built. The current rules also impose an unnecessary dependency on
vdso-offsets.h for all arm64/kernel/*.o, resulting in unnecessary
rebuilds.
This patch removes the arch/arm64/kernel/vdso/vdso-offsets.h file
generation, leaving only the include/generated/vdso-offsets.h one. It
adds a forced dependency check of the vdso-offsets.h file in
arch/arm64/kernel/Makefile which, if not up to date according to the
arch/arm64/kernel/vdso/Makefile rules (depending on vdso.so.dbg), will
trigger the vdso/ subdirectory build and vdso-offsets.h re-generation.
Automatic kbuild dependency rules between kernel/{vdso,signal}.c rules
and vdso-offsets.h will guarantee that the vDSO object is built first,
followed by the generated symbol offsets header file.
Reported-by: Kevin Brodsky <kevin.brodsky@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cavium erratum 27456 commit 104a0c02e8
("arm64: Add workaround for Cavium erratum 27456")
is applicable for thunderx-81xx pass1.0 SoC as well.
Adding code to enable to 81xx.
Signed-off-by: Ganapatrao Kulkarni <gkulkarni@cavium.com>
Reviewed-by: Andrew Pinski <apinski@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The AmLogic clock controller code is used by both arm and arm64
architectures. Explicitly select the core code for all Meson (arm64)
builds, and also select the GXBB driver, since that's the way arm64 does
things.
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This reverts commit f3abd62961, which caused a build regression:
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi:48:41: fatal error: dt-bindings/clock/gxbb-clkc.h: No such file or directory
We should apply this patch one merge window later, once the clk branch
is merged as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
If we take an exception while at EL1, the exception handler inherits
the original context's addr_limit and PSTATE.UAO values. To be consistent
always reset addr_limit and PSTATE.UAO on (re-)entry to EL1. This
prevents accidental re-use of the original context's addr_limit.
Based on a similar patch for arm from Russell King.
Cc: <stable@vger.kernel.org> # 4.6-
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
- Eric updates the bcm2836 interrupt controller driver not to rely on ARM/Linux specific functions
in preparation for using it on ARM64
- Eric also adds a Kconfig entry for the BCM2835 Raspberry Pi family in the ARM64 Kconfig.platforms
file
- Eric cherry picked a patch from Alexander Graf with Acks from ARM64 maintainers to support different
DMA and bus offsets, required for the Raspberry Pi 3 SoC
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXfeKCAAoJEIfQlpxEBwcE5lsQANQE4ppxhTsQe/VhxWFnIchC
UEBRTP00iFtQbiYLrP0irRe37QxRy16A5AY7yFp9CHPOe9Ut1fvzwOORCsXViqSo
5NB3UGUnLJmrBSe5q8wbGXXc0JAnFwcFEHIvnhRVPy8lG2dC0QsABmxoOgen1euz
WFFW3/nWhG3U8S59h0WqYeSlspbr9byDRFLYA8nvyK1GKtaRkwnAd4OuqKhHcI1t
1Yw1H9WnQk5deEYEYki6LJCNggJ4+cqltFb2h0x7QcMTVLz/KmNDA7uAmR+ZxLpx
RinlzKW8kdDFOqhzfr250M3z6THCpX9DR+NUjkaua5NxFuQZvhdLldOu9wXlo5Ya
bhYXgeU3YHdAw3mVHmCwqaNv0UDAhKAbmXtriqqJs44bF0HWr7oT4FyhMf7r1Pae
V6V3Oh+xYknaYOCS7Ny4ALkPFH7CbArLU5CCvW8uTSt3K38MMmFDwPurAlb7bVph
UB6jmsNVwPXrs40ha0IMnVgwnC5m8eva4g+UbV/KBr7vrSC4XQMwRfTd4Cm6ZhtB
GymQ9y7hR4VDkLnt1QNbQDWz+PE4ycixn3uN070rA+6evi0DLcOLH+KK+g3lPdsl
dZqxBkZR1JpzIM4OezKK6XzlR6cKUSW+vJ4GrDllWIHXXRILVVZLHdiDRG2rBrv0
/1rBUxXZoPvSGY79dRqD
=qrTS
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-4.8/soc-arm64-part2' of http://github.com/Broadcom/stblinux into next/arm64
Merge "Broadcom ARM64-based SoC changes for 4.8 second part" from Florian Fainelli:
- Eric updates the bcm2836 interrupt controller driver not to rely on ARM/Linux specific functions
in preparation for using it on ARM64
- Eric also adds a Kconfig entry for the BCM2835 Raspberry Pi family in the ARM64 Kconfig.platforms
file
- Eric cherry picked a patch from Alexander Graf with Acks from ARM64 maintainers to support different
DMA and bus offsets, required for the Raspberry Pi 3 SoC
* tag 'arm-soc/for-4.8/soc-arm64-part2' of http://github.com/Broadcom/stblinux:
arm64: Add platform selection for BCM2835.
arm64: Allow for different DMA and CPU bus offsets
irqchip: bcm2835: Avoid arch/arm-specific handle_IRQ
changes for 4.8. Please note that this pull request contains changes from the
ARM 32-bits port and ARM 64-bits port as well:
- Lubomir updates all BCM2835 (Raspberry Pi family) Device Tree source files with
their proper information about the on-board USB Ethernet adapter so there is
appropriate binding between this USB device and a device_node (useful for MAC
address fetching and stuff), this commit is also present for the ARM DT pull
request
- Eric adds support for the Raspberry Pi 3 aka BCM2837 and provides the binding
information and the basic SoC DT include file required to boot to a prompt
- Gerd updates the Raspberry Pi 3 DT with Ethernet information based on the
earlier change from Lubomir
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXfcQqAAoJEIfQlpxEBwcE1dAQANrY/Qj4mwSkTcvRYTwZqf6/
KOGivObK0t53Fo3EzVZnBlBI+rotm3EBN9MXsiQmODZkdVE6UMZPBUrHQREjc83w
6NN95xMxPwaJRfhgwo9vRzeGTNvMhJMkIP5JlNYU0QcDHpDr1OSzIuGPFeRdnMbB
ksXVg6JUec6b4Mt2vyU4DkW7upLA9mYQe5KXvXx4hkMGKaCXPF7CL0Ba5eQURYhl
gu53DUCfTnyGFqKu0gxJIoWL5GWETa1ySuFC5BQvMhVbSFI2ObZZb3b7CIrvBgL1
ugPhfKTm72EGDKaWCliiQ4jU1JKZqhDUY5FevTBGSH9Soi4+ncgOytoNA9h6swwq
DcxKfkp5OlEzfpVey6c73MdZ5Hj9SLFqsn0Q0gYrYEYP5RCkekKU4qX+mssbXLZe
gFVo+NR+ui8g+98p5MysMO+97/jA8M+7nMbsmWhSa8QOwK8e3HE2vuZo9yyPhGvl
feEgP8ZFlY1ZrTkni0fOM6HfTTqyMoSHY0JmMEFBP21D6l2OyWyw2oOJWu1aZK9k
Anw+CzmaryOSyA86AHMnwDqyTFnC2CD7NZOYnYYcwVTH2yiZrO6EFocNHRIoYtUE
uv6M7c0TAeVGFF/iQEIfBmtBJU5Ku71M4dN7p8nAsbw9yGp2CpfHcMc+qy8lsl0W
15ZTYMEPJa7jU/hu0e/+
=KQmU
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-4.8/devicetree-arm64-part2' of http://github.com/Broadcom/stblinux into next/dt64
Merge "Broadcom ARM64 Device Tree changes for 4.8 (part 2)" from Florian Fainelli:
This pull request contains the second part of the Broadcom ARM64-based SoCs
changes for 4.8. Please note that this pull request contains changes from the
ARM 32-bits port and ARM 64-bits port as well:
- Lubomir updates all BCM2835 (Raspberry Pi family) Device Tree source files with
their proper information about the on-board USB Ethernet adapter so there is
appropriate binding between this USB device and a device_node (useful for MAC
address fetching and stuff), this commit is also present for the ARM DT pull
request
- Eric adds support for the Raspberry Pi 3 aka BCM2837 and provides the binding
information and the basic SoC DT include file required to boot to a prompt
- Gerd updates the Raspberry Pi 3 DT with Ethernet information based on the
earlier change from Lubomir
* tag 'arm-soc/for-4.8/devicetree-arm64-part2' of http://github.com/Broadcom/stblinux:
ARM: bcm2837: dt: Add the ethernet to the device trees
ARM: bcm2835: Add devicetree for the Raspberry Pi 3.
dt-bindings: Add root properties for Raspberry Pi 3
ARM: bcm2835: dt: Add the ethernet to the device trees
Pull the clockevents/clocksource tree from Daniel Lezcano:
- Convert the clocksource-probe init functions to return a value in order to
prepare the consolidation of the drivers using the DT. It is a big patchset
but went through 01.org (kbuild bot), linux next and kernel-ci (continuous
integration) (Daniel Lezcano)
- Fix a bad error handling by returning the right value for cadence_ttc
(Christophe Jaillet)
- Fix typo in the Kconfig for the Samsung pwm (Alexandre Belloni)
- Change functions to static for armada-370-xp and digicolor (Ben Dooks)
- Add support for the rk3399 SoC timer by adding bindings and a slight
change in the base address. Take the opportunity to add the DYNIRQ flag
(Huang Tao)
- Fix endian accessors for the Samsung pwm timer (Matthew Leach)
- Add Oxford Semiconductor RPS Dual Timer driver (Neil Armstrong)
- Add a kernel parameter to swich on/off the event stream feature of the arch
arm timer (Will Deacon)
- update dt with mv-xor-v2 found in the Armada 7K/8K SoCs
- update dt with the clocks found in the Armada 3700 SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAld6y2sACgkQCwYYjhRyO9UU9wCgpZ7Nd5KeqQMuwOPL/RNjIg6F
oHsAoKcUVoQteML8NkpMeyr9Lk+dtb0A
=OElN
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.8-1' of git://git.infradead.org/linux-mvebu into next/dt64
Merge "mvebu dt64 for 4.8 (part 1)" from Gregory CLEMENT:
- update dt with mv-xor-v2 found in the Armada 7K/8K SoCs
- update dt with the clocks found in the Armada 3700 SoCs
* tag 'mvebu-dt64-4.8-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: add peripherals clocks for Armada 37xx
arm64: dts: marvell: add tbg clocks for Armada 37xx
arm64: dts: marvell: Add xtal clock support for Armada 3700
arm64: dts: marvell: add XOR engine description for Armada 7K/8K CP
arm64: dts: marvell: adjust to the latest mv-xor-v2 DT binding
enable Armada 3700 clock drivers
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAld6ykAACgkQCwYYjhRyO9Wo8ACdH6kYBKYuaivu3ggVBoSle+01
5noAn13h+iScUld+CAn0UVktOjd7Yplp
=sjV8
-----END PGP SIGNATURE-----
Merge tag 'mvebu-arm64-4.8-1' of git://git.infradead.org/linux-mvebu into next/arm64
Merge "mvebu arm64 for 4.8" from Gregory CLEMENT:
enable Armada 3700 clock drivers
* tag 'mvebu-arm64-4.8-1' of git://git.infradead.org/linux-mvebu:
arm64: marvell: enable Armada 3700 clock drivers
Enable the Watchdog Timer (WDT) controller on the Renesas Salvator-X
board equipped with an R-Car M3-W (r8a7796) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the Watchdog Timer (WDT) controller on the Renesas
R-Car M3-W (r8a7796) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Hook up all devices that are part of the CPG/MSSR Clock Domain to the
SYSC "always-on" PM Domain, for a more consistent device-power-area
description in DT.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the System Controller.
Hook up the Cortex-A57 CPU core and L2 cache/SCU to their respective PM
Domains.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Basic support for the Gen 3 R-Car M3-W SoC.
Based on work for the r8a7795 and r8a7796 SoCs by
Takeshi Kihara, Dirk Behme and Geert Uytterhoeven.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Adds CAN FD controller node for r8a7795.
Note: CAN FD controller register base address specified in R-Car Gen3
Hardware User Manual v0.5E is incorrect. The correct address is:
CAN FD - 0xe66c0000
Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
For consistency with a57_0/a57_1 cpu nodes, and all other nodes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
smp_cond_load_acquire() is used to spin on a variable until some
expression involving that variable becomes true.
On arm64, we can build this using the LDXR and WFE instructions, since
clearing of the exclusive monitor as a result of the variable being
changed by another CPU generates an event, which will wake us up out of WFE.
This patch implements smp_cond_load_acquire() using LDXR and WFE, which
themselves are contained in an internal __cmpwait() function.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: catalin.marinas@arm.com
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1467049434-30451-1-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
i2c and core io-domain nodes and some reasonable default rates
for core clocks. The rk3368 also gets io-domains for its r88 board
as well as a small fix for the gic's memory regions.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJXdbPUAAoJEPOmecmc0R2BiAUH/2UBBQ1f5A9W5bCtxe+kirFa
R+4tDNske10/h3ey+igciC+6SG4RavHyQn/MoQvu2rzeZvAoPRYi2IVR3/RERf86
uuDNMqI9C0zQNujuiN/1eVMLAhAUoDZ9+uC1uEJ6ilzKwcsk6Sb+8Fo/zQnR8evd
Z4GK+YnJtLvxQ3joEh5AcRbd+CaURjAXeJt1HGlDcLCG8HHKNNDpzaFPV2uaoVXp
1hwx7X8tY5u13K0W7yAzaAq5C4poKa+OpdxlE5g+ryOFWqnqco4l/BBaWg+XK0z5
XvPjtDE5Di8Wpgjeik/4KLwG/maD9ogdPAZGmg+U2SkGlwVdcOSZmSOE2mFHf3c=
=W2eY
-----END PGP SIGNATURE-----
Merge tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
The rk3399 gets support for its emmc controller as well as thermal,
i2c and core io-domain nodes and some reasonable default rates
for core clocks. The rk3368 also gets io-domains for its r88 board
as well as a small fix for the gic's memory regions.
* tag 'v4.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399
arm64: dts: rockchip: Provide emmcclk to PHY for rk3399
arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368
arm64: dts: rockchip: add i2c nodes for rk3399
arm64: dts: rockchip: add thermal nodes for rk3399 SoCs
arm64: dts: rockchip: add rk3399 io-domain core nodes
arm64: dts: rockchip: add rk3368-r88 iodomains
arm64: dts: rockchip: add rk3368 io-domain core nodes
arm64: dts: rockchip: make rk3368 grf syscons simple-mfds
arm64: dts: rockchip: enable eMMC for rk3399 EVB
arm64: dts: rockchip: add sdhci/emmc for rk3399
arm64: dts: rockchip: make rk3399's grf a "simple-mfd"
arm64: dts: rockchip: assign default rates for core rk3399 clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
When running on Xen hypervisor, runtime services are supported through
hypercall. Add a Xen specific function to initialize runtime services.
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Tested-by: Julien Grall <julien.grall@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Move xen_early_init() before efi_init(), then when calling efi_init()
could initialize Xen specific UEFI.
Check if it runs on Xen hypervisor through the flat dts.
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Tested-by: Julien Grall <julien.grall@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Change the BUCK2 (vdd_atlas) voltage range to '500 - 1200mv' since
CPU DVFS requires it.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
The S3C RTC controller on Exynos7 platform uses RTC source clock
from S2MPS11 PMIC. This patch enables the required drivers to make
RTC work on Exynos7 Espresso board.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
- name the GPIO lines
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXcq9/AAoJEAvIV27ZiWZcuEUQAIjDX8Bq6WNerOSsn/kyWIhb
0lTNHae6D4mxKax6u9npwiMpBl7JsgVkfzU6es0iZtZe+g6dAOOJMOvjRX/aPZD2
oiO05vHtU+wKlcCvRPTinTRGK3lAzsPda9xMxEuaztbcg1fmFgflpx4r+n4Gwsy4
DsPr/Miw3bMPJGtQrx4YFd9Rb7ehkDyyq7PXUBYlRtnZs4Osgxm2LVhoZsw2vQTi
u7JAA/N8R1bg7jYHEAIW+8GgPGJRcRPesGSmt92ELVVZHROP+7wx6y2PAsP+PDIO
ZIuVvqGFYWfb5bgzfYS0bApYAzcVdsGLYEzbJHEuHE84ZKzXQ0YGoZmNID3RN5Ns
2gboC7DJU+e3k6AUoBckn7drpCC7BjkwVJr3NqvyvygztdnhoibdRYxaO8ywfzD+
TY3ul0GDyUGdWsLcwTdwtbA3azdh3xFmKGzPfJGGhcN7SNfenkTxJsvNroze5PZC
ilqE5W25tS/ATqqqx2PBPbQQK4wTL0sULbFWSvt6jxYyV0OBekOMyvLnLLux/XOg
Q4XltZ16nG42ujKv0j/GCz5L0oNIuLBDqt0zF7Wa9pHq0aK+BeDXMmRf3fZ2ZLUu
4/awoQcXqorxWF8Hc8QTg/iE/I9OkiKpWzzhgIoYwabRPay/WV6Dk0kAO8UjkeAJ
OK7zJAbKnk1zYAchYxfo
=bqGx
-----END PGP SIGNATURE-----
Merge tag 'hi6220-dt-for-4.8' of git://github.com/hisilicon/linux-hisi into next/dt64
ARM64: DT: Hisilicon Hi6220 hikey board updates for 4.8
- name the GPIO lines
* tag 'hi6220-dt-for-4.8' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hikey: name the GPIO lines
Signed-off-by: Olof Johansson <olof@lixom.net>
- Update address-cells and reg properties of cpu nodes, considering
MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
and ls2080a
- Adds the cache nodes and next-level-cache property for ls1043a and
ls2080a to get cacheinfo work on these platforms
- Add dma-coherent for ls1043a PCI nodes to utilize the hardware
capability on data coherency
- Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
detection in P3 PHY mode
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJXcm2nAAoJEFBXWFqHsHzO6DAH/05cUGH7SLcJMBV0AVSEfCVK
eQTsriBUNNXcUwt70AUBAymfUkHPNysdN4P+KfReOc0j4FMQKqUB9UttUFItmxd2
plfhkd1wjusV5DqyqQI2Yzp7dsipgJdOoOUc206LISpJ2eaPZrOH0sOXUfZgcZ7h
F4vz5shTGk+zrvBbOd8VmTRizxr7Q1oUYAwOvAHH0DvFUFMfs3+nK8jN7qynBhnB
bdRbNxpNz2kkxrad3mIrKGLjPTBfNyhqTB6jwttwptzqOVxVhK59Kopox5dh2Mha
PvhLes1KYxdpw6CcyyJov7hvleRjKKK8kq08krEBldWeXPHB/GDREuMNg7EcNGU=
=m0V3
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
The Freescale arm64 device tree updates for 4.8:
- Update address-cells and reg properties of cpu nodes, considering
MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
and ls2080a
- Adds the cache nodes and next-level-cache property for ls1043a and
ls2080a to get cacheinfo work on these platforms
- Add dma-coherent for ls1043a PCI nodes to utilize the hardware
capability on data coherency
- Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
detection in P3 PHY mode
* tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: ls2080a: Add cache nodes for cacheinfo support
arm64: dts: ls1043a: Add cache nodes for cacheinfo support
arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
bindings: PCI: layerscape: Add 'dma-coherent' property
arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node
arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node
arm64: dts: fsl: Update address-cells and reg properties of cpu nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
arm64 port.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCgAGBQJXea6iAAoJELXWKTbR/J7oJlkP/jtpW5QNzWMUYq833W9/XqxU
CJQ2QvxFnYJGYAdyMUzsE+/nmXZYRwvoY/E2majlt9hblpkv8//r+EDKQzVd8KDs
AcYIskjljDNMQAzeEIowlA8LlMLRlQzo3xGSZ1F/PqGR7O41kxEGJGEWZM3t0ZEU
CShP028jc42z09XS/6JrFEEQZqG6QsDfp4ReCOrcI1VBG+NKzJbIAQkKDjw2Dw3g
NckvB2j6aAHzzQU/O4RZYfS+g/qvd76sTadAbW04aBEBvZ+bArK8w939mBpetpnB
La6LXmlujRdjugVWWVMJF8NzsE/RCLQI+TJZtUB49TFkcpaG8D4h2gMV7zwGgswv
HecvCZiZ2eHlc+MTUB9e7buANE5lbxKxZZZXaAAiD9dCBeCfi3N5QNSZ1e5BUnet
yJKaf0rX1CR46W9YO25pJ3lu2k5oADm7SdnmpVfCcVr6Btsq2ABEod2c0zYP2s5B
uBPl1R/QB3mzzNltkbICx8ENairp+Z1tKa3AQcmWy7FGb5DX5iqd5ESB/11H0SQs
uN9ePs32baGk0UyGR1m4HzbZOUlmb6dLnTwIKHdgCW2O5cUNE6QV1fJzoeU14zVK
6SWWbiEHXEoNQZ9JuqyVO+maMEypQLAQy42SY0EoMdNsSISbcxymVFhKVYhOR+uc
QVtEJiI3v+p0LD+xL2Nd
=Rdgt
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXfH/7AAoJEIfQlpxEBwcE2y4P/isPwi6mxx5t5EbbMXBMV+Yd
QbIH158lScKpfktBavCa9ktc6LtJOJspIGB7dsjMh4dLjtGIacufXRGIt9piakgR
tZhRE9a49c6mRS2/9LUN7xSWiE/naSWrwxldtz7wl/oR+sf7yfTO/rU/nIgg5F0p
KfeTq2QYn4kmY9KJl+VI1QN7vtbdIoCsyJMKn5IQRUqTyKeFERV1WQj9oQ0aUbB1
qUy0Wa2eQvCjNjz7VRXrQIqznkqy/q2yEozsmx6pwkG0GrNWrhST7B46E4lz3h0z
g0p8M6JvIbI3Wn/Jo8IlYv2Arsy4WNYgSE4oQapdZqFnyOae6O6tAWaJX10oYA+i
b7ya2vzKXWHVvy37HTQ/Y4yTqdIUMuYw2b7JWIiOlOPZPQa5Y9/EpyxYILkNprQO
WaOtrWb0R4FNP0PLJ9NXTQfXuTO+xJ/DMs2P5yzhAeNuN+MLgcM7DqJkSwSQVX/c
40fBP2DVRd+dYodg/sKbQscJsAMmUvzanypYLSlglvAnW7QhACBy8W46Ew9rFV0o
l1PMdOZhKZZykvrA8sXrStXqNzjnIndg7MpWer+peSr++ZUmXDtXr+4Q0N24ryD+
fLOVNlK/NMVI9+DheG/U68x983qB1pPHz9qBZkU+KJg544bIkp89N8HV02aXKxfY
eoA+8Qp/Gdu6e4oOMRe5
=pK2X
-----END PGP SIGNATURE-----
Merge tag 'bcm2835-arm64-next-2016-07-03' into soc-arm64/next
This pull request brings in the build support for the Raspberry Pi arm64
port. This has an external dependency on Jason Cooper's irqchip/bcm
branch, it is a stable branch based on v4.7-rc1, and it has been in
-next for a couple of weeks.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
support. Note that it also merges in the ethernet DT changes so that
the Pi3's ethernet can also get the MAC address.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCgAGBQJXea6FAAoJELXWKTbR/J7oTygP/A85W03JieEH/8K94YZPKD/A
H/5rag1zm77AI+hnBmItwC+z/aUUHOw2mMBJ4xHZ8+0bM0qWjfKIXpJs4IzoUXrw
BUNRWql2SeWRC73pntv31BoJl6MmE97Eeex3SvgI10NKh/z03ps5GOyRmwjHZxr+
T8hWRlYKB9jhapgMCA5CKh/1qzCPRArBimRUfyRwGU9OfoL3nH/ShUL/YF3pic/6
cIY2U9I9MKEnt6M1aubdjUYts+kB7wDSACMB+LmbYBhFIOaJWyR6d6A+UFNVrlbV
yYH736VI1mrZq2GV02i4o58u8Tmu7+R8HgTxO0x+TxoyGrqCDBBDmIJz4Kk5fdK8
hKAngYIfOTKlsGT7FkUoLKkaRxwhmY0QarryjOzlQcyCckwouNt03irlmwtUMU1r
yt5E1BveZfcGun9mfknJKZfsFmjWTwgUNOC0hVsPS77PY6c01sYUhUr+J8KrrwKT
bZeJcs14VXNvPDmO5Pvnzih5d8C4whoYY75hkeQ3R0MOFwMrTAz8iHepdO825A8F
65yJ9l6Ju/pEO0lQJL8klNYXK8gzGdQMP5xjcIKnO1SjN6/Ea/7K1dujfNo1l9Sv
ulRtV1a50NahDf1k2oXaeTmZbStQml9wwPZmg6dVUn2ixUuVg6TDtJD71+pCwsJd
efkY7Qr0HmGOyeSQwOXd
=tOiy
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXfH9vAAoJEIfQlpxEBwcEkU8P/jZL/E1nIdeToSNGd+Rnbok/
1CqEkx0e5tNr8o2BaslcmQT3QcJg+ioeCTiLqyHBDcg9/IyZZBscUVwa1PjRKt6N
sD2lhE9pz/gZXZnRjeB/DT5Yr4HjGisNK2ldS6KahN4rh077b8RqKIn93z4ToiYb
0q7uQg/tE11k9Y8XVZIzlz6Cz4BYrylkMI/oUAA4gg9kBzUMag/zvFqTSf+jVhke
0D1ekYwrJOdlbkI03XomyRyg58XqDIoWfN2Vn8v8UwS42/dV8LfaziJdWZU8r3gE
WXwzK8Uhcm59/AFxRiQZppx3aBiYUCwZz+OWHzSRPw4ifCvRvmZONQepFJ96Orj9
XYam02xGSSFDigV802kBbeDxF/v8OLQgsWuswkwIYVCdy1pR+Ak1kPYbROCUAP4s
6mhPg8cPHc8hiuGs6XKCz05JOwp+SSrL8qWfaefTI5pWM1or4ygzAeYKR889zUP7
j4JJRyCMCKc0KNkeO6VHnnVCDkDMn6O6X3NNlfzF0QelIxRurXEu/Exhp1xDpk9w
eUHD3rauBF6eJnz/bncmqKGO2m4GlrTMOhE2OLiRoW7i2/bLKkA02tpX56GiuIkK
pUOehuVfCaLfIlXAY+iaUz9w5IuK3VOXkHTUS9MJZEowWT84f51e9+nZhEbwSO/3
0sZU2VtiARV7nPoz2kCN
=4CCL
-----END PGP SIGNATURE-----
Merge tag 'bcm2835-dt-64-next-2016-07-03' into devicetree-arm64/next
This pull request brings in the Raspberry Pi 3 DT for its arm64
support. Note that it also merges in the ethernet DT changes so that
the Pi3's ethernet can also get the MAC address.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
1. Enable support for SCPI based sensors(temperature, voltage,
current and power)
2. Enable the Generic on-chip SRAM driver. SRAM is used for SCPI based
communication with SCP on Juno
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJXaQ0ZAAoJEABBurwxfuKYmooP/3VSLhrpD7gxtyNrfCxTge4O
3w3wvFtNrdvsce3nGZzdtcUs+G6iqj69rjwcTzfGMiLBmS2oD+LTfKYAF46JWgE7
KqHBPhUAz0d9UgfGWyLF8YEneTZ9TM6Gb6/3DFNE5zIIW1JlQBAkN61U1SYFw6JO
JPM1RbmA51cSosdS0woFZpQ391QwwXLIKkMCQWeWuK6qCjmtMKTAynEgmCXfoejX
Y2mdeTx0rsXDQsZIsX3Z65cKpd5M8FtN8hCoFm4hDTdMOVVX+aDhlzdk+CRsJWa7
2pXpUDqdwH1NPOikQqVwzhTizUur6IbXXYNO2V6k/M/HqplqVpuxpu+B90nvjoDo
UrswqKaJKjh29pRynkWVYGUggC6dQFN31lecEQMEPYk4FVifgwW7dOx3cekVvs67
wEjBCG2tbL5DkZOLe1s2f22bJQUItEb2Rwzya+o05l6y8ehxzdz/uUyagikPrqJO
ihCwTqsp/UOREaVUvAGrO3Av3FYcyx1fkN1GGYqsoyUPQognrMEsjBQGvRrmixHB
Ps4/kd89jJWaCpFMJYf5t0M1lSHGEN5esgSqnG01Pg7oOy2qqt6gNzVyTbH2tnXE
KvguBriCPIeE7TXQHb0Swep7nufXuTHvYoNQJxfa8oiqoyijlY1Bt3pLE67ST8xE
Rh1wTtONBqDNLtXoL3sm
=r5Ie
-----END PGP SIGNATURE-----
Merge tag 'juno-defconfig-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/arm64
ARMv8 Juno/Vexpress defconfig updates for v4.8
1. Enable support for SCPI based sensors(temperature, voltage,
current and power)
2. Enable the Generic on-chip SRAM driver. SRAM is used for SCPI based
communication with SCP on Juno
* tag 'juno-defconfig-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: defconfig: enable SENSORS_ARM_SCPI
arm64: defconfig: enable Generic on-chip SRAM driver
Signed-off-by: Olof Johansson <olof@lixom.net>
- Enable the PCIe host controller found on the Armada 7K/8K SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAldpA7YACgkQCwYYjhRyO9UpFwCgoVM2L6jaF0AU9Yg+aR8xeHrF
5xUAnRCe8B0TYqE0Bucj+MwmKXbWTLU7
=sEoy
-----END PGP SIGNATURE-----
Merge tag 'mvebu-defconfig64-4.8-1' of git://git.infradead.org/linux-mvebu into next/arm64
mvebu defconfig64 for 4.8 (part 1)
- Enable the PCIe host controller found on the Armada 7K/8K SoCs
* tag 'mvebu-defconfig64-4.8-1' of git://git.infradead.org/linux-mvebu:
arm64: configs: enable PCIe driver for Armada 7K/8K
Signed-off-by: Olof Johansson <olof@lixom.net>
Add two new blocks of clocks. The peripheral clocks are the source clocks
of the peripheral of the Armada 3700 SoC.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add a new block of clocks. The Time Base Generators clocks can be the
parent of the peripheral clocks.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The configuration of the clock depend of the gpio latch. This information
is stored in the gpio block registers. That's why the block is shared
using a syscon node.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
We have both KERN_TO_HYP and kern_hyp_va, which do the exact same
thing. Let's standardize on the latter.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
We can now remove a number of dead #defines, thanks to the trampoline
code being gone.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
So far, KVM was getting in the way of kexec on 32bit (and the arm64
kexec hackers couldn't be bothered to fix it on 32bit...).
With simpler page tables, tearing KVM down becomes very easy, so
let's just do it.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
There is no way to free the boot PGD, because it doesn't exist
anymore as a standalone entity.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Since we now only have one set of page tables, the concept of
boot_pgd is useless and can be removed. We still keep it as
an element of the "extended idmap" thing.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Now that we only have the "merged page tables" case to deal with,
there is a bunch of things we can simplify in the HYP code (both
at init and teardown time).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
We're in a position where we can now always have "merged" page
tables, where both the runtime mapping and the idmap coexist.
This results in some code being removed, but there is more to come.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Add the code that enables the switch to the lower HYP VA range.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Declare the __hyp_text_start/end symbols in asm/virt.h so that
they can be reused without having to declare them locally.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
As we move towards a selectable HYP VA range, it is obvious that
we don't want to test a variable to find out if we need to use
the bottom VA range, the top VA range, or use the address as is
(for VHE).
Instead, we can expand our current helper to generate the right
mask or nop with code patching. We default to using the top VA
space, with alternatives to switch to the bottom one or to nop
out the instructions.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Define the two possible HYP VA regions in terms of VA_BITS,
and keep HYP_PAGE_OFFSET_MASK as a temporary compatibility
definition.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
As we need to indicate to the rest of the kernel which region of
the HYP VA space is safe to use, add a capability that will
indicate that KVM should use the [VA_BITS-2:0] range.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
HYP_PAGE_OFFSET is not massively useful. And the way we use it
in KERN_HYP_VA is inconsistent with the equivalent operation in
EL2, where we use a mask instead.
Let's replace the uses of HYP_PAGE_OFFSET with HYP_PAGE_OFFSET_MASK,
and get rid of the pointless macro.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
hyp_kern_va is now completely unused, so let's remove it entirely.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
__hyp_panic_string is passed via the HYP panic code to the panic
function, and is being "upgraded" to a kernel address, as it is
referenced by the HYP code (in a PC-relative way).
This is a bit silly, and we'd be better off obtaining the kernel
address and not mess with it at all. This patch implements this
with a tiny bit of asm glue, by forcing the string pointer to be
read from the literal pool.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Since dealing with VA ranges tends to hurt my brain badly, let's
start with a bit of documentation that will hopefully help
understanding what comes next...
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
I don't think any single piece of the KVM/ARM code ever generated
as much hatred as the GIC emulation.
It was written by someone who had zero experience in modeling
hardware (me), was riddled with design flaws, should have been
scrapped and rewritten from scratch long before having a remote
chance of reaching mainline, and yet we supported it for a good
three years. No need to mention the names of those who suffered,
the git log is singing their praises.
Thankfully, we now have a much more maintainable implementation,
and we can safely put the grumpy old GIC to rest.
Fellow hackers, please raise your glass in memory of the GIC:
The GIC is dead, long live the GIC!
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
This adds basic chip support for MT6755 SoC.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
The routine __create_pgd_mapping() does nothing except calling init_pgd(),
which has no other callers. So fold the latter into the former. Also, drop
a comment that has gone stale.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Since the efi_create_mapping() no longer generates block mappings
and being the last user of the split_p*d code, remove these functions
and the corresponding TLBI.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
[ardb: replace 'overlapping regions' with 'block mappings' in commit log]
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
When running the OS with a page size > 4 KB, we need to round up mappings
for regions that are not aligned to the OS's page size. We already avoid
block mappings for EfiRuntimeServicesCode/Data regions for other reasons,
but in the unlikely event that other unaliged regions exists that have the
EFI_MEMORY_RUNTIME attribute set, ensure that unaligned regions are always
mapped down to pages. This way, the overlapping page is guaranteed not to
be covered by a block mapping that needs to be split.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
To avoid triggering diagnostics in the MMU code that are finicky about
splitting block mappings into more granular mappings, ensure that regions
that are likely to appear in the Memory Attributes table as well as the
UEFI memory map are always mapped down to pages. This way, we can use
apply_to_page_range() instead of create_pgd_mapping() for the second pass,
which cannot split or merge block entries, and operates strictly on PTEs.
Note that this aligns the arm64 Memory Attributes table handling code with
the ARM code, which already uses apply_to_page_range() to set the strict
permissions.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Add a bool parameter 'allow_block_mappings' to create_pgd_mapping() and
the various helper functions that it descends into, to give the caller
control over whether block entries may be used to create the mapping.
The UEFI runtime mapping routines will use this to avoid creating block
entries that would need to split up into page entries when applying the
permissions listed in the Memory Attributes firmware table.
This also replaces the block_mappings_allowed() helper function that was
added for DEBUG_PAGEALLOC functionality, but the resulting code is
functionally equivalent (given that debug_page_alloc does not operate on
EFI page table entries anyway)
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The ARM errata 819472, 826319, 827319 and 824069 for affected
Cortex-A53 cores demand to promote "dc cvau" instructions to
"dc civac". Since we allow userspace to also emit those instructions,
we should make sure that "dc cvau" gets promoted there too.
So lets grasp the nettle here and actually trap every userland cache
maintenance instruction once we detect at least one affected core in
the system.
We then emulate the instruction by executing it on behalf of userland,
promoting "dc cvau" to "dc civac" on the way and injecting access
fault back into userspace.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[catalin.marinas@arm.com: s/set_segfault/arm64_notify_segfault/]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The code for injecting a signal into userland if a trapped instruction
fails emulation due to a _userland_ error (like an illegal address)
will be used more often with the next patch.
Factor out the core functionality into a separate function and use
that both for the existing trap handler and for the deprecated
instructions emulation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[catalin.marinas@arm.com: s/set_segfault/arm64_notify_segfault/]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Currently we call the (optional) enable function for CPU _features_
only. As CPU _errata_ descriptions share the same data structure and
having an enable function is useful for errata as well (for instance
to set bits in SCTLR), lets call it when enumerating erratas too.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The newly introduced dcache_by_line_op macro is used at least in
one occassion at the moment to issue a "dc cvau" instruction,
which is affected by ARM errata 819472, 826319, 827319 and 824069.
Change the macro to allow for alternative patching in there to
protect affected Cortex-A53 cores.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[catalin.marinas@arm.com: indentation fixups]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The ARM errata 819472, 826319, 827319 and 824069 for affected
Cortex-A53 cores demand to promote "dc cvau" instructions to
"dc civac" as well.
Attribute the usage of the instruction in __flush_cache_user_range
to also be covered by our alternative patching efforts.
For that we introduce an assembly macro which both deals with
alternatives while still tagging the instructions as USER.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Commit 77ee306c0a ("arm64: alternatives: add enable parameter to
conditional asm macros") extended the alternative assembly macros.
Unfortunately this does not really work as one would expect, as the
enable parameter in fact correctly protects the alternative section
magic, but not the actual code sequences.
This results in having both the original instruction(s) _and_ the
alternative ones, if enable if false.
Since there is no user of this macros anyway, just revert it.
This reverts commit 77ee306c0a.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The memblock_alloc() and memblock_alloc_base() will panic on their own
if no free memory, remove pointless BUG_ON.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit adds the Device Tree description for the two XOR engines
found in the CP part of the Armada 7K/8K SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
As suggested by Rob Herring, we should:
1/ Use a SoC-specific compatible string in addition to the more generic
one.
2/ The generic compatible string has been changed from
"marvell,mv-xor-v2" to "marvell,xor-v2".
We simply reflect the changes made to the Device Tree bindings to the
relevant Marvell 7K/8K Device Tree files.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Several cases of overlapping changes, except the packet scheduler
conflicts which deal with the addition of the free list parameter
to qdisc_enqueue().
Signed-off-by: David S. Miller <davem@davemloft.net>
Structures that can be generally written to don't have any requirement
to be executable (quite the opposite). This includes the kvm and vcpu
structures, as well as the stacks.
Let's change the default to incorporate the XN flag.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
There should be no reason for mapping the HYP text read/write.
As such, let's have a new set of flags (PAGE_HYP_EXEC) that allows
execution, but makes the page as read-only, and update the two call
sites that deal with mapping code.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
In order to be able to use C code in HYP, we're now mapping the kernel's
rodata in HYP. It works absolutely fine, except that we're mapping it RWX,
which is not what it should be.
Add a new HYP_PAGE_RO protection, and pass it as the protection flags
when mapping the rodata section.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
EL2 page tables can be configured to deny code from being
executed, which is done by setting bit 54 in the page descriptor.
It is the same bit as PTE_UXN, but the "USER" reference felt odd
in the hypervisor code.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Currently, create_hyp_mappings applies a "one size fits all" page
protection (PAGE_HYP). As we're heading towards separate protections
for different sections, let's make this protection a parameter, and
let the callers pass their prefered protection (PAGE_HYP for everyone
for the time being).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
This names the GPIO lines on the HiKey board in accordance with
the 96Board Specification for especially the Low Speed External
Connector: "GPIO-A" thru "GPIO-L".
This will make these line names reflect through to userspace
so that they can easily be identified and used with the new
character device ABI.
Some care has been taken to name all lines, not just those used
by the external connectors, also lines that are muxed into some
other function than GPIO: these are named "[FOO]" so that users
can see with lsgpio what all lines are used for.
Cc: devicetree@vger.kernel.org
Cc: John Stultz <john.stultz@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: David Mandala <david.mandala@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add a 'rktimer' node in the device treee for the ARM64 rk3399 SoC.
Signed-off-by: Huang Tao <huangtao@rock-chips.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
As Kees Cook notes in the ARM counterpart of this patch [0]:
The _etext position is defined to be the end of the kernel text code,
and should not include any part of the data segments. This interferes
with things that might check memory ranges and expect executable code
up to _etext.
In particular, Kees is referring to the HARDENED_USERCOPY patch set [1],
which rejects attempts to call copy_to_user() on kernel ranges containing
executable code, but does allow access to the .rodata segment. Regardless
of whether one may or may not agree with the distinction, it makes sense
for _etext to have the same meaning across architectures.
So let's put _etext where it belongs, between .text and .rodata, and fix
up existing references to use __init_begin instead, which unlike _end_rodata
includes the exception and notes sections as well.
The _etext references in kaslr.c are left untouched, since its references
to [_stext, _etext) are meant to capture potential jump instruction targets,
and so disregarding .rodata is actually an improvement here.
[0] http://article.gmane.org/gmane.linux.kernel/2245084
[1] http://thread.gmane.org/gmane.linux.kernel.hardened.devel/2502
Reported-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
We currently open-code extracting the NUMA node of a memblock region,
which requires an ifdef to cater for !CONFIG_NUMA builds where the
memblock_region::nid field does not exist.
The generic memblock_get_region_node helper is intended to cater for
this. For CONFIG_HAVE_MEMBLOCK_NODE_MAP, builds this returns reg->nid,
and for for !CONFIG_HAVE_MEMBLOCK_NODE_MAP builds this is a static
inline that returns 0. Note that for arm64,
CONFIG_HAVE_MEMBLOCK_NODE_MAP is selected iff CONFIG_NUMA is.
This patch makes use of memblock_get_region_node to simplify the arm64
code. At the same time, we can move the nid variable definition into the
loop, as this is the only place it is used.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Steve Capper <steve.capper@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
To aid in debugging kexec problems or when adding new functionality to
kexec add a new routine kexec_image_info() and several inline pr_debug
statements.
Signed-off-by: Geoff Levand <geoff@infradead.org>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Add three new files, kexec.h, machine_kexec.c and relocate_kernel.S to the
arm64 architecture that add support for the kexec re-boot mechanism
(CONFIG_KEXEC) on arm64 platforms.
Signed-off-by: Geoff Levand <geoff@infradead.org>
Reviewed-by: James Morse <james.morse@arm.com>
[catalin.marinas@arm.com: removed dead code following James Morse's comments]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Commit 68234df4ea ("arm64: kill flush_cache_all()") removed the global
arm64 routines cpu_reset() and cpu_soft_restart() needed by the arm64
kexec and kdump support. Add back a simplified version of
cpu_soft_restart() with some changes needed for kexec in the new files
cpu_reset.S, and cpu_reset.h.
When a CPU is reset it needs to be put into the exception level it had when
it entered the kernel. Update cpu_soft_restart() to accept an argument
which signals if the reset address should be entered at EL1 or EL2, and
add a new hypercall HVC_SOFT_RESTART which is used for the EL2 switch.
Signed-off-by: Geoff Levand <geoff@infradead.org>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
kernel/smp.c has a fancy counter that keeps track of the number of CPUs
it marked as not-present and left in cpu_park_loop(). If there are any
CPUs spinning in here, features like kexec or hibernate may release them
by overwriting this memory.
This problem also occurs on machines using spin-tables to release
secondary cores.
After commit 44dbcc93ab ("arm64: Fix behavior of maxcpus=N")
we bring all known cpus into the secondary holding pen, meaning this
memory can't be re-used by kexec or hibernate.
Add a function cpus_are_stuck_in_kernel() to determine if either of these
cases have occurred.
Signed-off-by: James Morse <james.morse@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
[catalin.marinas@arm.com: cherry-picked from mainline for kexec dependency]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit makes a few slight modifications to the efi_call_virt() macro
to get it to work with function pointers that are stored in locations
other than efi.systab->runtime, and renames the macro to
efi_call_virt_pointer(). The majority of the changes here are to pull
these macros up into header files so that they can be accessed from
outside of drivers/firmware/efi/runtime-wrappers.c.
The most significant change not directly related to the code move is to
add an extra "p" argument into the appropriate efi_call macros, and use
that new argument in place of the, formerly hard-coded,
efi.systab->runtime pointer.
The last piece of the puzzle was to add an efi_call_virt() macro back into
drivers/firmware/efi/runtime-wrappers.c to wrap around the new
efi_call_virt_pointer() macro - this was mainly to keep the code from
looking too cluttered by adding a bunch of extra references to
efi.systab->runtime everywhere.
Note that I also broke up the code in the efi_call_virt_pointer() macro a
bit in the process of moving it.
Signed-off-by: Alex Thorlton <athorlton@sgi.com>
Signed-off-by: Matt Fleming <matt@codeblueprint.co.uk>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Dimitri Sivanich <sivanich@sgi.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Roy Franz <roy.franz@linaro.org>
Cc: Russ Anderson <rja@sgi.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-efi@vger.kernel.org
Link: http://lkml.kernel.org/r/1466839230-12781-5-git-send-email-matt@codeblueprint.co.uk
Signed-off-by: Ingo Molnar <mingo@kernel.org>
There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff.
Let's add the definition of these two pins to rk3399's main dtsi file so
that boards can use them.
These two pins are similar to the global_pwroff and ddrio_pwroff pins in
rk3288 and are expected to be used in the same way: boards will likely
want to configure these pinctrl settings in their global pinctrl hog
list.
Note that on rk3288 there were two additional pins in the "sleep"
section: "ddr0_retention" and "ddr1_retention". On rk3288 designs these
pins appeared to actually route from rk3288 back to rk3288. Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch enables pinctrl support required to boot msm8996/apq8096
boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Enable the clk drivers on msm8996. This allows us to boot and
test most device drivers on this SoC.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to sdc2 sdhci controller, which is used on some
of the boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds pinctrl required for sdhci for external sd card
controller.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp2_spi5 device, which is used in some of
the APQ8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp1_spi0 which is used on some of APQ8096
based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp2_i2c0, which is used on some of the
APQ8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp2_i2c0 pinctrl.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp2_i2c1, which is used in one of the
apq8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support to blsp2_i2c1 pinctrl nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds blsp1_i2c2 support, as this bus is used on some of the
apq8096 boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds bslp2_uart2 node in soc so that boards that use this
uart can enable it.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds 2pin and 4 pin uart pinctrl support for blsp2_uart1
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds msmgpio label for pin and gpio controller so that
it can referenced in dedicated pins file and other board level gpios.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Andre Przywara
Arnd Bergmann
Sebastian Andrzej Siewior
Thierry Reding
Jon Hunter
Rhyland Klein
Dan Carpenter
Thomas Gleixner
Steve Capper
Kevin Brodsky
Catalin Marinas
Krzysztof Kozlowski
Mauro Carvalho Chehab
Tiffany Lin
Lorenzo Pieralisi
Andrew-CT Chen
Ganapatrao Kulkarni
Michael Turquette
James Morse
Zhangfei Gao
Geert Uytterhoeven
Takeshi Kihara
Simon Horman
Ramesh Shanmugasundaram
Ingo Molnar
Will Deacon
Olof Johansson
Juergen Gross
Shannon Zhao
Abhilash Kesavan
Alim Akhtar
Florian Fainelli
Gregory CLEMENT
Marc Zyngier
Mars Cheng
Ard Biesheuvel
Kefeng Wang
Thomas Petazzoni
David S. Miller
Xinliang Liu
Linus Walleij
Huang Tao
Mark Rutland
Geoff Levand
Alex Thorlton
Douglas Anderson
Srinivas Kandagatla
Stephen Boyd
Andy Gross