Commit Graph

40 Commits

Author SHA1 Message Date
Stephen Boyd ef1ae47094 Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and 'clk-debugfs-simple' into clk-next
* clk-imx7d:
  clk: imx7d: reset parent for mipi csi root
  clk: imx7d: fix mipi dphy div parent

* clk-hisi-stub:
  clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB

* clk-mvebu:
  clk: mvebu: use correct bit for 98DX3236 NAND

* clk-imx6-epit:
  clk: imx6: add EPIT clock support

* clk-debugfs-simple:
  clk: Return void from debug_init op
  clk: remove clk_debugfs_add_file()
  clk: tegra: no need to check return value of debugfs_create functions
  clk: davinci: no need to check return value of debugfs_create functions
  clk: bcm2835: no need to check return value of debugfs_create functions
  clk: no need to check return value of debugfs_create functions
2018-06-04 12:32:28 -07:00
Rui Miguel Silva b4f5e1ffcc clk: imx7d: reset parent for mipi csi root
To guarantee that we do not get Overflow in image FIFO the outer bandwidth has
to be faster than inputer bandwidth. For that it must be possible to set a
faster frequency clock. So set new parent to sys_pfd3 clock for the mipi csi
block.

Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01 12:41:32 -07:00
Rui Miguel Silva 4dd5d5b520 clk: imx7d: fix mipi dphy div parent
Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a orphan
clock and set the correct parent.

before:
cat clk_orphan_summary
                                 enable  prepare  protect
   clock                          count    count    count        rate   accuracy   phase
----------------------------------------------------------------------------------------
 mipi_dphy_post_div                   1        1        0           0          0 0
    mipi_dphy_root_clk                1        1        0           0          0 0

cat clk_dump | grep mipi_dphy
mipi_dphy_post_div                    1        1        0           0          0 0
    mipi_dphy_root_clk                1        1        0           0          0 0

after:
cat clk_dump | grep mipi_dphy
   mipi_dphy_src                     1        1        0    24000000          0 0
       mipi_dphy_cg                  1        1        0    24000000          0 0
          mipi_dphy_pre_div          1        1        0    24000000          0 0
             mipi_dphy_post_div      1        1        0    24000000          0 0
                mipi_dphy_root_clk   1        1        0    24000000          0 0

Fixes: 8f6d8094b2 ("ARM: imx: add imx7d clk tree support")
Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01 12:41:24 -07:00
Anson Huang 9c7150daff clk: imx7d: correct enet clock CCGR registers
Correct enet clock gates as below:

CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK

Just rename unused IMX7D_ENETx_REF_ROOT_CLK for
IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks.

Based on Andy Duan's patch from the NXP kernel tree.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01 12:15:21 -07:00
Anson Huang f93f2ed94a clk: imx7d: correct enet phy ref clock gates
IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY directly,
there is no clock gate after it, rename it to
IMX7D_ENET_PHY_REF_ROOT_CLK to avoid device tree change.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-06-01 12:14:32 -07:00
Dong Aisheng 8d41e6538c clk: imx7d: Move clks_init_on before any clock operations
For init on clocks we should move it at the first place in imx7d_clocks_init()
before any clock operations, else the clock operation may fail in case the clock
is still not on.

Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 10:14:04 -07:00
Anson Huang a12ec8b653 clk: imx7d: Correct ahb clk parent select
Design team change the ahb's clk parent options but
did NOT update the DOC accordingly in time, so the
AHB/IPG's clk rate in clk tree is incorrect, AHB is
67.5MHz and IPG is 33.75MHz, but using scope to
monitor them, they are actually 135MHz and 67.5MHz,
update the clk parent option to make clk tree info
correct.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 10:14:03 -07:00
Anson Huang afe7c08a03 clk: imx7d: Correct dram pll type
DRAM PLL is a audio/video type PLL, need to correct
it to get correct ops of PLL.

There is a test_div placed before DRAM PLL's gate, so
add this test div clk.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 10:13:59 -07:00
Peter Chen 5fcb4c76bb clk: imx7d: Add USB clock information
Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM
which is the output of USBOTG2 PHY.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-04-06 10:13:55 -07:00
Stephen Boyd cc4d07a411 i.MX clock misc updates for 4.17:
- A correction on i.MX6SX CKO clock mux options.
  - A fix on i.MX7D Video PLL clock tree to include the missing dividers.
  - Update i.MX6UL/ULL clock driver to add epdc_podf instead of sim_podf
    clock for i.MX6ULL.
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Merge tag 'clk-imx-4.17-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx

Pull i.MX clock misc updates from Shawn Guo:

 - A correction on i.MX6SX CKO clock mux options.
 - A fix on i.MX7D Video PLL clock tree to include the missing dividers.
 - Update i.MX6UL/ULL clock driver to add epdc_podf instead of sim_podf
   clock for i.MX6ULL.

* tag 'clk-imx-4.17-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx6ull: Add epdc_podf instead of sim_podf
  clk: imx: imx7d: correct video pll clock tree
  clk: imx: imx6sx: update cko mux options
2018-03-14 15:14:08 -07:00
Anson Huang b716aad97e clk: imx: imx7d: correct video pll clock tree
There is a test divider and post divider in video PLL,
test divider is placed before post divider, all clocks
that can select parent from video PLL should be from
post divider, NOT from pll_video_main, below are
clock tree dump before and after this patch:

Before:
pll_video_main
   pll_video_main_bypass
      pll_video_main_clk
         lcdif_pixel_src
            lcdif_pixel_cg
               lcdif_pixel_pre_div
                  lcdif_pixel_post_div
                     lcdif_pixel_root_clk
After:
pll_video_main
   pll_video_main_bypass
      pll_video_main_clk
         pll_video_test_div
            pll_video_post_div
               lcdif_pixel_src
                  lcdif_pixel_cg
                     lcdif_pixel_pre_div
                        lcdif_pixel_post_div
                           lcdif_pixel_root_clk

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-03-01 08:13:38 +08:00
Stefan Agner 1691cc375a clk: imx: imx7d: add the Keypad Port module clock
According to the i.MX7D Reference Manual, the Keypad Port module
(KPP) requires this clock gate to be enabled.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-28 14:43:00 +08:00
Rui Miguel Silva baf15cbf54 clk: imx7d: add CAAM clock
Add CAAM clock so that we could use the Cryptographic Acceleration and
Assurance Module (CAAM) hardware block.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: "Horia Geantă" <horia.geanta@nxp.com>
Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-28 09:17:41 +08:00
Anson Huang d931ba53e0 clk: imx: imx7d: add the snvs clock
According to the i.MX7D Reference Manual,
SNVS block has a clock gate, accessing SNVS block
would need this clock gate to be enabled, add it
into clock tree so that SNVS module driver can
operate this clock gate.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-02-22 17:46:58 +08:00
Adriana Reus 259bc28306 clk: imx: imx7d: Remove ARM_M0 clock
IMX7d does not have an M0 Core and this particular
clock doesn't seem connected to anything else.
Remove this entry from the CCM driver.

Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-11-02 00:26:18 -07:00
Adriana Reus edc5a8e754 clk: imx: imx7d: Fix parent clock for OCRAM_CLK
The parent of OCRAM_CLK should be axi_main_root_clk
and not axi_post_div.

before:

    axi_src                     1       1       332307692       0 0
      axi_cg                    1       1       332307692       0 0
        axi_pre_div             1       1       332307692       0 0
          axi_post_div          1       1       332307692       0 0
            ocram_clk           0       0       332307692       0 0
            main_axi_root_clk   1       1       332307692       0 0

after:

    axi_src                     1       1       332307692       0 0
      axi_cg                    1       1       332307692       0 0
        axi_pre_div             1       1       332307692       0 0
          axi_post_div          1       1       332307692       0 0
            main_axi_root_clk   1       1       332307692       0 0
              ocram_clk         0       0       332307692       0 0

Reference Doc: i.MX 7D Reference Manual - Chap 5, p 516
(https://www.nxp.com/docs/en/reference-manual/IMX7DRM.pdf)

Fixes: 8f6d8094b2 ("ARM: imx: add imx7d clk tree support")
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-11-02 00:26:14 -07:00
Arvind Yadav fdda6ee947 clk: imx: constify clk_div_table
clk_div_table are not supposed to change at runtime. All functions
working with clk_div_table provided by <linux/clk-provider.h> work
with const clk_div_table. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30 22:30:27 -07:00
Stefan Agner 22039d150f clk: imx7d: create clocks behind rawnand clock gate
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
and NAND_CLK_ROOT. However, the gate has been in the chain of the
latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
only, e.g. as required by APBH-Bridge-DMA.

Add new clocks which represent the clock after the gate, and use a
shared clock gate to correctly model the hardware.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:41 -07:00
Fabio Estevam ad14972422 clk: imx7d: Fix the powerdown bit location of PLL DDR
According to the MX7D Reference Manual the powerdown bit of
CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-01 00:25:38 -07:00
Stefan Agner e24f5287cd clk: imx7d: fix USDHC NAND clock
The USDHC NAND root clock is not gated by any CCM clock gate. Remove
the bogus gate definition.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:44:14 -07:00
Dong Aisheng 40e00eff79 clk: imx7d: add the missing ipg_root_clk
Add the missing ipg_root_clk which actually is already used by many
orphan clks in current tree.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:10:23 -07:00
Dong Aisheng 9a6e904226 clk: clk-imx7d: fix ahb clk definition
MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200
used actually is for adc, not ahb. After fix, correct ocram_s_clk
parent accordingly as well.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19 09:10:12 -07:00
Fabio Estevam 6847c4c296 clk: imx7d: Add the OCOTP clock
Add the OCOTP so that this hardware block can be used.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-20 16:27:19 -08:00
Fabio Estevam 54fe0791fa clk: imx7d: Add PLL_AUDIO_TEST_DIV/POST_DIV clocks
Currently we see the following error when using the SAI audio
driver on mx7:

Division by zero in kernel.
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0-rc3-next-20160823
Hardware name: Freescale i.MX7 Dual (Device Tree)
Backtrace:
[<c010b70c>] (dump_backtrace) from [<c010b8a8>] (show_stack+0x18)
r6:60000013 r5:ffffffff r4:00000000 r3:00000000
[<c010b890>] (show_stack) from [<c03e9324>] (dump_stack+0xb0/0xe)
[<c03e9274>] (dump_stack) from [<c010b578>] (__div0+0x18/0x20)
r8:00000000 r7:ffffffff r6:ffffffff r5:00000000 r4:00000000 r3:0
[<c010b560>] (__div0) from [<c03e795c>] (Ldiv0_64+0x8/0x18)
[<c06cd860>] (divider_get_val) from [<c06cda28>] (clk_divider_se)

This error happens due to the lack of definition of the
IMX7D_PLL_AUDIO_TEST_DIV/IMX7D_PLL_AUDIO_POST_DIV clocks.

Add support for them.

Tested on a imx7s-warp board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-30 14:58:15 -07:00
Fabio Estevam 0698102576 clk: imx7d: Add SAI IPG clocks
The SAI_IPG clocks are enabled by the same bits that control SAI_ROOT_CLK
clocks, so represent them as shared clocks.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19 12:53:43 -07:00
Fabio Estevam 96e9dff6dd clk: imx7d: Add the clock for SDMA
Add IMX7D_SDMA_CORE_CLK clock so that SDMA can be functional.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19 12:53:36 -07:00
Fabio Estevam 1fd92dbaab clk: imx7d: do not set the parent of IMX7D_ENET_AXI_ROOT_SRC
Booting the kernel on a imx7s-warp leads to several warnings like these:

[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:3536 lock_release+0x2f8/0x330
[    0.000000] releasing a pinned lock

[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:2722 trace_hardirqs_on_caller+0x1ac/0x1f4
[    0.000000] DEBUG_LOCKS_WARN_ON(unlikely(early_boot_irqs_disabled))

[    0.000000] ---[ end trace cb88537fdc8fa201 ]---
[    0.000000] bad: scheduling from the idle thread!
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W       4.7.0-rc7-next-20160715 #404

[    0.000000] ------------[ cut here ]------------
[    0.000000] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8
[    0.000000] Modules linked in:

[    0.000591] ------------[ cut here ]------------
[    0.000610] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8

[    0.002084] ------------[ cut here ]------------
[    0.002104] WARNING: CPU: 0 PID: 0 at init/main.c:576 start_kernel+0x258/0x3b0
[    0.002114] Interrupts were enabled early

This fix is along the same lines as 5e33ebff7e ("clk: imx7d: do not
set parent of ethernet time/ref clocks") and the explanation from that
commit is:

"The reason for the warning is that setting the parent enables the ENET
 PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can
 cause clk_pllv3_wait_lock to sleep. See also:
 commit fc8726a2c0 ("clk: core: support clocks which requires parents
 enable (part 2)")."

imx7s-warp does not even use the FEC interface, so we should not really
configure the parent of IMX7D_ENET_AXI_ROOT_SRC in the common MX7 clock
driver code.

The dts file should use the assigned-clocks/assigned-clock-parents method,
so simply remove the configuration of IMX7D_ENET_AXI_ROOT_SRC parent.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-11 18:49:20 -07:00
Stefan Agner 5e33ebff7e clk: imx7d: do not set parent of ethernet time/ref clocks
All device trees currently in mainline specify the time clock parent
using the assigned-clocks/assigned-clock-parents method, there is no
need to statically assign the parent in the core clock driver.
Also all current boards provide an Ethernet reference clock for the
PHY externally, hence configuring the internal PHY reference clock.

Furthermore, and the actual driver of this patch, specify ethernet
related parents at that early point in boot leads to a warning:
bad: scheduling from the idle thread!

The reason for the warning is that setting the parent enables the ENET
PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can
cause clk_pllv3_wait_lock to sleep. See also:
commit fc8726a2c0 ("clk: core: support clocks which requires parents
enable (part 2)").

Note that setting the ENET AXI root clock parent also requires ENET
PLL to be enabled. However, U-Boot typically leaves the ENET PLL on,
hence when the framework sets the parent of the first clock, it does
not need to wait for the PLL to come up. But because there is currently
no user of that clock, the PLL gets disabled after setting the parent.
Therefore, subsequent reparenting calls of any clock which somehow rely
on the ENET PLL, need to reenable the ENET PLL which leads to a sleep.
Removing those subsequent reparenting calls works around this issue.

Also remove comments. The code is really verbose enough.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160703174813.13970-1-stefan@agner.ch
2016-07-12 15:31:14 -07:00
Dong Aisheng e8e628fb3f clk: imx7d: only enable minimum required clocks
Formerly clk core does not support imx7d clock type well that all
its clock operations requires the parent clock on.
Therefore we enabled all clocks by default in clock driver
initialization for other module clocks operate well.

After patch 'clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE',
clk core can handle such clock type well, so we don't have to enable
them all by default anymore. Instead, we only enable a minimum required
set of clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01 17:43:21 -07:00
Dong Aisheng cbeac74a58 clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE
i.MX7D requires all clocks operations including enable/disable,
rate change and re-parent with its parent clock on.
Changing to the correct APIs to tell clk core such requirement.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-01 17:43:20 -07:00
Dong Aisheng f83d31635c clk: imx: fix pll clock parents
pllx_bypass_src mux shouldn't be the parent of pllx clock
since it's only valid when when pllx BYPASS bit is set.
Thus it is actually one parent of pllx_bypass only.

Instead, pllx parent should be fixed to osc according to
reference manual.
Other plls have the same issue.

e.g. before fix, the pll tree is:
osc                                      6            6    24000000          0 0
   pll1_bypass_src                       0            0    24000000          0 0
      pll1                               0            0   792000000          0 0
         pll1_bypass                     0            0   792000000          0 0
            pll1_sys                     0            0   792000000          0 0

After the fix, it's:
osc                                      6            6    24000000          0 0
   pll1                                  0            0   792000000          0 0
      pll1_bypass                        0            0   792000000          0 0
         pll1_sys                        0            0   792000000          0 0

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12 21:21:41 +08:00
Anson Huang 1479475495 clk: imx7d: correct dram pll type
DRAM PLL is a audio/video type PLL, need to correct
it to get correct ops of PLL.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12 19:26:05 +08:00
Anson Huang 7e797d9fc8 clk: imx7d: correct dram root clk parent select
DRAM root clk should be either from pll dram main clk
or dram alt root clk.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-06-12 19:26:01 +08:00
Stefan Agner 92a847e360 clk: imx7d: fix ahb clock mux 1
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in  Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.

While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-05-03 20:35:38 +08:00
Gary Bisson 4aba2755b8 clk: imx: add ckil clock for i.MX7
Add the necessary clock to use the ckil on i.MX7.

Inspired from the following patch:
https://github.com/boundarydevices/linux-imx6/commit/b80e8271

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-06 17:04:26 +08:00
Bai Ping 31cbb57d5a clk: imx: Replace clk error check with imx_check_clocks()
As we already have a 'imx_check_clocks' to do the clock error
check, so cleanup the error check code.

Signed-off-by: Bai Ping <b51503@freescale.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-12-02 14:10:25 +08:00
Bai Ping fdb868cd05 clk: imx: Add a virtual arm clk on i.mx7d
Add a virtual arm clk to abstract the actual steps
when changing the ARM core frequency.So we can using
the 'cpufreq-dt' driver on i.MX7D/Solo.

Signed-off-by: Bai Ping <b51503@freescale.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-12-02 13:34:01 +08:00
Haibo Chen ab4c6a2407 clk: imx7d: add ADC root clock
Add ADC root clock support in imx7d clock tree.

Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-10-09 11:01:50 +08:00
Lucas Stach 1b9af68f32 clk: imx7d: retain early UART clocks during kernel init
Make sure to keep UART clocks enabled during kernel init if
earlyprintk or earlycon are active.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2015-09-25 21:59:06 -07:00
Frank Li 8f6d8094b2 ARM: imx: add imx7d clk tree support
Add i.MX7D clk tree support.

Enable all clock to bring up imx7.
Clock framework need be modified a little since imx7d
change clock design. otherwise system will halt and block the
other part upstream.

All clock refine need wait for Dong Aisheng's patch
clk: support clocks which requires parent clock on during operation
Or other solution ready.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-06-03 14:49:37 +08:00