Commit Graph

20 Commits

Author SHA1 Message Date
Chunyan Zhang 1ded879e12 clk: move clock common macros out from vendor directories
These macros are used by more than one SoC vendor platforms, avoid to
have many copies of these code, this patch moves them to the common
header file which every clock drivers can access to.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-12-21 15:00:38 -08:00
Arvind Yadav 59273246b2 clk: zte: constify clk_div_table
clk_div_table are not supposed to change at runtime. All functions
working with clk_div_table provided by <linux/clk-provider.h> work
with const clk_div_table. So mark the non-const structs as const.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-30 22:30:30 -07:00
Shawn Guo 6454504c80 clk: zx296718: export I2S mux clocks
Export I2S mux clocks, so that device tree can refer to them for setting
a better parent clock for I2S work clock.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19 19:02:42 -07:00
Stephen Boyd 15a2a14b23 clk: zte: Mark pll config tables as const
These should be const.

Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2017-04-12 18:51:34 +02:00
Shawn Guo a90099da3c clk: zte: add pll_vga clock for zx296718
It adds zx296718 pll_vga clock for VGA support, so that VGA device can
get required pixel rate from clock driver for different display mode.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2017-04-12 18:51:33 +02:00
Shawn Guo ee249cbe42 clk: zte: pd_bit is not 0 on zx296718
The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
of postdiv2 field.  The consequence is that functions like hw_to_idx()
and zx_pll_enable() will end up tampering the postdiv2 of the PLL.

Let's fix it by defining pd_bit 0xff which is obviously invalid for a
bit position and having PLL driver check the validity before operating
on the bit.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2017-04-12 18:51:31 +02:00
Shawn Guo 5790d80176 clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
To support VOU VGA display driver with different modes, we need to set
flag for a few clocks, so that clk_set_rate() call in VOU driver can get
VGA device desired pixel rate.

While at it, the divider between pll_vga and clk_vga gets corrected, as
it's 1:1 instead of 1:2.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2017-04-12 18:51:29 +02:00
Baoyou Xie 48239135dd clk: zte: add i2s clocks for zx296718
The i2s related clock support is missing from the existing zx296718
clock driver. This patch adds it, so that the upstream ZX I2S driver
can work out.

Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-10 09:17:38 -08:00
Jun Nie edc6da239a clk: zte: add audio clocks for zx296718
The audio related clock support is missing from the existing zx296718
clock driver.  Let's add it, so that the upstream ZX SPDIF driver can
work for HDMI audio support.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[sboyd@codeaurora.org: Staticize some more structures]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09 16:06:43 -08:00
Shawn Guo 26f6b0b771 clk: zx296718: do not panic on failure
Instead of using panic, we should give an error message and return error
code when of_clk_add_hw_provider() call fails.

Since we have error prompt for failures, the "init over" pr_info output
isn't really necessary but becomes a debug noise.  So let's clean it up
along the way.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09 16:06:42 -08:00
Shawn Guo c72f2883c3 clk: zx296718: register driver earlier with core_initcall
Clock driver should be registered with an earlier initcall than
module_init which is used by most of client device drivers.  Otherwise,
probing of these client drivers will likely be deferred due to that
calls into clk API will return -EPROBE_DEFER.

Deferred probing is not a problem for most subsystems, but could bring
some side effect for particular subsystem, like display.  On ZX296718
platform, we get Linux logo and boot log lost from display device, just
because the DRM/KMS driver gets -EPROBE_DEFER from devm_clk_get() call.

Let's use core_initcall (qcom and a few other clk drivers use that) for
driver registration to avoid those unnecessary -EPROBE_DEFER and get rid
of the side effect with ZX296718 display system.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-23 14:42:13 -07:00
Arnd Bergmann f00d2db7c4 clk: zx: fix pointer case warnings
The zx296718 clock driver has a creative way of assigning the register
values for each clock, by initializing an __iomem pointer to an
offset and then later adding the base (from ioremap) on top
with a cast to u64. This fail on all 32-bit architectures during
compile testing:

drivers/clk/zte/clk-zx296718.c: In function 'top_clocks_init':
drivers/clk/zte/clk-zx296718.c:554:35: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
   zx296718_pll_clk[i].reg_base += (u64)reg_base;
drivers/clk/zte/clk-zx296718.c:579:29: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
drivers/clk/zte/clk-zx296718.c:592:31: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]

It would be nice to avoid all the casts, but I decided to simply
shut up the warnings by changing the type from u64 to uintptr_t,
which does the right thing in practice.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: ca0233285a ("clk: zx: register ZX296718 clocks")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16 16:18:19 -07:00
Wei Yongjun faabbe50ad clk: zx296718: use builtin_platform_driver to simplify the code
Use the builtin_platform_driver() macro to make the code simpler.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-16 16:05:16 -07:00
Jun Nie ca0233285a clk: zx: register ZX296718 clocks
The ZX296718 clocks are statically listed and registered. More
clock will be added later.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14 13:50:33 -07:00
Jun Nie 8d9a0860b7 clk: zx: reform pll config info to ease code extension
Add power down bit and pll lock bit in pll config structure
to ease new SoC support.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14 13:48:32 -07:00
Stephen Boyd c9bb8a4f3d clk: zte: Remove CLK_IS_ROOT
This flag is a no-op now. Remove usage of the flag.

Cc: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15 16:50:07 -07:00
Jun Nie d99215ae06 clk: zx: Constify parent names in clock init data
The array of parent names can be made as array of const pointers to
const strings.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:59:39 -07:00
Jun Nie 105644e59a clk: zx: Add audio and GPIO clock for zx296702
Add SPDIF/I2S and GPIO clock for zx296702

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:59:37 -07:00
Jun Nie 4599dd2c92 clk: zx: Add audio div clock method for zx296702
Add SPDIF/I2S divider clock method for zx296702

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28 11:59:34 -07:00
Jun Nie 5a46580812 clk: zx: add clock support to zx296702
It adds a clock driver for zx296702 SoC to register the clock tree to
Common Clock Framework.  All the clocks of bus topology and some the
peripheral clocks are ready with this commit. Some missing leaf clocks
for peripherals will be added later when needed.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-11 16:18:08 -07:00