Commit Graph

4215 Commits

Author SHA1 Message Date
Mark Brown 14dbfb417b
Merge branch 'spi-5.1' into spi-next 2019-03-04 15:32:51 +00:00
Mark Brown b50c6ac8b6
Merge branch 'spi-5.0' into spi-linus 2019-03-04 15:32:49 +00:00
Geert Uytterhoeven 0e836c3bea
spi: sh-msiof: Restrict bits per word to 8/16/24/32 on R-Car Gen2/3
While the MSIOF variants in older SuperH and SH/R-Mobile SoCs support
bits-per-word values in the full range 8..32, the variants present in
R-Car Gen2 and Gen3 SoCs are restricted to 8, 16, 24, or 32.

Obtain the value from family-specific sh_msiof_chipdata to fix this.

Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-04 00:02:28 +00:00
Wei Yongjun daad4d2a0a
spi: sifive: Remove redundant dev_err call in sifive_spi_probe()
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-22 15:17:58 +00:00
Wei Yongjun 049e5feae1
spi: sifive: Remove spi_master_put in sifive_spi_remove()
The call to spi_master_put() in sifive_spi_remove() is redundant since
the master is registered using devm_spi_register_master() and no
reference hold by using spi_master_get() in sifive_spi_remove().

This is detected by Coccinelle semantic patch.

Fixes: 484a9a68d6 ("spi: sifive: Add driver for the SiFive SPI controller")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-22 15:17:43 +00:00
Russell King b89fefda7d
spi: spi-gpio: fix SPI_CS_HIGH capability
spi-gpio is capable of dealing with active-high chip-selects.
Unfortunately, commit 4b859db2c6 ("spi: spi-gpio: add SPI_3WIRE
support") broke this by setting master->mode_bits, which overrides
the setting in the spi-bitbang code.  Fix this.

[Fixed a trivial conflict with SPI_3WIRE_HIZ support -- broonie]

Fixes: 4b859db2c6 ("spi: spi-gpio: add SPI_3WIRE support")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
2019-02-21 19:03:35 +00:00
Mark Brown bf9f742c38
Merge branch 'for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.1 2019-02-20 17:58:18 +00:00
Andy Shevchenko ef070b4e4a
spi: pxa2xx: Setup maximum supported DMA transfer length
When the commit b6ced294fb

   ("spi: pxa2xx: Switch to SPI core DMA mapping functionality")

switches to SPI core provided DMA helpers, it missed to setup maximum
supported DMA transfer length for the controller and thus users
mistakenly try to send more data than supported with the following
warning:

  ili9341 spi-PRP0001:01: DMA disabled for transfer length 153600 greater than 65536

Setup maximum supported DMA transfer length in order to make users know
the limit.

Fixes: b6ced294fb ("spi: pxa2xx: Switch to SPI core DMA mapping functionality")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
2019-02-20 17:14:14 +00:00
Yash Shah 484a9a68d6
spi: sifive: Add driver for the SiFive SPI controller
Add driver for the SiFive SPI controller
on the HiFive Unleashed board.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-19 15:28:53 +00:00
Baolin Wang 5e060c48bc
spi: sprd: Add a prefix for SPI DMA channel macros
Add a prefix for SPI DMA channel macros to avoid namespace conflicts,
and no functional changes.

Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-13 15:41:01 +00:00
Lanqing Liu 386119bc7b
spi: sprd: spi: sprd: Add DMA mode support
Add DMA mode support for the Spreadtrum SPI controller, and we will enable
SPI interrupt to help to complete the SPI transfer work in DMA mode.

Signed-off-by: Lanqing Liu <lanqing.liu@unisoc.com>
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-13 12:20:59 +00:00
Lanqing Liu de082d866c
spi: sprd: Add the SPI irq function for the SPI DMA mode
The SPI irq event will use to complete the SPI work in the SPI DMA mode,
so this patch is a preparation for the following DMA mode support.

Moreover the SPI interrupt can be fired when removing the SPI controller,
so we should make sure the SPI controller has stopped the queue in
remove function before freeing the SPI irq.

Signed-off-by: Lanqing Liu <lanqing.liu@unisoc.com>
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-13 12:20:28 +00:00
Felix Fietkau 28f7604f48
spi: use gpio[d]_set_value_cansleep for setting chipselect GPIO
Sleeping is safe inside spi_transfer_one_message, and some
GPIO chips are running on slow busses (such as I2C GPIO
expanders) and need to sleep for setting values.

Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-12 16:41:11 +00:00
Jonathan Neuschäfer 9b4f84212f
spi: gpio: Advertise support for SPI_CS_HIGH
The spi-gpio driver already handles different chip select polarities,
but so far this was not advertised in master->mode_bits.

This patch fixes mmc_spi on top of spi_gpio, which is useful in some
testing scenarios.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-12 16:41:10 +00:00
Geert Uytterhoeven 35c35fd925
spi: sh-msiof: Replace spi_master by spi_controller
As of commit 8caab75fd2 ('spi: Generalize SPI "master" to
"controller"'), the old master-centric names are compatibility wrappers
for the new controller-centric names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-08 13:04:32 +00:00
Geert Uytterhoeven 5a0e577fc9
spi: sh-hspi: Replace spi_master by spi_controller
As of commit 8caab75fd2 ('spi: Generalize SPI "master" to
"controller"'), the old master-centric names are compatibility wrappers
for the new controller-centric names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-08 13:04:19 +00:00
Geert Uytterhoeven 9428a073eb
spi: rspi: Replace spi_master by spi_controller
As of commit 8caab75fd2 ('spi: Generalize SPI "master" to
"controller"'), the old master-centric names are compatibility wrappers
for the new controller-centric names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-08 13:02:19 +00:00
Tudor Ambarus 2e5c888873
spi: atmel-quadspi: add support for sam9x60 qspi controller
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory. It uses
different transfer type bits in IFR register. It has dedicated registers
to specify a read or a write instruction: Read Instruction Code Register
(RICR) and Write Instruction Code Register (WICR). ICR/RICR/WICR have
identical fields.

Tested with sst26vf064b jedec,spi-nor flash. Backward compatibility test
done on sama5d2 qspi controller and mx25l25635e jedec,spi-nor flash.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 17:21:00 +00:00
Tudor Ambarus bd7905e2fe
spi: atmel-quadspi: add support for named peripheral clock
Naming clocks is a good practice. Keep supporting unnamed
peripheral clock, to be backward compatible with old DTs.
While here, rename clk to pclk, to indicate that it is a
peripheral clock.

Suggested-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 17:20:59 +00:00
Tudor Ambarus b456fd18ca
spi: atmel-quadspi: rework transfer macros
Split the TFRTYP_TRSFR_ bitfields in 2: one bit encoding the
mem/reg transfer type and one bit encoding the direction of
the transfer (read/write).

Remove NOP when setting read transfer type. Remove useless
setting of write transfer type when
op->data.dir == SPI_MEM_DATA_IN && !op->data.nbytes.

QSPI_IFR_TFRTYP_TRSFR_WRITE is specific just to sama5d2 qspi,
rename it to QSPI_IFR_SAMA5D2_WRITE_TRSFR.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 17:20:40 +00:00
Tudor Ambarus cae417b2a8
spi: atmel-quadspi: switch to SPDX license identifiers
Adopt the SPDX license identifiers to ease license compliance
management.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 17:19:22 +00:00
Tudor Ambarus 2aaa8dd093
spi: atmel-quadspi: return appropriate error code
Return -ENOTSUPP when atmel_qspi_find_mode() fails. Propagate
the error in atmel_qspi_exec_op().

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 17:19:14 +00:00
Tudor Ambarus 9ce4c5128b
spi: atmel-quadspi: remove unnecessary cast
The cast is done implicitly.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 17:19:06 +00:00
Tudor Ambarus 1db6de22b2
spi: atmel-quadspi: fix naming scheme
Let general names to core drivers.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 17:18:57 +00:00
Tudor Ambarus 18b6f6e176
spi: atmel-quadspi: drop wrappers for iomem accesses
The wrappers hid that the accesses are relaxed. Drop them.

Suggested-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 17:18:49 +00:00
Tudor Ambarus 3ae012e9df
spi: atmel-quadspi: order header files inclusion alphabetically
Cosmetic change, no functional change.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 17:18:41 +00:00
Tudor Ambarus 9958c8c39e
spi: atmel-quadspi: cache MR value to avoid a write access
Set the controller by default in Serial Memory Mode (SMM) at probe.
Cache Mode Register (MR) value to avoid write access when setting
the controller in serial memory mode at exec_op().

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 17:16:41 +00:00
Lukasz Majewski 5ce3cc5674
spi: spi-fsl-dspi: Provide support for DSPI slave mode operation (Vybryd vf610)
The NXP's Vybryd vf610 can work as a SPI slave device (the CS and clock
signals are provided by master).

It is possible to specify a single device to work in that mode. As we do
use DMA for transferring data, the RX channel must be prepared for
incoming data.
Moreover, in slave mode we just set a subset of control fields in
configuration registers (CTAR0, PUSHR).

For testing the spidev_test program has been used.
Test script for this patch can be found here:
https://github.com/lmajewski/tests-spi/blob/master/tests/spi/spi_tests.sh

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06 16:47:38 +00:00
Jonas Bonn 473a78a7bb
spi-atmel: support inter-word delay
If the SPI slave requires an inter-word delay, configure the DLYBCT
register accordingly.

Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
board).

Signed-off-by: Jonas Bonn <jonas@norrbonn.se>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
CC: Nicolas Ferre <nicolas.ferre@microchip.com>
CC: Mark Brown <broonie@kernel.org>
CC: Alexandre Belloni <alexandre.belloni@bootlin.com>
CC: Ludovic Desroches <ludovic.desroches@microchip.com>
CC: linux-spi@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-30 23:02:11 +00:00
Jonas Bonn b7bb367afa
spi: support inter-word delay requirement for devices
Some devices are slow and cannot keep up with the SPI bus and therefore
require a short delay between words of the SPI transfer.

The example of this that I'm looking at is a SAMA5D2 with a minimum SPI
clock of 400kHz talking to an AVR-based SPI slave.  The AVR cannot put
bytes on the bus fast enough to keep up with the SoC's SPI controller
even at the lowest bus speed.

This patch introduces the ability to specify a required inter-word
delay for SPI devices.  It is up to the controller driver to configure
itself accordingly in order to introduce the requested delay.

Note that, for spi_transfer, there is already a field word_delay that
provides similar functionality.  This field, however, is specified in
clock cycles (and worse, SPI controller cycles, not SCK cycles); that
makes this value dependent on the master clock instead of the device
clock for which the delay is intended to provide some relief.  This
patch leaves this old word_delay in place and provides a time-based
word_delay_us alongside it; the new field fits in the struct padding
so struct size is constant.  There is only one in-kernel user of the
word_delay field and presumably that driver could be reworked to use
the time-based value instead.

The time-based delay is limited to 8 bits as these delays are intended
to be short.  The SAMA5D2 that I've tested this on limits delays to a
maximum of ~100us, which is already many word-transfer periods even at
the minimum transfer speed supported by the controller.

Signed-off-by: Jonas Bonn <jonas@norrbonn.se>
CC: Mark Brown <broonie@kernel.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Mark Rutland <mark.rutland@arm.com>
CC: linux-spi@vger.kernel.org
CC: devicetree@vger.kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-30 23:02:10 +00:00
Uwe Kleine-König f3fdea3af4
spi: mxs: add tracing to custom .transfer_one_message callback
Driver specific implementations for .transfer_one_message need to call
the tracing stuff themself. This is necessary to make spi tracing
actually useful.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-29 15:08:58 +00:00
Yogesh Narayan Gaur c55d0e8c54
spi: spi-mem: spi-fsl-qspi: typo fix in author name
Typo fix in Author Boris Brezillon last name and update with new
email address.

Fixes: 84d043185d ("spi: Add a driver for the Freescale/NXP QuadSPI controller")
Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-29 12:12:03 +00:00
Vignesh R 673c865efb
spi: ti-qspi: Fix mmap read when more than one CS in use
Commit 4dea6c9b0b ("spi: spi-ti-qspi: add mmap mode read support") has
has got order of parameter wrong when calling regmap_update_bits() to
select CS for mmap access. Mask and value arguments are interchanged.
Code will work on a system with single slave, but fails when more than
one CS is in use. Fix this by correcting the order of parameters when
calling regmap_update_bits().

Fixes: 4dea6c9b0b ("spi: spi-ti-qspi: add mmap mode read support")
Cc: stable@vger.kernel.org
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-29 12:08:03 +00:00
Yogesh Narayan Gaur ce6f0697eb
spi: spi-mem: spi-nxp-fspi: add module license info
Add MODULE_LICENSE info to fix below warning:
WARNING: modpost: missing MODULE_LICENSE() in drivers/spi/spi-nxp-fspi.o

Typo fix in Boris Brezillon last name.

Fixes: a5356aef6a ("spi: spi-mem: Add driver for NXP FlexSPI controller")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-29 11:55:41 +00:00
Jiwei Sun 7aef2b646b
spi: pl022: add a message state STATE_TIMEOUT for timeout transfer
When transfer timeout, give -EAGAIN to the message's status, and it can
make the spi device driver choose repeated transimation or not. And if
transfer timeout, output some useful information for tracing the issue.

Signed-off-by: Jiwei Sun <jiwei.sun@windriver.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-28 18:23:04 +00:00
Fabio Estevam 2e236bafab
spi: Kconfig: imx: Update the help text to make it more generic
The spi-imx driver supports both master and slave modes, so update
the help text to make it more generic.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-28 17:58:11 +00:00
Yogesh Narayan Gaur b328179447
spi: nxp-fspi: add octal mode flag bit for octal support
Add octal mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports 8 lines Rx/Tx data transfer.

Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-28 12:28:46 +00:00
Yogesh Narayan Gaur a5356aef6a
spi: spi-mem: Add driver for NXP FlexSPI controller
- Add driver for NXP FlexSPI host controller

(0) What is the FlexSPI controller?
 FlexSPI is a flexsible SPI host controller which supports two SPI
 channels and up to 4 external devices. Each channel supports
 Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
 data lines) i.e. FlexSPI acts as an interface to external devices,
 maximum 4, each with up to 8 bidirectional data lines.

 It uses new SPI memory interface of the SPI framework to issue
 flash memory operations to up to four connected flash
 devices (2 buses with 2 CS each).

(1) Tested this driver with the mtd_debug and JFFS2 filesystem utility
 on NXP LX2160ARDB and LX2160AQDS targets.
 LX2160ARDB is having two NOR slave device connected on single bus A
 i.e. A0 and A1 (CS0 and CS1).
 LX2160AQDS is having two NOR slave device connected on separate buses
 one flash on A0 and second on B1 i.e. (CS0 and CS3).
 Verified this driver on following SPI NOR flashes:
    Micron, mt35xu512ab, [Read - 1 bit mode]
    Cypress, s25fl512s, [Read - 1/2/4 bit mode]

Signed-off-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Boris Brezillon <bbrezillon@kernel.org>
Tested-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-28 12:27:44 +00:00
Linus Walleij 6046f5407f
spi: cadence: Fix default polarity of native chipselect
The Cadence controller also supports platforms specifying
native chipselects. When I enforce the use of high CS
for drivers opting in for using GPIO descriptors, I
inadvertedly switched the driver to also use active
high chip select for native chip selects.

Fix this by inverting the logic in the callback for the
native chip select. Rename the parameter from "is_high"
(which is interpreted as being high when 0, which is
confusing, I will not make any drug-related jokes here)
to "enabled" which is more intuitive, especially now that
it is true when CS is supposed to be enabled.

Cc: Wei Yongjun <weiyongjun1@huawei.com>
Fixes: cfeefa79dc ("spi: cadence: Convert to use CS GPIO descriptors")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-24 19:03:11 +00:00
Linus Walleij 6e0a32d6f3
spi: dw: Fix default polarity of native chipselect
The DW controller also supports platforms specifying
native chipselects. When I enforce the use of high CS
for drivers opting in for using GPIO descriptors, I
inadvertedly switched the driver to also use active
high chip select for native chip selects.

As it turns out, the DW hardware driving chip selects
also thinks it is weird with active low chip selects
so all we need to do is remove an inversion in the
driver.

Cc: Jan Kotas <jank@cadence.com>
Reported-by: Jan Kotas <jank@cadence.com>
Tested-by: Jan Kotas <jank@cadence.com>
Fixes: 9400c41e77 ("spi: dw: Convert to use CS GPIO descriptors")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-24 19:02:58 +00:00
Linus Walleij 2df201e006
spi: Support high CS when using descriptors
All controllers using GPIO descriptors can by definition
support high CS connections, so just enforce this when
registering an SPI controller.

This fixes a regression where controllers were missing
SPI_CS_HIGH, the drivers would fail like this:

spi spi0.0: setup: unsupported mode bits 4
cdns-spi fd0b0000.spi: can't setup spi0.0, status -22

This is because as using descriptors moves the CS inversion
logic over to gpiolib, all such controllers are registered
with CS active high.

Cc: Jan Kotas <jank@cadence.com>
Reported-by: Jan Kotas <jank@cadence.com>
Tested-by: Jan Kotas <jank@cadence.com>
Fixes: f3186dd876 ("spi: Optionally use GPIO descriptors for CS GPIOs")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-24 19:01:05 +00:00
Mark Brown f0125f1a55
spi: Go back to immediate teardown
Commit 412e603732 ("spi: core: avoid waking pump thread from spi_sync
instead run teardown delayed") introduced regressions on some boards,
apparently connected to spi_mem not triggering shutdown properly any
more.  Since we've thus far been unable to figure out exactly where the
breakage is revert the optimisation for now.

Reported-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: kernel@martin.sperl.org
2019-01-23 17:29:53 +00:00
YueHaibing e902cdcb51
spi/topcliff_pch: Fix potential NULL dereference on allocation error
In pch_spi_handle_dma, it doesn't check for NULL returns of kcalloc
so it would result in an Oops.

Fixes: c37f3c2749 ("spi/topcliff_pch: DMA support")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-23 15:45:37 +00:00
Lubomir Rintel 51eea52d26
pxa2xx: replace spi_master with spi_controller
It's also a slave controller driver now, calling it "master" is slightly
misleading.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-23 10:59:56 +00:00
YueHaibing bfc7af6d6d
spi: bcm2835aux: remove unneeded NULL check of devm_clk_get
Fix a static code checker warning:
drivers/spi/spi-bcm2835aux.c:460
 bcm2835aux_spi_probe() warn: passing zero to 'PTR_ERR'

In case of error, the function devm_clk_get() returns ERR_PTR()
and not returns NULL.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-23 10:31:21 +00:00
Boris Brezillon 1fc1b63638
spi: spi-mem: Add devm_spi_mem_dirmap_{create,destroy}()
Since direct mapping descriptors usually the same lifetime as the SPI
MEM device adding devm_ variants of the spi_mem_dirmap_{create,destroy}()
should greatly simplify error/remove path of spi-mem drivers making use
of the direct mapping API.

Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-21 17:58:12 +00:00
Boris Brezillon bfecfd6e23
spi: spi-mem: Fix a memory leak in spi_mem_dirmap_destroy()
The dirmap descriptor object allocated in spi_mem_dirmap_create is
never freed. Add a kfree(desc) in spi_mem_dirmap_destroy().

Fixes: aa167f3fed ("spi: spi-mem: Add a new API to support direct mapping")
Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-21 17:57:14 +00:00
Boris Brezillon 5c0c4ec9ba
spi: spi-mem: Fix spi_mem_dirmap_destroy() kerneldoc
spi_mem_dirmap_destroy() takes a single argument, remove the @info entry
in the doc.

Fixes: aa167f3fed ("spi: spi-mem: Add a new API to support direct mapping")
Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-21 17:55:17 +00:00
Hoan Nguyen An d05e3eadb1
spi: sh-msiof: Use DMA if possible
Currently, this driver only supports feature for DMA 32-bits.
In this case, only if the data length is divisible by 4 to use
DMA, otherwise PIO will be used. This patch will suggest use
the DMA 32-bits with 4bytes of words, then the remaining data
will be transmitted by PIO mode.

Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-18 18:20:52 +00:00
Hoan Nguyen An f70351ae06
spi: sh-msiof: fix *info pointer in request_dma()
sh_msiof_spi_info *info struct pointer was initialized in the probe() function
no need to get back and keep consistency.

Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-01-18 18:20:39 +00:00