Commit Graph

55 Commits

Author SHA1 Message Date
Keith Packard 92b79f4322 drm/i915: Cannot set clock gating under UMS
The clock gating functions are only assigned under KMS, so don't try
to call them under UMS.

Signed-off-by: Keith Packard <keithp@keithp.com>
Tested-by: Justin P. Mattock <justinmattock@gmail.com>
2011-08-15 12:10:27 -07:00
Keith Packard 9b546e571b Merge branch 'drm-intel-fixes' into drm-intel-next 2011-07-29 16:24:10 -07:00
Adam Jackson cda2bb78c2 drm/i915/pch: Save/restore PCH_PORT_HOTPLUG across suspend
At least on a Lenovo X220 the HPD bits of this are enabled at boot but
cleared after resume, which means plug interrupts stop working.

This also happens to fix DP displays re-lighting on resume.  I'm quite
certain that's an accident: the first DP link train inevitably fails on
that machine, and it's only serendipity that we're getting multiple plug
interrupts and the second train works.  But I shall take my victories
where I get them.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Tested-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-29 16:23:31 -07:00
Chris Wilson 43a9539fa9 drm/i915: Only export the generic intel_disable_fbc() interface
As the enable/disable routines will be gain additional complexity in
future patches, it is necessary that all callers do not bypass the
generic interface by calling into the chipset routines directly. to do
this we make the chipset routines static, so there is no choice.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-08 10:22:51 -07:00
Keith Packard e489bda422 Merge branch 'drm-intel-fixes' into drm-intel-next 2011-06-29 13:47:53 -07:00
Keith Packard d70bed1947 drm/i915: Hold struct_mutex during i915_save_state/i915_restore_state
Lots of register access in these functions, some of which requires the
struct mutex.

These functions now hold the struct mutex across the calls to
i915_save_display and i915_restore_display, and so the internal mutex
calls in those functions have been removed. To ensure that no-one else
was calling them (and hence violating the new required locking
invarient), those functions have been made static.

gen6_enable_rps locks the struct mutex, and so i915_restore_state
unlocks the mutex around calls to that function.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-29 11:20:45 -07:00
Jesse Barnes 23b2f8bb92 drm/i915: load a ring frequency scaling table v3
The ring frequency scaling table tells the PCU to treat certain GPU
frequencies as if they were a given CPU frequency for purposes of
scaling the ring frequency.  Normally the PCU will scale the ring
frequency based on the CPU P-state, but with the table present, it will
also take the GPU frequency into account.

The main downside of keeping the ring frequency high while the CPU is
at a low frequency (or asleep altogether) is increased power
consumption.  But then if you're keeping your GPU busy, you probably
want the extra performance.

v2:
  - add units to debug table header (from Eric)
  - use tsc_khz as a fallback if the cpufreq driver doesn't give us a freq
    (from Chris)
v3:
  - fix comments & debug output
  - remove unneeded force wake get/put

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-28 13:54:27 -07:00
Ben Widawsky 483f179899 drm/i915: save/resume forcewake lock fixes
The lock must be held for the saving and restoring of VGA state.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
CC: Alexander Zhaunerchyk <alex.vizor@gmail.com>
CC: Andrey Rahmatullin <wrar@wrar.name>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-22 10:28:33 -07:00
Jesse Barnes 645c62a5e9 drm/i915: split PCH clock gating init
Ibex Peak and CougarPoint already require a different setting (added
here), and future chips will likely follow that precedent.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:53 -07:00
Jesse Barnes 6067aaeadb drm/i915: split clock gating init into per-chipset functions
This helps contain the mess to init_display() instead.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 18:12:50 -07:00
Chris Wilson 968b503e69 Revert "drm/i915: Don't save/restore hardware status page address register"
This reverts commit a7a75c8f70.

There are two different variations on how Intel hardware addresses the
"Hardware Status Page". One as a location in physical memory and the
other as an offset into the virtual memory of the GPU, used in more
recent chipsets. (The HWS itself is a cacheable region of memory which
the GPU can write to without requiring CPU synchronisation, used for
updating various details of hardware state, such as the position of
the GPU head in the ringbuffer, the last breadcrumb seqno, etc).

These two types of addresses were updated in different locations of code
- one inline with the ringbuffer initialisation, and the other during
device initialisation. (The HWS page is logically associated with
the rings, and there is one HWS page per ring.) During resume, only the
ringbuffers were being re-initialised along with the virtual HWS page,
leaving the older physical address HWS untouched. This then caused a
hang on the older gen3/4 (915GM, 945GM, 965GM) the first time we tried
to synchronise the GPU as the breadcrumbs were never being updated.

Reported-and-tested-by: Linus Torvalds <torvalds@linux-foundation.org>
Reported-by: Jan Niehusmann <jan@gondor.com>
Reported-by: Justin P. Mattock <justinmattock@gmail.com>
Reported-and-tested-by: Michael "brot" Groh <brot@minad.de>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-03-23 19:45:06 -07:00
Zhenyu Wang a7a75c8f70 drm/i915: Don't save/restore hardware status page address register
It's cleaned before saving and re-initialized after restoring.
So don't need to save/restore it. And also new chip has new address
for hardware status page register, don't write to old address.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-02 11:26:13 +00:00
Jesse Barnes 9db4a9c7b2 drm/i915: cleanup per-pipe reg usage
We had some conversions over to the _PIPE macros, but didn't get
everything.  So hide the per-pipe regs with an _ (still used in a few
places for legacy) and add a few _PIPE based macros, then make sure
everyone uses them.

[update: remove usage of non-existent no-op macro]
[update 2: keep modesetting suspend/resume code, update to new reg names]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: stylistic cleanups for checkpatch and taste]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07 21:17:15 +00:00
Jesse Barnes d5bb081b02 drm/i915: cleanup rc6 code
Cleanup several aspects of the rc6 code:
  - misnamed intel_disable_clock_gating function (was only about rc6)
  - remove commented call to intel_disable_clock_gating
  - rc6 enabling code belongs in its own function (allows us to move the
    actual clock gating enable call back into restore_state)
  - allocate power & render contexts up front, only free on unload
    (avoids ugly lazy init at rc6 enable time)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: checkpatch cleanup]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:43:59 +00:00
Jesse Barnes 1daed3fb83 drm/i915: fix rc6 enabling around suspend/resume
Enabling RC6 implies setting a graphics context.  Make sure we do that
only after the ring has been enabled, otherwise our ring commands will
hang.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:43:59 +00:00
Jesse Barnes 88271da3f3 drm/i915: re-enable rc6 support for Ironlake+
Re-enable rc6 support on Ironlake for power savings.  Adds a debugfs
file to check current RC state, adds a missing workaround for Ironlake
MI_SET_CONTEXT instructions, and renames MCHBAR_RENDER_STANDBY to
RSTDBYCTL to match the docs.

Keep RC6 and the power context disabled on pre-ILK.  It only seems to
hang and doesn't save any power.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:43:58 +00:00
Chris Wilson 5909a77ac6 drm/i915: Undo "Uncouple render/power ctx before suspending"
Manaul revert of 0cdab21f9a, just to
remove the call to disable the clock gatings and powerctx before
suspend.

Peter Clifton bisected a suspend failure on his gme45 and found this to
be the culprit. As this was intended to be a fix for a similar suspend
failure for Ironlake (it didn't work), undoing this patch should have no
other side-effects.

Reported-and-tested-by: Peter Clifton <pcjc2@cam.ac.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-20 09:45:15 +00:00
Jesse Barnes 3b8d8d91d5 drm/i915: dynamic render p-state support for Sandy Bridge
Add an interrupt handler for switching graphics frequencies and handling
PM interrupts.  This should allow for increased performance when busy
and lower power consumption when idle.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-18 11:07:02 +00:00
Chris Wilson 0cdab21f9a drm/i915: Uncouple render/power ctx before suspending
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 23:19:37 +00:00
Chris Wilson 312817a39f drm/i915: Only save and restore fences for UMS
With KMS, we can simply relinquish the fence when we idle the GPU and
reassign it upon first use.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25 15:03:22 +00:00
Chris Wilson f3c91c1dea drm/i915: Only save/restore cursor regs if !KMS
Under KMS, restoring the cursor is handled upon modeswitch in order to
avoid enabling an undefined set of registers. At the moment, the cursor
is restored before the aperture and modes are fully setup causing some
invalid access during resume, such as:

  PGTBL_ER: 0x00040000
    Invalid GTT entry during Cursor Fetch

Fix this by only performing cursor register save/restore under UMS where
it is done in the correct sequence.

Reported-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-21 09:56:00 +00:00
Kyle McMartin 48fcfc888b i915: reprogram power monitoring registers on resume
Fixes issue where i915_gfx_val was reporting values several
orders of magnitude higher than physically possible (without
leaving scorch marks on my thighs at least.)

Signed-off-by: Kyle McMartin <kyle@redhat.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-03 21:44:47 +00:00
Chris Wilson a6c45cf013 drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965g
Avoid confusion between i965g meaning broadwater and the gen4+ chipset
families.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:45 +01:00
Chris Wilson e9e5f8e8d3 Merge branch 'drm-intel-fixes' into HEAD
Conflicts:
	drivers/char/agp/intel-agp.c
	drivers/gpu/drm/i915/intel_crt.c
2010-09-21 11:19:32 +01:00
Chris Wilson f899fc64cd drm/i915: use GMBUS to manage i2c links
Use the GMBUS interface rather than direct bit banging to grab the EDID
over DDC (and for other forms of auxiliary communication with external
display controllers). The hope is that this method will be much faster
and more reliable than bit banging for fetching EDIDs from buggy monitors
or through switches, though we still preserve the bit banging as a
fallback in case GMBUS fails.

Based on an original patch by Jesse Barnes.

Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-18 15:46:19 +01:00
Chris Wilson e259befd90 drm/i915: Fix Sandybridge fence registers
With 5 places to update when adding handling for fence registers, it is
easy to overlook one or two. Correct that oversight, but fence
management should be improved before a new set of registers is added.

Bugzilla: https://bugs.freedesktop.org/show_bug?id=30199
Original patch by: Yuanhan Liu <yuanhan.liu@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2010-09-17 08:18:30 +01:00
Chris Wilson 90eb77baae drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/
For the shared paths on the next generation chipsets.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-21 23:20:21 -07:00
Chris Wilson 72bcb26909 drm/i915/suspend: Flush register writes before busy-waiting.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-21 23:20:17 -07:00
Zhao Yakui b52eb4dcab drm/i915: Add frame buffer compression support on Ironlake mobile
About 0.2W power can be saved on one HP laptop.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:44 -07:00
Zhao Yakui a2c459ee9a drm/i915: Only save/restore FBC on the platform that supports FBC
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-04-12 09:25:54 -07:00
Matthew Garrett b5b72e891a drm/i915: Deobfuscate the render p-state obfuscation
The ironlake render p-state support includes some rather odd variable
names. Clean them up in order to improve the readability of the code.

Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-22 11:46:55 -05:00
Jesse Barnes f97108d1d0 drm/i915: add dynamic performance control support for Ironlake
Ironlake (and 965GM, which this patch doesn't support) supports a
hardware performance and power management feature that allows it to
adjust to changes in GPU load over time with software help.  The goal
if this is to maximize performance/power for a given workload.

This patch enables that feature, which is also a requirement for
supporting Intelligent Power Sharing, a feature which allows for
dynamic budgeting of power between the CPU and GPU in Arrandale
platforms.

Tested-by: ykzhao <yakui.zhao@intel.com>
[anholt: Resolved against the irq handler loop removal]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-22 11:46:54 -05:00
Andrew Lutomirski 1d3c36ad41 drm/i915: Fix RC6 suspend/resume
We restored RC6 twice on resume, even with modesetting off.  Instead,
only restore it once and skip RC6 initialization entirely in non-KMS mode.

Signed-off-by: Andy Lutomirski <luto@mit.edu>
Tested-by: Jeff Chua <jeff.chua.linux@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-01-06 09:39:53 -08:00
Dave Airlie 0b5e8db639 Merge remote branch 'anholt/drm-intel-next' into drm-linus
Pull more Intel changes in, especially one to init the GTT properly
2009-12-10 15:44:19 +10:00
Andrew Lutomirski 7e8b60faea drm/i915: restore render clock gating on resume
Rather than restoring just a few clock gating registers on resume,
just reinitialize the whole thing.

Signed-off-by: Andy Lutomirski <luto@mit.edu>
[anholt: Fixed up for RC6 support landed since the patch was written]
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-08 06:32:51 -08:00
Dave Airlie 3ff99164f6 Merge remote branch 'anholt/drm-intel-next' into drm-linus
This merges the upstream Intel tree and fixes up numerous conflicts
due to patches merged into Linus tree later in -rc cycle.

Conflicts:
	drivers/char/agp/intel-agp.c
	drivers/gpu/drm/drm_dp_i2c_helper.c
	drivers/gpu/drm/i915/i915_irq.c
	drivers/gpu/drm/i915/i915_suspend.c
2009-12-08 14:03:47 +10:00
Adam Jackson f2b115e69d drm/i915: Fix product names and #defines
IGD* isn't a useful name.  Replace with the codenames, as sourced from
pci.ids.

Signed-off-by: Adam Jackson <ajax@redhat.com>
[anholt: Fixed up for merge with pineview/ironlake changes]
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-07 14:55:56 -08:00
Eric Anholt f0217c42c9 drm/i915: Fix DDC on some systems by clearing BIOS GMBUS setup.
This is a sync of a fix I made in the old UMS code.  If the BIOS uses
the GMBUS and doesn't clear that setup, then our bit-banging I2C can
fail, leading to monitors not being detected.

Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-01 11:56:30 -08:00
Zhenyu Wang 5586c8bc93 drm/i915: Add more registers save/restore for Ironlake suspend
Add more display registers save/restore to fix unstable issues
during S4 testing on Ironlake. And DPLL_B_MD should not be restored
on Ironlake.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-12 11:21:14 -08:00
Jesse Barnes 97f5ab6651 drm/i915: add render standby support
Render standy allows the GPU to power down the render unit when idle.
In order for this to work, it needs a page of graphics memory to save
state.  This patch allocates that page and enables the feature on
supported chipsets.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:47:06 -08:00
Zhenyu Wang 4204878179 drm/i915: Ironlake suspend/resume support
This adds registers save/restore for Ironlake to make suspend work.

Signed-off-by: Guo, Chaohong <chaohong.guo@intel.com>
[zhenyuw: some code re-orgnization, and add more save/restore for
FDI link and transcoder registers, also fix palette register for Ironlake]
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-23 11:31:26 -07:00
Jesse Barnes 0eb96d6ed3 drm/i915: save/restore BLC histogram control reg across suspend/resume
Turns out some machines, like the ThinkPad X40 don't come back if you
don't save/restore this register.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-15 09:20:48 -07:00
Jesse Barnes 06027f9111 drm/i915: Save and restore the GM45 FBC regs on suspend and resume.
This hasn't fixed the regressions we were testing against, but clearly
should be required.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-13 10:36:20 -07:00
Ben Gamari 1341d655dd drm/i915: Refactor save/restore code
We move the display-specific code into it's own functions, called
from the general GPU state save/restore functions. This will be needed
later by the GPU reset code.

Signed-off-by: Ben Gamari <bgamari.foss@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-09-17 14:34:27 -07:00
Jesse Barnes 652c393a33 drm/i915: add dynamic clock frequency control
There are several sources of unnecessary power consumption on Intel
graphics systems. The first is the LVDS clock. TFTs don't suffer from
persistence issues like CRTs, and so we can reduce the LVDS refresh rate
when the screen is idle. It will be automatically upclocked when
userspace triggers graphical activity. Beyond that, we can enable memory
self refresh. This allows the memory to go into a lower power state when
the graphics are idle. Finally, we can drop some clocks on the gpu
itself. All of these things can be reenabled between frames when GPU
activity is triggered, and so there should be no user visible graphical
changes.

Signed-off-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-09-04 13:05:38 -07:00
Roel Kluin 819e006463 drm/i915: Fix read outside array bounds in restoring the SWF10 range.
dev_priv->saveSWF1 is a 16 element array, but this reads up to index 22,
and restored values from the wrong registers.

Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-08-05 11:21:29 -07:00
Zhao Yakui fccdaba431 drm/i915: Avoid saving/restore the modesetting registers twice in KMS mode
In KMS mode we now use the normal mode-setting paths to set the modes
back to the current configuration, so we don't need to also run the more
limited non-KMS implementation of modesetting for resume.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-07-10 12:40:36 -07:00
Keith Packard a4fc5ed698 drm/i915: Add Display Port support
Signed-off-by: Keith Packard <keithp@keithp.com>
2009-06-18 15:54:07 -07:00
Eric Anholt 1fd1c62436 drm/i915: Save/restore cursor state on suspend/resume.
This may fix cursor corruption in X on resume, which would persist until
the cursor was hidden and then shown again.

V2: Also include the cursor control regs.

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-04 11:43:11 +00:00
Keith Packard 79f11c19a3 drm/i915: save/restore fence registers across suspend/resume
This makes software fallbacks not do tiling wrong on i965 and later after
resume. It also should fix 945 performance reduction after resume which
would have disabled tiling without causing any visible effect.

Signed-off-by: Keith Packard <keithp@keithp.com>
[anholt: Fixed up the 915 case to not save/restore the new regs]
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-04-30 16:04:40 -07:00