Commit Graph

9 Commits

Author SHA1 Message Date
Mark Brown 244a60c28d Merge remote-tracking branches 'spi/topic/armada', 'spi/topic/ath79', 'spi/topic/bcm-qspi' and 'spi/topic/bcm53xx' into spi-next 2017-02-19 16:40:55 +00:00
Wei Yongjun e92f0051c0 spi: armada-3700: Remove spi_master_put in a3700_spi_remove()
The call to spi_master_put() in a3700_spi_remove() is redundant since
the master is registered using devm_spi_register_master() and no
reference hold by using spi_master_get() in a3700_spi_remove().

This is detected by Coccinelle semantic patch.

Fixes: 5762ab71eb ("spi: Add support for Armada 3700 SPI Controller")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-02-19 16:10:44 +00:00
Wei Yongjun d9928b4c48 spi: armada-3700: Remove .owner field for driver
Remove .owner field if calls are used which set it automatically.

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-02-09 16:35:26 +00:00
Romain Perier 85798e153e spi: armada-3700: Coding style fixes
The following warning are reported by checkpatch.pl:

CHECK: Alignment should match open parenthesis
+static void a3700_spi_transfer_setup(struct spi_device *spi,
+                                   struct spi_transfer *xfer)

WARNING: Missing a blank line after declarations
+                       u32 data = le32_to_cpu(val);
+                       memcpy(a3700_spi->rx_buf, &data, 4);

total: 0 errors, 1 warnings, 1 checks, 923 lines checked

Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-12-31 18:53:16 +00:00
Romain Perier cfd6693c06 spi: armada-3700: Replaced raw values for nbits by the SPI macros
Currently, function a3700_spi_pin_mode_set() configures the SPI transfer
mode according to the value passed as second argument. This value is
detected using the raw values from a switch case.

This commit replaces these raw values by the corresponding macro
constants in linux/spi/spi.h

Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-12-31 18:53:16 +00:00
Dan Carpenter 42cd4ed888 spi: armada-3700: Set mode bits correctly
We set SPI_RX_DUAL twice instead of setting SPI_TX_DUAL.

Fixes: 5762ab71eb ("spi: Add support for Armada 3700 SPI Controller")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Romain Perier <romain.perier@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-12-16 12:28:36 +00:00
Dan Carpenter 0cc059abac spi: armada-3700: Remove unnecessary condition
We checked that "a3700_spi->wait_mask & cause" was set at the beginning
of the function so we don't need to check again here.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Romain Perier <romain.perier@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-12-16 12:28:10 +00:00
Colin Ian King f6f0083cca spi: armada-3700: fix unsigned compare than zero on irq
spi->irq is an unsigned integer hence the check if status is less than
zero has no effect.  Fix this by replacing spi->irq with an int irq
so the less than zero compare will correctly detect errors.

Issue found with static analysis with CoverityScan, CID1388567

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Acked-by: Romain Perier <romain.perier@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-12-14 17:38:51 +00:00
Romain Perier 5762ab71eb spi: Add support for Armada 3700 SPI Controller
Marvell Armada 3700 SoC comprises an SPI Controller. This Controller
supports up to 4 SPI slave devices, with dedicated chip selects,supports
SPI mode 0/1/2 and 3, CPIO or Fifo mode with DMA transfers and different
SPI transfer mode (Single, Dual or Quad).

This commit adds basic driver support for FIFO mode. In this mode,
dedicated registers are used to store the instruction, the address, the
read mode and the data. Write and Read FIFO are used to store the
outcoming or incoming data. The data FIFOs are accessible via DMA or by
the CPU. Only the CPU is supported for now.

Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2016-12-08 16:05:34 +00:00