OpenE2K
/
linux
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
442,068 Commits 4 Branches 0 Tags 2 GiB
Commit Graph

3 Commits

Author SHA1 Message Date
Dinh Nguyen b89cd950cb clk: socfpga: Support multiple parents for the pll clocks 
The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2014-02-26 12:23:40 -08:00
Dinh Nguyen 5585f73175 clk: socfpga: Fix integer overflow in clock calculation 
Use 64-bit integer for calculating clock rate. Also use do_div for the
64-bit division.

Signed-off-by: Graham Moore <grmoore@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2014-02-26 12:23:29 -08:00
Steffen Trumtrar 97259e99bd clk: socfpga: split clk code 
Move the different kinds of clocks into their own files. The reason is to aid
readability of the code. This also goes along with the other SoC-specific
clock drivers.

The split introduces new structs for the three types of clocks and uses them.
Other changes are not done to the code.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
 2014-02-18 14:08:13 -08:00