Commit Graph

7 Commits

Author SHA1 Message Date
Chao Xie c2b7e05c75 ARM: cache: add dt support for tauros2 cache
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2012-08-16 16:16:50 +08:00
Chao Xie 38f2e37724 ARM: cache: add extra feature enable for tauros2
The extra feature may be used by SOCs are prefetch, burst8,
write buffer coalesce

Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2012-08-16 16:16:27 +08:00
Chao Xie fa79b8d6a2 ARM: cache: add cputype.h for tauros2
Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2012-08-16 16:16:17 +08:00
Chao Xie 5967b546dd ARM: cache: fix uninitialized ptr in tauros2_init
init the variable "mode" to NULL to ensure the later NULL checking is
taking effect.

Signed-off-by: Chao Xie <xiechao.mail@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2012-08-16 16:16:06 +08:00
Chao Xie 89326f76b7 ARM: cache: tauros2: add disable and resume callback
For the SOC chips using tauros2 cache, will need disable
and resume tauros2 cache for SOC suspend/resume.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2012-05-07 11:43:48 +08:00
Russell King 15d07dc9c5 ARM: move CP15 definitions to separate header file
Avoid namespace conflicts with drivers over the CP15 definitions by
moving CP15 related prototypes and definitions to a private header
file.

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com> [Tegra]
Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> [EP93xx]
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: David Howells <dhowells@redhat.com>
2012-03-28 18:30:01 +01:00
Lennert Buytenhek 573a652fb0 ARM: Add Tauros2 L2 cache controller support
Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
2009-11-27 15:43:21 -05:00