Commit Graph

3403 Commits

Author SHA1 Message Date
Radoslaw Pietrzyk 430a2a5945 pinctrl: stm32: Optimizes and enhances stm32gpio irqchip
- removes unneeded irq_chip.irq_eoi callback
- adds irq_chip.irq_set_wake callback for possible
  in the future GPIO wakeup
- adds irq_chip.irq_ack callback

Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com>
Reviewed-by: Ludovic Barre <ludovic.barre@st.com>
Tested-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-02 08:40:31 +01:00
Jesper Nilsson 41e009b2b5 pinctrl: artpec-6: Add smaller groups for uarts
Add group configuration for uarts that are cut down
variants, the standard being full, i.e. all signals,
flow control, i.e. rx/tx and cts/rts, and rx/tx only.

This allows us to be more precise in which pins we're
actually using.

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-01 17:04:09 +01:00
James Hogan 4a7cba71ca pinctrl: Drop TZ1090 drivers
Now that arch/metag/ has been removed, along with TZ1090 SoC support,
remove the TZ1090 pinctrl drivers. They are of no value without the
architecture and SoC platform code.

Signed-off-by: James Hogan <jhogan@kernel.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-metag@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-01 15:34:15 +01:00
Takeshi Kihara a8ab4f2bd8 pinctrl: sh-pfc: r8a77965: Add support for INTC-EX IRQ pins
Most pins on the R8A77965 SoC can be configured in GPIO mode for
interrupt and GPIO functionality, while a couple of them can also
be routed to the INTC-EX hardware block (formerly known as IRQC).

On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
this patch adds support for them to the PFC driver as "intc_ex_irqN".

Based on a similar patch for the R8A7795 PFC driver by Magnus Damm
<damm+renesas@opensource.se>.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-28 09:17:54 +01:00
Ulrich Hecht fbd452aeb4 pinctrl: sh-pfc: r8a77995: Add VIN4 pins, groups and function
This patch adds VIN4 pins, groups and function for the
R8A77995 (D3) SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-26 10:19:03 +01:00
Ulrich Hecht 6b4de40810 pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins, groups and functions
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7795 SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-26 10:19:03 +01:00
Ulrich Hecht 8db6cbabac pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7796 SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-26 10:19:03 +01:00
Phil Reid fa2b7fae84 pinctrl: mcp23s08: add open drain configuration for irq output
The mcp23s08 series device can be configured for wired and interrupts
using an external pull-up and open drain output via the IOCON_ODR bit.
And "drive-open-drain" property to enable this.

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: Phil Reid <preid@electromag.com.au>
Reviewed-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 16:08:59 +01:00
Phil Reid d9f50048dc pinctrl: mcp23s08: fix probing of mcp23s18
one_regmap_config is always null if mcp type is MCP_TYPE_S18.
Remove the null check so that the mcp23s18 will probe.

Fixes: 1781af563a ("pinctrl: mcp23s08: spi: Fix duplicate pinctrl debugfs entries")
Signed-off-by: Phil Reid <preid@electromag.com.au>
Reviewed-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 16:04:26 +01:00
Daniel Kurtz 12b10f47e5 pinctrl/amd: add get_direction handler
On boot, gpiochip_add_data() initializes the FLAG_IS_OUT bit in
desc->flags iff its gpio_chip does not have ->direction_input() handler,
else it is initialized to 0, which implies the GPIO is an "input".

Later, the sysfs "direction" handler will use gpiod_get_direction() to
get the current direction, but if no ->get_direction() handler is
installed, the result will just be the current (initial) value of flags,
which will always be OUT irregardless of the initial register value.

Add a get_direction() handler to pinctrl-amd to fix this and always
provide the correct value for direction.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 15:52:19 +01:00
Andy Shevchenko b5520891a3 pinctrl: Re-use DEFINE_SHOW_ATTRIBUTE() macro
...instead of open coding file operations followed by custom ->open()
callbacks per each attribute.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 15:36:03 +01:00
Colin Ian King ce3e7f0ee9 pinctrl: ocelot: make function ocelot_pinctrl_probe static
The function ocelot_pinctrl_probe is local to the source and does not
need to be in global scope, so make it static.

Cleans up sparse warning:
drivers/pinctrl/pinctrl-ocelot.c:465:5: warning: symbol
'ocelot_pinctrl_probe' was not declared. Should it be static?

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-22 14:02:18 +01:00
Jacopo Mondi fa3e8b71b9 pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions
Add EtherAVB groups and functions definitions for R-Car M3-N.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:33:02 +01:00
Jacopo Mondi 58cfd7f37e pinctrl: sh-pfc: r8a77965: Add SCIFs groups/functions
Add SCIF[0-5] groups and pin function definitions for R-Car M3-N.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:32:59 +01:00
Jacopo Mondi 490e687eb8 pinctrl: sh-pfc: Initial R-Car M3-N support
Add initial PFC support for R-Car M3-N (r8a77965) SoC.
No groups or functions defined, just pin and registers enumeration.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:32:58 +01:00
Takeshi Kihara 74965de1ca pinctrl: sh-pfc: r8a7796: Add TMU pins, groups and functions
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:03:29 +01:00
Takeshi Kihara f0442cf27c pinctrl: sh-pfc: r8a7795-es1: Add TMU pins, groups and functions
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7795 ES1.x SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:03:26 +01:00
Takeshi Kihara edcc14c82d pinctrl: sh-pfc: r8a7795: Add TMU pins, groups and functions
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7795 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:03:23 +01:00
Takeshi Kihara 71c236adf0 pinctrl: sh-pfc: r8a7796: Add HDMI pins, groups and functions
This patch adds HDMI0 CEC pin, group and function to the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:03:18 +01:00
Takeshi Kihara 1240414859 pinctrl: sh-pfc: r8a7795-es1: Add HDMI pins, groups and functions
This patch adds HDMI0 CEC pin, group and function to
the R8A7795 ES1.x SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:03:15 +01:00
Takeshi Kihara 5722110e2f pinctrl: sh-pfc: r8a7795: Add HDMI pins, groups and functions
This patch adds HDMI0 CEC pin, group and function to the R8A7795 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:02:56 +01:00
Takeshi Kihara 8b446c4d38 pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment for NDFC pins group
This patch fixes to set IPSR and MOD_SEL when using NFDATA{14,15}_A and
NF{RB,WP}_N_A pin function is selected. And renamess MOD_SEL2 bit22 value
definition name to SEL_NDFC.

This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.53E.

Fixes: f9aece7344 ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:02:20 +01:00
Takeshi Kihara b418c4609d pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI pins group
This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment
for SSI pins group.

This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344 ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:02:16 +01:00
Takeshi Kihara 740a4a3aa7 pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin assignment for SSI pins group
This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment
for SSI pins group.

This is a correction because MOD_SEL register specification for R8A7795
ES2.0 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.

Fixes: b205914c8f ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 19:02:10 +01:00
Ulrich Hecht 65a90f046b pinctrl: sh-pfc: r8a77995: Add DU pins, groups and function
This patch adds DU pins, groups and function for the R8A77995 (D3) SoC.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20 16:19:03 +01:00
Linus Walleij 5da2bd5ad5 pinctrl: nomadik: add USB functions for STn8815
The MUSB block in the Nomadik has two pin settings: high speed or
full speed. These correspond to two unique pin group settings: all
pins set to function B for high speed and all set to function C
for full speed. Full speed uses more pins than high speed.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-13 08:18:17 +01:00
Markus Elfring 2580b1ceb7 pinctrl: sh-pfc: Use seq_puts() in sh_pfc_pin_dbg_show()
A string which did not contain a data format specification should be put
into a sequence. Thus use the corresponding function "seq_puts".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-12 15:27:58 +01:00
Yixun Lan 49527bc0e8 pinctrl: meson-axg: adjust uart_ao_b pin group naming
Simply adjust the pin group to _x _y _z style, as to
keep the consistency in DT with previous naming scheme.

Fixes: 83c566806a ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC")
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-12 10:47:36 +01:00
Bjorn Andersson a7aa75a2a7 pinctrl: msm: Use dynamic GPIO numbering
The base of the TLMM gpiochip should not be statically defined as 0, fix
this to not artificially restrict the existence of multiple pinctrl-msm
devices.

Fixes: f365be0925 ("pinctrl: Add Qualcomm TLMM driver")
Reported-by: Timur Tabi <timur@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-12 10:47:24 +01:00
Jan Kundrát 1781af563a pinctrl: mcp23s08: spi: Fix duplicate pinctrl debugfs entries
This is a bit more involved because the pinctrl core so far always
assumed that one device (with a unique dev_name) only contains a single
pinctrl thing. This is not true for the mcp23s08 driver for chips
connected over SPI. They have a "logical address" which means that
several chips can share one physical CS signal.

A downside of this patch are some possibly ugly names for the debugfs
entries, such as "spi1.1-mcp23xxx-pinctrl.2", etc.

Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-12 10:47:24 +01:00
Jan Kundrát ed23175141 pinctrl: mcp23s08: spi: Add HW address to gpio_chip.label
When several devices are sharing one hardware SPI CS, there is no visual
clue in `lsgpio` or in /sys/kernel/debug/gpio about which one is which
one. Stuff depends on the enumeration order, and therefore lower chip
addresses always go first, but that's just an implementation detail.
This change includes the device-specific address in the debug output:

  gpiochip4: GPIOs 464-479, parent: spi/spi1.1, mcp23s17.2, can sleep:
  gpiochip3: GPIOs 480-495, parent: spi/spi1.1, mcp23s17.1, can sleep:

Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-12 10:47:24 +01:00
Jan Kundrát 9b3e420766 pinctrl: mcp23s08: spi: Fix regmap debugfs entries
The SPI version of this chip allows several devices to be present on the
same SPI bus via a local address. If this is in action and if the kernel
has debugfs, however, the code attempts to create duplicate entries for
the regmap's debugfs:

  mcp23s08 spi1.1: Failed to create debugfs directory

This patch simply assigns a local name matching the device logical
address to the `struct regmap_config`.

No changes are needed for MCP23S18 because that device does not support
any logical addressing. Similarly, I2C devices do not need any action,
either, because they are already different in their I2C address.

A similar problem is present for the pinctrl debugfs instance, but that
one is not addressed by this patch.

Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-12 10:47:23 +01:00
Kyle Yan 184f3448f6 pinctrl: qcom: Add sdm845 pinctrl driver
This adds the pinctrl definitions for the TLMM of SDM845.

Signed-off-by: Kyle Yan <kyan@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-12 10:47:23 +01:00
Linus Torvalds ef991796be This is the bulk of pin control changes for the v4.16 kernel cycle:
Core changes:
 
 - After lengthy discussions and partly due to my ignorance, we have
   merged a patch making pinctrl_force_default() and pinctrl_force_sleep()
   reprogram the states into the hardware of any hogged pins, even
   if they are already in the desired state. This only apply to hogged
   pins since groups of pins owned by drivers need to be managed by
   each driver, lest they could not do things like runtime PM and
   put pins to sleeping state even if the system as a whole is not
   in sleep.
 
 New drivers:
 
 - New driver for the Microsemi Ocelot SoC. This is used in ethernet
   switches.
 
 - The X-Powers AXP209 GPIO driver was extended to also deal with pin
   control and moved over from the GPIO subsystem. This circuit is
   a mixed-mode integrated circuit which is part of AllWinner designs.
 
 - New subdriver for the Qualcomm MSM8998 SoC, core of a high end
   mobile devices (phones) chipset.
 
 - New subdriver for the ST Microelectronics STM32MP157 MPU and
   STM32F769 MCU from the STM32 family.
 
 - New subdriver for the MediaTek MT7622 SoC. This is used for routers,
   repeater, gateways and such network infrastructure.
 
 - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC has
   multimedia features and target "smart devices", I guess in-car
   entertainment, in-flight entertainment, industrial control panels etc.
 
 General improvements:
 
 - Incremental improvements on the SH-PFC subdrivers for things like
   the CAN bus.
 
 - Enable the glitch filter on Baytrail GPIOs used for interrupts.
 
 - Proper handling of pins to GPIO ranges on the Semtec SX150X
 
 - An IRQ setup ordering fix on MCP23S08.
 
 - A good set of janitorial coding style fixes.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJadGEKAAoJEEEQszewGV1zA4QQALs8edxhv4qV5vm50mTdrO3n
 QtRhJNb53j6MIKtjFnazMvh6MXRIP+08SyX9sDLi5AxINIVuyQh3mrcB6Zc9zN58
 +6jFFOIbfm5E8by4n3wnKm3F/WAbNBZph9eT2Rn3cDv9o9hQbyNJ50sQkQMCjd9X
 WGR353c3OL4zb3vU8t72G/RPYUY1w1SkG9bGzRuSif8LawDcN6v6MMo2XhZA6RqM
 3qYIG29vJ1n0weggUIBeSAJIzk4eMwcoWCbVWxhns5JGxw5VPES1zbSp1D+mbzRC
 01i5Pt/gD+cWN/Kk/zKIMo1OqLAl+uLr6hzepj6W+5wu9CcQz/BgvRx7HUqnqgyh
 S8cN4AOgWmW+T75pHypd1WVic3q0RCXkFY8jjHpCATDY+Z+js0lZRs3y4DBiJ2ys
 DMVBeumDINKqaZ6aLH6lVkm+SxXOUy143arQQIzi0/F7fAp68i+9ofIO8B5smEmd
 0S+3sT0sO5QXVgZJ0t0iGUUG5irXi8XtF5qvRmuFZUe0OLGgKX20oCdC0pH0WU4M
 OZO1Bvb8vmn1tddogO2WlHeg6amWdwxtDuBsLRO3YILLu3jwPjhNqNmErXzXEmWt
 TY9l2M1uQmoJibNpmTjOzSfj4OtUHMwkDrFRJHAcUPcKwdEy4MyzFL16ATnIwgY9
 AmyMLNWJd8Wazgc6BK6w
 =gLY/
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.16 kernel cycle.
  Like with GPIO it is actually a bit calm this time.

  Core changes:

   - After lengthy discussions and partly due to my ignorance, we have
     merged a patch making pinctrl_force_default() and
     pinctrl_force_sleep() reprogram the states into the hardware of any
     hogged pins, even if they are already in the desired state.

     This only apply to hogged pins since groups of pins owned by
     drivers need to be managed by each driver, lest they could not do
     things like runtime PM and put pins to sleeping state even if the
     system as a whole is not in sleep.

  New drivers:

   - New driver for the Microsemi Ocelot SoC. This is used in ethernet
     switches.

   - The X-Powers AXP209 GPIO driver was extended to also deal with pin
     control and moved over from the GPIO subsystem. This circuit is a
     mixed-mode integrated circuit which is part of AllWinner designs.

   - New subdriver for the Qualcomm MSM8998 SoC, core of a high end
     mobile devices (phones) chipset.

   - New subdriver for the ST Microelectronics STM32MP157 MPU and
     STM32F769 MCU from the STM32 family.

   - New subdriver for the MediaTek MT7622 SoC. This is used for
     routers, repeater, gateways and such network infrastructure.

   - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC
     has multimedia features and target "smart devices", I guess in-car
     entertainment, in-flight entertainment, industrial control panels
     etc.

  General improvements:

   - Incremental improvements on the SH-PFC subdrivers for things like
     the CAN bus.

   - Enable the glitch filter on Baytrail GPIOs used for interrupts.

   - Proper handling of pins to GPIO ranges on the Semtec SX150X

   - An IRQ setup ordering fix on MCP23S08.

   - A good set of janitorial coding style fixes"

* tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits)
  pinctrl: mcp23s08: fix irq setup order
  pinctrl: Forward declare struct device
  pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding
  pinctrl: stm32: add STM32F769 MCU support
  pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping
  pinctrl: sx150x: Register pinctrl before adding the gpiochip
  pinctrl: sx150x: Unregister the pinctrl on release
  pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe()
  pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show()
  pinctrl: pinmux: Use seq_putc() in pinmux_pins_show()
  pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show()
  pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call
  pinctrl: mediatek: mt7622: fix potential uninitialized value being returned
  pinctrl: uniphier: refactor drive strength get/set functions
  pinctrl: imx7ulp: constify struct imx_cfg_params_decode
  pinctrl: imx: constify struct imx_pinctrl_soc_info
  pinctrl: imx7d: simplify imx7d_pinctrl_probe
  pinctrl: imx: use struct imx_pinctrl_soc_info as a const
  pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly.
  pinctrl: qcom: Add msm8998 pinctrl driver
  ...
2018-02-02 14:22:53 -08:00
Linus Torvalds 9798f5178f The is the bulk of GPIO changes for the v4.16 kernel cycle.
Core changes:
 
 - Disallow open drain and open source flags to be set
   simultaneously. This doesn't make electrical sense, and would
   the hardware actually respond to this setting, the result
   would be short circuit.
 
 - ACPI GPIO has a new core infrastructure for handling quirks.
   The quirks are there to deal with broken ACPI tables centrally
   instead of pushing the work to individual drivers. In the world
   of BIOS writers, the ACPI tables are perfect. Until they find a
   mistake in it. When such a mistake is found, we can patch it
   with a quirk. It should never happen, the problem is that it
   happens. So we accomodate for it.
 
 - Several documentation updates.
 
 - Revert the patch setting up initial direction state from
   reading the device. This was causing bad things for drivers
   that can't read status on all its pins. It is only affecting
   debugfs information quality.
 
 - Label descriptors with the device name if no explicit label is
   passed in.
 
 - Pave the ground for transitioning SPI and regulators to use
   GPIO descriptors by implementing some quirks in the device tree
   GPIO parsing code.
 
 New drivers:
 
 - New driver for the Access PCIe IDIO 24 family.
 
 Other:
 
 - Major refactorings and improvements to the GPIO mockup driver
   used for test and verification.
 
 - Moved the AXP209 driver over to pin control since it gained a
   pin control back-end. These patches will appear (with the same
   hashes) in the pin control pull request as well.
 
 - Convert the onewire GPIO driver w1-gpio to use descriptors.
   This is merged here since the W1 maintainers send very few
   pull requests and he ACKed it.
 
 - Start to clean up driver headers using <linux/gpio.h> to just
   use <linux/gpio/driver.h> as appropriate.
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJacIW6AAoJEEEQszewGV1z9b0P/jxWKaCAGFTTu/HZQ79RBAFq
 w33nIazzoh+88sN7A9xKexpr4ibOxiCvOwkTtrUBNaxGGy5fslj4+OY5BzunEfBK
 1vYxyEqtenvvZK03pOd6CSfHKV+vD5ngnVHGdtGzRvtmDDiSgtzqyEyUhQcXM+l7
 PrEh6qrd4TBZezlVR8kn5eqcmclkCBVSQCuLSq+ThMmCKRZuOdf1Im3D6eBzh1/N
 P81HdcglqbSsfUl1RcFiHs9Z+KcZOq83CNl2Ej1LePK2JBZbmkx9dR+WSJmV1u4P
 6wvzFcQDhfGEiiteg2BS5c+o6aAyShpuRNut+2MLre8icmdfpqUEqFotHbfQjW5y
 sqaejGsJ5aHcRBq7UUM+F9s1R0iN3tlafi3L0WEhl0Tn5huRQq3Uqcw6e5l+XrWd
 0h+b5PbKJZO/iqzRhSl+rhc0V2CFDJOCwvY+JX6356fvrcF0T6LhvKfDYtKU3Iyb
 HB0RG1OcYe228f96azvafCkFyBIYX9mqHBvOXpQQgrZQYXfN1rupLvpOhxC+Wbvn
 nsGE2bdD6HA1bytTbkxbL+QWP7faHf5YVcZpaN7UWbO3sOzL46fj8eHwHUim95Tr
 pR5kDZRhZd8+9SCNZ/ttpaEbis9MOqS/3Mlxrj4GXtfFFmR53hjFy2bG/Z7R2RB0
 MlSEJRc8iDIs+1j3D2RR
 =k5nL
 -----END PGP SIGNATURE-----

Merge tag 'gpio-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "The is the bulk of GPIO changes for the v4.16 kernel cycle. It is
  pretty calm this time around I think. I even got time to get to things
  like starting to clean up header includes.

  Core changes:

   - Disallow open drain and open source flags to be set simultaneously.
     This doesn't make electrical sense, and would the hardware actually
     respond to this setting, the result would be short circuit.

   - ACPI GPIO has a new core infrastructure for handling quirks. The
     quirks are there to deal with broken ACPI tables centrally instead
     of pushing the work to individual drivers. In the world of BIOS
     writers, the ACPI tables are perfect. Until they find a mistake in
     it. When such a mistake is found, we can patch it with a quirk. It
     should never happen, the problem is that it happens. So we
     accomodate for it.

   - Several documentation updates.

   - Revert the patch setting up initial direction state from reading
     the device. This was causing bad things for drivers that can't read
     status on all its pins. It is only affecting debugfs information
     quality.

   - Label descriptors with the device name if no explicit label is
     passed in.

   - Pave the ground for transitioning SPI and regulators to use GPIO
     descriptors by implementing some quirks in the device tree GPIO
     parsing code.

  New drivers:

   - New driver for the Access PCIe IDIO 24 family.

  Other:

   - Major refactorings and improvements to the GPIO mockup driver used
     for test and verification.

   - Moved the AXP209 driver over to pin control since it gained a pin
     control back-end. These patches will appear (with the same hashes)
     in the pin control pull request as well.

   - Convert the onewire GPIO driver w1-gpio to use descriptors. This is
     merged here since the W1 maintainers send very few pull requests
     and he ACKed it.

   - Start to clean up driver headers using <linux/gpio.h> to just use
     <linux/gpio/driver.h> as appropriate"

* tag 'gpio-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (103 commits)
  gpio: Timestamp events in hardirq handler
  gpio: Fix kernel stack leak to userspace
  gpio: Fix a documentation spelling mistake
  gpio: Documentation update
  gpiolib: remove redundant initialization of pointer desc
  gpio: of: Fix NPE from OF flags
  gpio: stmpe: Delete an unnecessary variable initialisation in stmpe_gpio_probe()
  gpio: stmpe: Move an assignment in stmpe_gpio_probe()
  gpio: stmpe: Improve a size determination in stmpe_gpio_probe()
  gpio: stmpe: Use seq_putc() in stmpe_dbg_show()
  gpio: No NULL owner
  gpio: stmpe: i2c transfer are forbiden in atomic context
  gpio: davinci: Include proper header
  gpio: da905x: Include proper header
  gpio: cs5535: Include proper header
  gpio: crystalcove: Include proper header
  gpio: bt8xx: Include proper header
  gpio: bcm-kona: Include proper header
  gpio: arizona: Include proper header
  gpio: amd8111: Include proper header
  ...
2018-01-31 12:25:27 -08:00
Dmitry Mastykin 02e389e63e pinctrl: mcp23s08: fix irq setup order
When using mcp23s08 module with gpio-keys, often (50% of boots)
it fails to get irq numbers with message:
"gpio-keys keys: Unable to get irq number for GPIO 0, error -6".
Seems that irqs must be setup before devm_gpiochip_add_data().

Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Mastykin <mastichi@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-30 15:17:14 +01:00
Geert Uytterhoeven 470b73a384 pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-22 09:55:05 +01:00
Alexandre Torgue f90160fc95 pinctrl: stm32: add STM32F769 MCU support
This patch which adds STM32F769 pinctrl and GPIO support, relies on the
generic STM32 pinctrl driver.

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Acked-by: Patrice CHOTARD <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-22 09:28:08 +01:00
Peter Rosin b930151e5b pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping
Without such a range, gpiolib fails with -EPROBE_DEFER, pending the
addition of the range. So, without a range, gpiolib will keep
deferring indefinitely.

Cc: stable@vger.kernel.org
Fixes: 9e80f9064e ("pinctrl: Add SX150X GPIO Extender Pinctrl Driver")
Fixes: e10f72bf4b ("gpio: gpiolib: Generalise state persistence beyond sleep")
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-18 11:04:47 +01:00
Peter Rosin 1a1d39e1b8 pinctrl: sx150x: Register pinctrl before adding the gpiochip
Various gpiolib activity depend on the pinctrl to be up and kicking.
Therefore, register the pinctrl before adding a gpiochip.

Cc: stable@vger.kernel.org
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-18 11:04:43 +01:00
Peter Rosin 0657cb50b5 pinctrl: sx150x: Unregister the pinctrl on release
There is no matching call to pinctrl_unregister, so switch to the
managed devm_pinctrl_register to clean up properly when done.

Cc: stable@vger.kernel.org
Fixes: 9e80f9064e ("pinctrl: Add SX150X GPIO Extender Pinctrl Driver")
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-18 11:04:30 +01:00
Wei Yongjun 119fcf47fd pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe()
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.

Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-18 08:51:32 +01:00
Markus Elfring 9d2fc7c370 pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show()
A single character (line break) should be put into a sequence.
Thus use the corresponding function "seq_putc".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-16 11:08:24 +01:00
Markus Elfring ffd10c2ec7 pinctrl: pinmux: Use seq_putc() in pinmux_pins_show()
A single character (line break) should be put into a sequence.
Thus use the corresponding function "seq_putc".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-16 11:07:18 +01:00
Markus Elfring 02c9d285ff pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show()
A single character (line break) should be put into a sequence.
Thus use the corresponding function "seq_putc".

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-16 11:06:13 +01:00
Sean Wang 8b3d9cd48d pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call
Make consistent error handling of all mtk_hw_get_value occurrences using
propagating error code from the internal instead of creating a new one.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-11 10:43:24 +01:00
Sean Wang 181cdac02c pinctrl: mediatek: mt7622: fix potential uninitialized value being returned
commit d6ed935513 ("pinctrl: mediatek: add pinctrl driver for MT7622
SoC") leads to the following static checker warning:

drivers/pinctrl/mediatek/pinctrl-mt7622.c:1419 mtk_gpio_get()
error: uninitialized symbol 'value'.
1412  static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
1413  {
1414          struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent);
1415          int value;
1416
1417          mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value);
^^^^^^^^^^^^^^^^
1418
1419          return !!value;
1420  }

The appropriate error handling must be added to avoid the potential error
caused by uninitialized value being returned.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-11 10:42:12 +01:00
Masahiro Yamada fb36a7b07d pinctrl: uniphier: refactor drive strength get/set functions
There is code duplication between uniphier_conf_pin_drive_get() and
uniphier_conf_pin_drive_set().  Factor out the common code into
uniphier_conf_get_drvctrl_data().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-11 10:40:23 +01:00
Stefan Agner d6093367bc pinctrl: imx7ulp: constify struct imx_cfg_params_decode
The decode parameters are constant mark them const.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-11 10:29:40 +01:00
Stefan Agner 7c017687f8 pinctrl: imx: constify struct imx_pinctrl_soc_info
Now that imx_pinctrl_probe accepts const struct imx_pinctrl_soc_info
we can constify all declarations of struct imx_pinctrl_soc_info.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-11 10:29:37 +01:00
Stefan Agner 7372077542 pinctrl: imx7d: simplify imx7d_pinctrl_probe
Using of_device_get_match_data in imx7d_pinctrl_probe simplifies
the function. Also get rid of the void pointer cast since
imx_pinctrl_probe now accepts const struct imx_pinctrl_soc_info.

Cc: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-11 10:29:32 +01:00
Stefan Agner f5843492ec pinctrl: imx: use struct imx_pinctrl_soc_info as a const
For some SoCs the struct imx_pinctrl_soc_info is passed through
of_device_id.data which is const. Most variables are already const
or otherwise not written. However, some fields are modified at
runtime. Move those fields to the dynamically allocated struct
imx_pinctrl.

Fixes: b3060044e4 ("pinctrl: freescale: imx7d: make of_device_ids const")
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Arvind Yadav <arvind.yadav.cs@gmail.com>
Cc: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-11 10:29:18 +01:00
hao_zhang 32e21f084f pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly.
Pin function can not be match correctly when SUNXI_PIN describe with
mutiple variant and same function.

such as:
on pinctrl-sun4i-a10.c

SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
		SUNXI_FUNCTION(0x0, "gpio_in"),
		SUNXI_FUNCTION(0x1, "gpio_out"),
		SUNXI_FUNCTION_VARIANT(0x2, "pwm",    /* PWM0 */
			PINCTRL_SUN4I_A10 |
			PINCTRL_SUN7I_A20),
		SUNXI_FUNCTION_VARIANT(0x3, "pwm",    /* PWM0 */
			PINCTRL_SUN8I_R40)),

it would always match to the first variant function
(PINCTRL_SUN4I_A10, PINCTRL_SUN7I_A20)

so we should add variant compare on it.

Signed-off-by: hao_zhang <hao5781286@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-10 14:44:20 +01:00
Khan, Imran a3a093ae02 pinctrl: qcom: Add msm8998 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for msm8998.

Signed-off-by: Imran Khan <kimran@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
[bjorn: Consolidated function groups]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-09 15:30:20 +01:00
Markus Elfring 7c3012c855 pinctrl: mcp23s08: Combine two function calls into one in mcp23s08_dbg_show()
* Print a line break together with other data in a single function call.

* Adjust indentation.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-09 15:10:02 +01:00
Bai Ping ba33f4f42e pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULL
On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
are available in a separate IOMUXC_SNVS module. Add support for the
IOMUXC_SNVS module to the i.MX 6UL pinctrl driver.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-09 14:59:17 +01:00
Alexandre Belloni ce8dc09433 pinctrl: Add Microsemi Ocelot SoC driver
The Microsemi Ocelot SoC has a few pins that can be used as GPIOs or take
multiple other functions. Add a driver for the pinmuxing and the GPIOs.

There is currently no support for interrupts.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-09 14:54:59 +01:00
Masahiro Yamada b67ecdec45 pinctrl: remove redundant mux_setting clear in pinmux_disable_setting()
desc->mux_setting is set to NULL in pin_free() called just below.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-09 14:48:34 +01:00
Linus Walleij 55b6986ca1 pinctrl: sh-pfc: Updates for v4.16 (take two)
- Add PWM pin groups on various R-Car Gen2 and RZ/G1 SoCs,
   - Add missing I2C5 pin groups on R-Car E2 and RZ/G1E,
   - Add SATA pin groups on R-Car H3 ES2.0.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJaT1M+AAoJEEgEtLw/Ve77BkwP/jR3qNvbAW6Ur5bQvl5rVJcc
 +OoSZU0ULXP6kwk0KxMcddpAWyCYKsy+lbQaIAnjJlZa/JCr4Am7A42OB/lTfDo1
 EQmt9aWA8RAGvsLOZwsfP/FCw8o3BpYOjS1EhoXi+Y91VHfSehCrZiPRs/2AkVZb
 cWntYOw5EJXwKcAH7gL4dhE93vSVyKTs8uimdZ+NlNDT3Z42vUckdGXqPjKYT/OB
 wNFk/u/bZ5iOR9b7K8UQFZ255Yzp8rIfFUsXUBUGBgN0DKjsbppYd2qV6JZoGC78
 LW2kewGXLHk1zuSnveY+AbEQKz/hKlPIviW0QoQ9nJwsMthTUf/OOZFTPuryuNLc
 jtUzlqNfEHS/fbLqii8ey3VourrI3vLGZ8jaXT0k33CK9cx8bY33g103oUpUBk0w
 HXy+I9DrvE74aEf2oqW+oHOjIRp4RPsVVtgbvw2wdDcroHtNcxYLjeEaujEjDNxm
 9yslzlNSt9R9O1J/c4gPfM90laOOr8By6nA98igQykDlGEyzLZnEsqD7pmMVOhYx
 Nh6mpw4J9IRy/6lHoMc9SWPeodEvDer7XDZI69gU1jNkanTiWb8ZPn498UP9p9WH
 ytN3yxaqqAFb60oQhKw1b5a9kCjbmzX+J4qirffIcw4XT9R9CO20IGwUeyPagkVs
 dSrdEmHEfwnufmjyMC8J
 =EJKS
 -----END PGP SIGNATURE-----

Merge tag 'sh-pfc-for-v4.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.16 (take two)

  - Add PWM pin groups on various R-Car Gen2 and RZ/G1 SoCs,
  - Add missing I2C5 pin groups on R-Car E2 and RZ/G1E,
  - Add SATA pin groups on R-Car H3 ES2.0.
2018-01-08 08:17:10 +01:00
Julia Lawall 924f5494da pinctrl: armada-37xx: account for const type of of_device_id.data
The data field of an of_device_id structure has type const void *, so
there is no need for a const-discarding cast when putting const values
into such a structure.

Done using Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-08 08:15:48 +01:00
Julia Lawall 9b8ee3c0f6 pinctrl: axp209: account for const type of of_device_id.data
The return value of of_device_get_match_data has type const void *.
The desc field of the pctl structure also has a const type, so there
is no need for the const-discarding cast between them.

Done using Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-08 08:15:47 +01:00
Julia Lawall 8b74c7d3e3 pinctrl: at91-pio4: account for const type of of_device_id.data
This driver creates a const structure that it stores in the data field
of an of_device_id array.

Adding const to the declaration of the location that receives the
const value from the data field ensures that the compiler will
continue to check that the value is not modified.  Furthermore, the
const-discarding cast on the extraction from the data field is no
longer needed.

Done using Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-08 08:15:47 +01:00
Hans de Goede 9291c65b01 pinctrl: baytrail: Enable glitch filter for GPIOs used as interrupts
On some systems, some PCB traces attached to GpioInts are routed in such
a way that they pick up enough interference to constantly (many times per
second) trigger.

Enabling glitch-filtering fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-08 08:15:46 +01:00
Markus Elfring 659e7142bd pinctrl: vt8500: Delete an error message for a failed memory allocation in five functions
Omit an extra message for a memory allocation failure in these functions.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-08 08:15:46 +01:00
Markus Elfring b18b2e7759 pinctrl: tegra: Delete two error messages for a failed memory allocation in tegra_pinctrl_probe()
Omit extra messages for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:55 +01:00
Markus Elfring 51d7a036a6 pinctrl: spear: Delete an error message for a failed memory allocation in spear_pinctrl_probe()
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:55 +01:00
Markus Elfring b5623acb8d pinctrl/spear/plgpio: Delete two error messages for a failed memory allocation in plgpio_probe()
Omit extra messages for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:54 +01:00
Krzysztof Kozlowski 221173a3fc pinctrl: samsung: Add SPDX license identifiers
Replace GPL license statements with SPDX GPL-2.0+ license identifiers.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:54 +01:00
Markus Elfring e423f0ceef pinctrl: xway: Delete two error messages for a failed memory allocation in pinmux_xway_probe()
Omit extra messages for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:53 +01:00
Markus Elfring 86f75c65ff pinctrl: utils: Delete an error message for a failed memory allocation in pinctrl_utils_add_map_configs()
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:53 +01:00
Markus Elfring 405e64a1cd pinctrl: tz1090-pdc: Delete an error message for a failed memory allocation in two functions
Omit an extra message for a memory allocation failure in these functions.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:52 +01:00
Markus Elfring 8c017679ab pinctrl: tz1090: Delete an error message for a failed memory allocation in two functions
Omit an extra message for a memory allocation failure in these functions.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:52 +01:00
Markus Elfring 7598160d7d pinctrl: single: Delete an unnecessary return statement in pcs_irq_chain_handler()
The script "checkpatch.pl" pointed information out like the following.

WARNING: void function return statements are not generally useful

Thus remove such a statement in the affected function.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:51 +01:00
Markus Elfring a14aa2716b pinctrl: single: Delete an error message for a failed memory allocation in pcs_probe()
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:51 +01:00
Markus Elfring 85dc397a24 pinctrl: rockchip: Fix a typo in four comment lines
Adjust words in these descriptions.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:51 +01:00
Markus Elfring 283b7ac92b pinctrl: rockchip: Improve a size determination in rockchip_pinctrl_probe()
Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:50 +01:00
Markus Elfring 98c8ee73fe pinctrl: rockchip: Delete error messages for a failed memory allocation in two functions
Omit extra messages for a memory allocation failure in these functions.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:50 +01:00
Markus Elfring 5896c8d7c8 pinctrl: palmas: Delete an error message for a failed memory allocation in palmas_pinctrl_probe()
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:49 +01:00
Markus Elfring 3da941b048 pinctrl: at91: Delete an error message for a failed memory allocation in at91_pinctrl_mux_mask()
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-01-03 08:46:49 +01:00
Thomas Gleixner 702cb0a028 genirq/irqdomain: Rename early argument of irq_domain_activate_irq()
The 'early' argument of irq_domain_activate_irq() is actually used to
denote reservation mode. To avoid confusion, rename it before abuse
happens.

No functional change.

Fixes: 7249164346 ("genirq/irqdomain: Update irq_domain_ops.activate() signature")
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Alexandru Chirvasitu <achirvasub@gmail.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Dou Liyang <douly.fnst@cn.fujitsu.com>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Mikael Pettersson <mikpelinux@gmail.com>
Cc: Josh Poulson <jopoulso@microsoft.com>
Cc: Mihai Costache <v-micos@microsoft.com>
Cc: Stephen Hemminger <sthemmin@microsoft.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-pci@vger.kernel.org
Cc: Haiyang Zhang <haiyangz@microsoft.com>
Cc: Dexuan Cui <decui@microsoft.com>
Cc: Simon Xiao <sixiao@microsoft.com>
Cc: Saeed Mahameed <saeedm@mellanox.com>
Cc: Jork Loeser <Jork.Loeser@microsoft.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: devel@linuxdriverproject.org
Cc: KY Srinivasan <kys@microsoft.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Sakari Ailus <sakari.ailus@intel.com>,
Cc: linux-media@vger.kernel.org
2017-12-29 21:13:04 +01:00
Icenowy Zheng e210a0a948 pinctrl: sunxi: fix a typo when merging A20 support to A10 driver
When merging A20 pinctrl support to A10 pinctrl driver, the I2C function
of PI3 is wrongly written as "i2c3" (it should be "i2c4").

Fix this typo.

Fixes: cad4e209c1 ("pinctrl: sunxi: add support of R40 to A10 pinctrl driver")
Reported-by: Mark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-28 15:06:01 +01:00
Markus Elfring 203f4b0651 pinctrl: msm: Delete an error message for a failed memory allocation in msm_pinctrl_probe()
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-28 13:41:02 +01:00
Linus Walleij bd8ed930af Revert "pinctrl: qcom: disable GPIO groups with no pins"
This reverts commit 93ebe8636b.

After discussion and review of the v11 patchset, a new approach
was found so that this patch is not needed.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-28 13:32:53 +01:00
Andrew Lunn 39c3fd5895 kernel/irq: Extend lockdep class for request mutex
The IRQ code already has support for lockdep class for the lock mutex
in an interrupt descriptor. Extend this to add a second class for the
request mutex in the descriptor. Not having a class is resulting in
false positive splats in some code paths.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: linus.walleij@linaro.org
Cc: grygorii.strashko@ti.com
Cc: f.fainelli@gmail.com
Link: https://lkml.kernel.org/r/1512234664-21555-1-git-send-email-andrew@lunn.ch
2017-12-28 12:26:35 +01:00
Timur Tabi 93ebe8636b pinctrl: qcom: disable GPIO groups with no pins
pinctrl-msm only accepts an array of GPIOs from 0 to n-1, and it expects
each group to support have only one pin (npins == 1).

We can support "sparse" GPIO maps if we allow for some groups to have zero
pins (npins == 0).  These pins are "hidden" from the rest of the driver
and gpiolib.

Access to unavailable GPIOs is blocked via a request callback.  If the
requested GPIO is unavailable, -EACCES is returned, which prevents
further access to that GPIO.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-21 13:04:35 +01:00
Markus Elfring ce8b8d70d4 pinctrl: adi2: Improve a size determination in two functions
Replace the specification of data structures by variable references
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-21 10:22:41 +01:00
Markus Elfring 419517f15d pinctrl: adi2: Delete an error message for a failed memory allocation in two functions
Omit an extra message for a memory allocation failure in these functions.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-21 10:21:56 +01:00
Markus Elfring cb1a42d5fa pinctrl/nomadik/abx500: Improve a size determination in abx500_gpio_probe()
Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-21 10:20:29 +01:00
Markus Elfring 8931dc0804 pinctrl/nomadik/abx500: Delete an error message for a failed memory allocation in abx500_gpio_probe()
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-21 10:19:26 +01:00
Wolfram Sang 297e5b2b7a pinctrl: sh-pfc: r8a7795: Add SATA pins, groups, and functions
Tested with a Salvator-XS and H3 ES2.0.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-12-21 10:08:23 +01:00
Markus Elfring bca50ce005 pinctrl: mvebu: Delete an error message for a failed memory allocation in mvebu_pinctrl_probe()
Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-20 13:20:27 +01:00
Tony Lindgren c2584927b7 pinctrl: single: Remove invalid message
Pinctrl single should just show how many pins were found, the physical
address is already in the dev information. So let's remove the wrong
information that claims to show the physical address but really prints
a virtual address that is now hashed.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-20 12:38:46 +01:00
Linus Walleij 723dd2f0de pinctrl: sh-pfc: Updates for v4.16
- Add CAN pin groups on RZ/G1E,
   - Add CAN and CAN FD pin groups on R-Car H3 ES2.0, and R-Car D3,
   - Add support for the new R-Car V3M SoC,
   - Add support for I2C on R-Car D3,
   - Small fixes and cleanups.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJaM5QbAAoJEEgEtLw/Ve77DL0QAK5qKY/9Jt9PASqIvEJMsc5U
 Ns8ULXaynLSvOLHWNCFN0MD53gnKsQVOFMynsf1NWJ5j2fqCCu5nkrxoZKTTxMWs
 1TJGXBrCqQLzQspUXxdjFwJHIOeXCDQllw5Xsdq4MbzmlDRr+G9jj7CxLK5pjk1B
 jUZ+cfDBwuSWlDymrwcEAREBQtg7HYBlkt1zyFXPJYu5R/iGdE1ih39yBqTPka1/
 ua+d2FdGOUeOXoqqAkkJZ9+8YsITAoU+YoriKgf2I/vLiovBCBSdfenJZ5He+Hth
 7EWaIiK1Y/zdwadUtzC6/FGckkn4kj6+t5koLrXaSXce/TO4uWN6iIAiWATd26CY
 sxv1+likNAN5rGXtowXiyyOo26bZ/nFchgT4JC8FZdG0DeseOAFYE8pn8TKvDdSZ
 RTPmo6r/CiFsyn3oAzOjSMbafEvXJBZX/QQDgsS1orboWAbi8YtswacIPc/GGBhr
 iCc28erUks2fSq4+3W64Q+s/061I7NiES13ry9o3srfjWb45PEdjO+FUMN8chazt
 sNrWWrRB6HEs9N5/jGA6ZRPnbZnJnl8d1sxY/Tpj32To0kDWn3CVlGwLZDDaRIJf
 Zs/q8i/2D97RyiXtTtKacO2fZpHWQl+9kDKXOEjVcLZh5utkKM+L2cBSHoG5cCRn
 XsPp6HLHI4BdJnap4+La
 =dwjl
 -----END PGP SIGNATURE-----

Merge tag 'sh-pfc-for-v4.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.16

  - Add CAN pin groups on RZ/G1E,
  - Add CAN and CAN FD pin groups on R-Car H3 ES2.0, and R-Car D3,
  - Add support for the new R-Car V3M SoC,
  - Add support for I2C on R-Car D3,
  - Small fixes and cleanups.
2017-12-20 10:37:46 +01:00
Quentin Schulz 971f1b38f9 pinctrl: axp209: add missing Kconfig dependencies
This fixes some compilation issues.

GENERIC_PINCONF and OF at least for pinconf_generic_dt_*, PINMUX at
least for pinmux_ops and GPIOLIB for at least gpio_chip.

Fixes: 23f75d7dfa ("pinctrl: axp209: add pinctrl features")

Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-20 09:13:14 +01:00
Quentin Schulz a049815229 pinctrl: axp209: dereference pointer after it's been set
The number of GPIOs is gotten from a field within the structure
referenced in the of_device.data but it was actually read before it was
retrieved, thus it was dereferencing a null pointer.

Set the number of GPIOs after retrieving of_device.data.

Fixes: e1190083b8 ("pinctrl: axp209: add support for AXP813 GPIOs")
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Reported-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Tested-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-20 09:06:29 +01:00
Brian Norris 5c9d8c4f6b pinctrl: rockchip: enable clock when reading pin direction register
We generally leave the GPIO clock disabled, unless an interrupt is
requested or we're accessing IO registers. We forgot to do this for the
->get_direction() callback, which means we can sometimes [1] get
incorrect results [2] from, e.g., /sys/kernel/debug/gpio.

Enable the clock, so we get the right results!

[1] Sometimes, because many systems have 1 or mor interrupt requested on
each GPIO bank, so they always leave their clock on.

[2] Incorrect, meaning the register returns 0, and so we interpret that
as "input".

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-20 09:00:13 +01:00
Sean Wang d6ed935513 pinctrl: mediatek: add pinctrl driver for MT7622 SoC
Add support for pinctrl on MT7622 SoC. The IO core found on the SoC has
the registers for pinctrl, pinconf and gpio mixed up in the same register
range. However, the IO core for the MT7622 SoC is completely distinct from
anyone of previous MediaTek SoCs which already had support, such as
the hardware internal, register address map and register detailed
definition for each pin.

Therefore, instead, the driver is being newly implemented by reusing
generic methods provided from the core layer with GENERIC_PINCONF,
GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS for the sake of code
simplicity and rid of superfluous code. Where the function of pins
determined by groups is utilized in this driver which can help developers
less confused with what combinations of pins effective on the SoC and even
reducing the mistakes during the integration of those relevant boards.

As the gpio_chip handling is also only a few lines, the driver also
implements the gpio functionality directly through GPIOLIB.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-20 08:49:41 +01:00
Sean Wang e3fd24a574 pinctrl: mediatek: cleanup for placing all drivers under the menu
Since lots of MediaTek drivers had been added, it seems slightly better
for that adding cleanup for placing MediaTek pinctrl drivers under the
independent menu as other kinds of drivers usually was done.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-20 08:47:56 +01:00
Ludovic Barre 4ef4cc13ea pinctrl: stm32: Add STM32MP157 MPU support
This driver consists of 2 controllers due to a hole in mapping:
-1 controller for GPIO bankA to K.
-1 controller for GPIO bankZ.

Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-20 08:36:22 +01:00
Florian Fainelli 981ed1bfbc pinctrl: Really force states during suspend/resume
In case a platform only defaults a "default" set of pins, but not a
"sleep" set of pins, and this particular platform suspends and resumes
in a way that the pin states are not preserved by the hardware, when we
resume, we would call pinctrl_single_resume() -> pinctrl_force_default()
-> pinctrl_select_state() and the first thing we do is check that the
pins state is the same as before, and do nothing.

In order to fix this, decouple the actual state change from
pinctrl_select_state() and move it pinctrl_commit_state(), while keeping
the p->state == state check in pinctrl_select_state() not to change the
caller assumptions. pinctrl_force_sleep() and pinctrl_force_default()
are updated to bypass the state check by calling pinctrl_commit_state().

[Linus Walleij]
The forced pin control states are currently only used in some pin
controller drivers that grab their own reference to their own pins.
This is equal to the pin control hogs: pins taken by pin control
devices since there are no corresponding device in the Linux device
hierarchy, such as memory controller lines or unused GPIO lines,
or GPIO lines that are used orthogonally from the GPIO subsystem
but pincontrol-wise managed as hogs (non-strict mode, allowing
simultaneous use by GPIO and pin control). For this case forcing
the state from the drivers' suspend()/resume() callbacks makes
sense and should semantically match the name of the function.

Fixes: 6e5e959dde ("pinctrl: API changes to support multiple states per device")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-20 08:24:13 +01:00