Commit Graph

316 Commits

Author SHA1 Message Date
Linus Torvalds 8bc4d5f394 MTD updates for v4.7:
First cycle with Boris as NAND maintainer! Many (most) bullets stolen from him.
 
 Generic:
 
  * Migrated NAND LED trigger to be a generic MTD trigger
 
 NAND:
 
  * Introduction of the "ECC algorithm" concept, to avoid overloading the ECC
    mode field too much more
  * Replaced the nand_ecclayout infrastructure with something a little more
    flexible (finally!) and future proof
  * Rework of the OMAP GPMC and NAND drivers; the TI folks pulled some of
    this into their own tree as well
  * Prepare the sunxi NAND driver to receive DMA support
  * Handle bitflips in erased pages on GPMI revisions that do not support
    this in hardware.
 
 SPI NOR:
 
  * Start using the spi_flash_read() API for SPI drivers that support it (i.e.,
    SPI drivers with special memory-mapped flash modes)
 
 And other small scattered improvments.
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Merge tag 'for-linus-20160523' of git://git.infradead.org/linux-mtd

Pull MTD updates from Brian Norris:
 "First cycle with Boris as NAND maintainer! Many (most) bullets stolen
  from him.

  Generic:
   - Migrated NAND LED trigger to be a generic MTD trigger

  NAND:
   - Introduction of the "ECC algorithm" concept, to avoid overloading
     the ECC mode field too much more
   - Replaced the nand_ecclayout infrastructure with something a little
     more flexible (finally!) and future proof
   - Rework of the OMAP GPMC and NAND drivers; the TI folks pulled some
     of this into their own tree as well
   - Prepare the sunxi NAND driver to receive DMA support
   - Handle bitflips in erased pages on GPMI revisions that do not
     support this in hardware.

  SPI NOR:
   - Start using the spi_flash_read() API for SPI drivers that support
     it (i.e., SPI drivers with special memory-mapped flash modes)

  And other small scattered improvments"

* tag 'for-linus-20160523' of git://git.infradead.org/linux-mtd: (155 commits)
  mtd: spi-nor: support GigaDevice gd25lq64c
  mtd: nand_bch: fix spelling of "probably"
  mtd: brcmnand: respect ECC algorithm set by NAND subsystem
  gpmi-nand: Handle ECC Errors in erased pages
  Documentation: devicetree: deprecate "soft_bch" nand-ecc-mode value
  mtd: nand: add support for "nand-ecc-algo" DT property
  mtd: mtd: drop NAND_ECC_SOFT_BCH enum value
  mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping
  mtd: nand: read ECC algorithm from the new field
  mtd: nand: fsmc: validate ECC setup by checking algorithm directly
  mtd: nand: set ECC algorithm to Hamming on fallback
  staging: mt29f_spinand: set ECC algorithm explicitly
  CRIS v32: nand: set ECC algorithm explicitly
  mtd: nand: atmel: set ECC algorithm explicitly
  mtd: nand: davinci: set ECC algorithm explicitly
  mtd: nand: bf5xx: set ECC algorithm explicitly
  mtd: nand: omap2: Fix high memory dma prefetch transfer
  mtd: nand: omap2: Start dma request before enabling prefetch
  mtd: nandsim: add __init attribute
  mtd: nand: move of_get_nand_xxx() helpers into nand_base.c
  ...
2016-05-24 11:00:20 -07:00
Brian Norris 5651d6aaf4 mtd: bcm47xxsflash: use ioremap_cache() instead of KSEG0ADDR()
Using KSEG0ADDR makes code highly MIPS dependent and not portable.
Thanks to the fix a68f376 ("MIPS: io.h: Define `ioremap_cache'") we can
use ioremap_cache which is generic and supported on MIPS as well now.

KSEG0ADDR was translating 0x1c000000 into 0x9c000000. With ioremap_cache
we use MIPS's __ioremap (and then remap_area_pages). This results in
different address (e.g. 0xc0080000) but it still should be cached as
expected and it was successfully tested with BCM47186B0.

Other than that drivers/bcma/driver_chipcommon_sflash.c nicely setups a
struct resource for access window, but we wren't using it. Use it now
and drop duplicated info.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
2016-04-04 00:07:57 -07:00
Arnd Bergmann c58d900cc9 bcma: fix building without OF_IRQ
The bcma driver core can be built with or without DT support, but
it fails to build when CONFIG_OF=y and CONFIG_OF_IRQ=n, which
can happen on platforms that do not support IRQ domains.

ERROR: "irq_create_of_mapping" [drivers/bcma/bcma.ko] undefined!
ERROR: "of_irq_parse_raw" [drivers/bcma/bcma.ko] undefined!
ERROR: "of_irq_parse_one" [drivers/bcma/bcma.ko] undefined!

This adds another compile-time check for OF_IRQ, but also
gets rid of now unneeded #ifdef checks: Using the simpler
IS_ENABLED() check for OF_IRQ also covers the case of not
having CONFIG_OF enabled. The check for CONFIG_OF_ADDRESS
was added to allow building on architectures without
OF_ADDRESS, but that has been addressed already in
b1d06b60e9 ("of: Provide static inline function for
of_translate_address if needed").

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-03-23 17:52:10 +02:00
Rafał Miłecki 0ea6f0c582 bcma: move flash detection code to ChipCommon core driver
Flashes are attached and accessible through ChipCommon core, they aren't
connected to MIPS one. Moreover some new ARM devices (e.g. BCM47189) may
have serial flash accessibility using ChipCommon registers as well. To
support them we can't keep this code in MIPS core driver.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-03-07 14:41:08 +02:00
Rafał Miłecki d6a3b51ada bcma: move parallel flash support to separated file
This follows the way of handling other flashes and cleans code a bit. As
next task we will want to move flash code to ChipCommon driver as:
1) Flash controllers are accesible using ChipCommon registers
2) This code isn't MIPS specific
This change prepares bcma for that.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-03-07 14:41:08 +02:00
Rafał Miłecki 2e62f9b2a4 bcma: drop unneeded fields from bcma_pflash struct
Most of info stored in this struct wasn't really used anywhere as we put
all that data in platform data & resource as well.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-03-07 14:41:08 +02:00
David S. Miller 6cd21d7941 Major changes:
wl12xx
 
 * add device tree support for SPI
 
 mwifiex
 
 * add debugfs file to read chip information
 * add MSIx support for newer pcie chipsets (8997 onwards)
 * add schedule scan support
 * add WoWLAN net-detect support
 * firmware dump support for w8997 chipset
 
 iwlwifi
 
 * continue the work on multiple Rx queues
 * add support for beacon storing used in low power states
 * use the regular firmware image of WoWLAN
 * fix 8000 devices for Big Endian machines
 * more firmware debug hooks
 * add support for P2P Client snoozing
 * make the beacon filtering for AP mode configurable
 * fix transmit queues overflow with LSO
 
 libertas
 
 * add support for setting power save via cfg80211
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Merge tag 'wireless-drivers-next-for-davem-2016-02-12' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next

Kalle Valo says:

====================
Major changes:

wl12xx

* add device tree support for SPI

mwifiex

* add debugfs file to read chip information
* add MSIx support for newer pcie chipsets (8997 onwards)
* add schedule scan support
* add WoWLAN net-detect support
* firmware dump support for w8997 chipset

iwlwifi

* continue the work on multiple Rx queues
* add support for beacon storing used in low power states
* use the regular firmware image of WoWLAN
* fix 8000 devices for Big Endian machines
* more firmware debug hooks
* add support for P2P Client snoozing
* make the beacon filtering for AP mode configurable
* fix transmit queues overflow with LSO

libertas

* add support for setting power save via cfg80211
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
2016-02-16 20:38:29 -05:00
Rafał Miłecki 515b399c9a bcma: claim only 14e4:4365 PCI Dell card with SoftMAC BCM43142
It seems 14e4:4365 pattern is too generic as there are two devices:
1) 14e4:4365 1028:0016 with SoftMAC BCM43142 chipset
2) 14e4:4365 14e4:4365 with FullMAC BCM4366 chipset
The later one was found in D-Link DIR-885L router and we want to let
brcmfmac handle it.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-02-06 13:49:17 +02:00
Rafał Miłecki 61dba73cdb bcma: add support for BCM47094
It's another SoC with 32 GPIOs and simplified watchdog handling. It was
tested on D-Link DIR-885L.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-02-06 13:46:59 +02:00
Rafał Miłecki 4c81acab38 bcma: init serial console directly from ChipCommon code
UART is connected to and controlled over ChipCommon core. It doesn't
have much to do with MIPS core (where we initialize it currently)
except just existing on embedded systemms. There isn't point of such
cross-core initialization (and we needed #ifdef anyway) so just handle
it in ChipCommon.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-02-06 13:45:04 +02:00
Rafał Miłecki b3c47afbf5 bcma: support PMU present as separated bus core
On recent Broadcom chipsets PMU is present as separated core and it
can't be accessed using ChipCommon anymore as it fails with e.g.:
[    0.000577] Unhandled fault: external abort on non-linefetch (0x1008) at 0xf1000604

Solve it by using a new (PMU) core pointer set to ChipCommon or PMU
depending on the hardware capabilities.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-02-06 13:36:11 +02:00
Rafał Miłecki 67edf354fa bcma: use _PMU_ in all names of PMU registers
PMU (Power Management Unit) seems to be a separated piece of hardware,
just accessed using ChipCommon core registers. In recent Broadcom
chipsets PMU is not bounded to CC but available as separated core.

To make code cleaner & easier to review (for a correct R/W access) use
clearer names.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-02-06 13:36:11 +02:00
Rafał Miłecki 0c06f5d43e bcma: support chipsets with PMU and GCI cores (devices)
Both cores are another exceptions. They are not accessed in a standard
way and to they don't need or have wrapping addresses.
This fixes bus scanning after finding such core.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-02-06 13:34:51 +02:00
Rafał Miłecki 7267bcda33 bcma: identify bus cores (devices) found on BCM47189
Add missing defines and print proper names.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-02-06 13:34:50 +02:00
Rafał Miłecki 1b3b36b044 bcma: support identifying MX25L25635F serial flash
It's a Macronix 32 MiB flash found on board with BCM47189 SoC.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2016-02-06 13:33:05 +02:00
Linus Torvalds 58cf279aca GPIO bulk updates for the v4.5 kernel cycle:
Infrastructural changes:
 
 - In struct gpio_chip, rename the .dev node to .parent to better reflect
   the fact that this is not the GPIO struct device abstraction. We will
   add that soon so this would be totallt confusing.
 
 - It was noted that the driver .get_value() callbacks was
   sometimes reporting negative -ERR values to the gpiolib core, expecting
   them to be propagated to consumer gpiod_get_value() and gpio_get_value()
   calls. This was not happening, so as there was a mess of drivers
   returning negative errors and some returning "anything else than zero"
   to indicate that a line was active. As some would have bit 31 set to
   indicate "line active" it clashed with negative error codes. This is
   fixed by the largeish series clamping values in all drivers with
   !!value to [0,1] and then augmenting the code to propagate error codes
   to consumers. (Includes some ACKed patches in other subsystems.)
 
 - Add a void *data pointer to struct gpio_chip. The container_of() design
   pattern is indeed very nice, but we want to reform the struct gpio_chip
   to be a non-volative, stateless business, and keep states internal to
   the gpiolib to be able to hold on to the state when adding a proper
   userspace ABI (character device) further down the road. To achieve this,
   drivers need a handle at the internal state that is not dependent on
   their struct gpio_chip() so we add gpiochip_add_data() and
   gpiochip_get_data() following the pattern of many other subsystems.
   All the "use gpiochip data pointer" patches transforms drivers to this
   scheme.
 
 - The Generic GPIO chip header has been merged into the general
   <linux/gpio/driver.h> header, and the custom header for that removed.
   Instead of having a separate mm_gpio_chip struct for these generic
   drivers, merge that into struct gpio_chip, simplifying the code and
   removing the need for separate and confusing includes.
 
 Misc improvements:
 
 - Stabilize the way GPIOs are looked up from the ACPI legacy
   specification.
 
 - Incremental driver features for PXA, PCA953X, Lantiq (patches from the
   OpenWRT community), RCAR, Zynq, PL061, 104-idi-48
 
 New drivers:
 
 - Add a GPIO chip to the ALSA SoC AC97 driver.
 
 - Add a new Broadcom NSP SoC driver (this lands in the pinctrl dir, but
   the branch is merged here too to account for infrastructural changes).
 
 - The sx150x driver now supports the sx1502.
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Merge tag 'gpio-v4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO updates from Linus Walleij:
 "Here is the bulk of GPIO changes for v4.5.

  Notably there are big refactorings mostly by myself, aimed at getting
  the gpio_chip into a shape that makes me believe I can proceed to
  preserve state for a proper userspace ABI (character device) that has
  already been proposed once, but resulted in the feedback that I need
  to go back and restructure stuff.  So I've been restructuring stuff.
  On the way I ran into brokenness (return code from the get_value()
  callback) and had to fix it.  Also, refactored generic GPIO to be
  simpler.

  Some of that is still waiting to trickle down from the subsystems all
  over the kernel that provide random gpio_chips, I've touched every
  single GPIO driver in the kernel now, oh man I didn't know I was
  responsible for so much...

  Apart from that we're churning along as usual.

  I took some effort to test and retest so it should merge nicely and we
  shook out a couple of bugs in -next.

  Infrastructural changes:

   - In struct gpio_chip, rename the .dev node to .parent to better
     reflect the fact that this is not the GPIO struct device
     abstraction.  We will add that soon so this would be totallt
     confusing.

   - It was noted that the driver .get_value() callbacks was sometimes
     reporting negative -ERR values to the gpiolib core, expecting them
     to be propagated to consumer gpiod_get_value() and gpio_get_value()
     calls.  This was not happening, so as there was a mess of drivers
     returning negative errors and some returning "anything else than
     zero" to indicate that a line was active.  As some would have bit
     31 set to indicate "line active" it clashed with negative error
     codes.  This is fixed by the largeish series clamping values in all
     drivers with !!value to [0,1] and then augmenting the code to
     propagate error codes to consumers.  (Includes some ACKed patches
     in other subsystems.)

   - Add a void *data pointer to struct gpio_chip.  The container_of()
     design pattern is indeed very nice, but we want to reform the
     struct gpio_chip to be a non-volative, stateless business, and keep
     states internal to the gpiolib to be able to hold on to the state
     when adding a proper userspace ABI (character device) further down
     the road.  To achieve this, drivers need a handle at the internal
     state that is not dependent on their struct gpio_chip() so we add
     gpiochip_add_data() and gpiochip_get_data() following the pattern
     of many other subsystems.  All the "use gpiochip data pointer"
     patches transforms drivers to this scheme.

   - The Generic GPIO chip header has been merged into the general
     <linux/gpio/driver.h> header, and the custom header for that
     removed.  Instead of having a separate mm_gpio_chip struct for
     these generic drivers, merge that into struct gpio_chip,
     simplifying the code and removing the need for separate and
     confusing includes.

  Misc improvements:

   - Stabilize the way GPIOs are looked up from the ACPI legacy
     specification.

   - Incremental driver features for PXA, PCA953X, Lantiq (patches from
     the OpenWRT community), RCAR, Zynq, PL061, 104-idi-48

  New drivers:

   - Add a GPIO chip to the ALSA SoC AC97 driver.

   - Add a new Broadcom NSP SoC driver (this lands in the pinctrl dir,
     but the branch is merged here too to account for infrastructural
     changes).

   - The sx150x driver now supports the sx1502"

* tag 'gpio-v4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (220 commits)
  gpio: generic: make bgpio_pdata always visible
  gpiolib: fix chip order in gpio list
  gpio: mpc8xxx: Do not use gpiochip_get_data() in mpc8xxx_gpio_save_regs()
  gpio: mm-lantiq: Do not use gpiochip_get_data() in ltq_mm_save_regs()
  gpio: brcmstb: Allow building driver for BMIPS_GENERIC
  gpio: brcmstb: Set endian flags for big-endian MIPS
  gpio: moxart: fix build regression
  gpio: xilinx: Do not use gpiochip_get_data() in xgpio_save_regs()
  leds: pca9532: use gpiochip data pointer
  leds: tca6507: use gpiochip data pointer
  hid: cp2112: use gpiochip data pointer
  bcma: gpio: use gpiochip data pointer
  avr32: gpio: use gpiochip data pointer
  video: fbdev: via: use gpiochip data pointer
  gpio: pch: Optimize pch_gpio_get()
  Revert "pinctrl: lantiq: Implement gpio_chip.to_irq"
  pinctrl: nsp-gpio: use gpiochip data pointer
  pinctrl: vt8500-wmt: use gpiochip data pointer
  pinctrl: exynos5440: use gpiochip data pointer
  pinctrl: at91-pio4: use gpiochip data pointer
  ...
2016-01-17 12:32:01 -08:00
Linus Walleij 78d455a2e4 bcma: gpio: use gpiochip data pointer
This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().

Cc: Kalle Valo <kvalo@codeaurora.org>
Cc: linux-wireless@vger.kernel.org
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-07 00:08:36 +01:00
Rafał Miłecki 0510931ef5 bcma: use module_init for the main part of bus initialization
So far we were using fs_initcall. It was (and still is) needed because
struct bus_type has to be registered early. However main bus
initialization has to happen later as it requires SPROM which depends on
NVRAM which depends on mtd.
Solve it by using fs_initcall only for bus_register call and module_init
for the rest. It affects bcma only when built-in obviously.

This was tested with BCM4706 and BCM5357C0 (BCM47XX), BCM4708A0
(ARCH_BCM_5301X) and BCM43225 (PCIe card with bcma as module).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-12-31 10:17:05 +02:00
Linus Walleij 58383c7842 gpio: change member .dev to .parent
The name .dev in a struct is normally reserved for a struct device
that is let us say a superclass to the thing described by the struct.
struct gpio_chip stands out by confusingly using a struct device *dev
to point to the parent device (such as a platform_device) that
represents the hardware. As we want to give gpio_chip:s real devices,
this is not working. We need to rename this member to parent.

This was done by two coccinelle scripts, I guess it is possible to
combine them into one, but I don't know such stuff. They look like
this:

@@
struct gpio_chip *var;
@@
-var->dev
+var->parent

and:

@@
struct gpio_chip var;
@@
-var.dev
+var.parent

and:

@@
struct bgpio_chip *var;
@@
-var->gc.dev
+var->gc.parent

Plus a few instances of bgpio that I couldn't figure out how
to teach Coccinelle to rewrite.

This patch hits all over the place, but I *strongly* prefer this
solution to any piecemal approaches that just exercise patch
mechanics all over the place. It mainly hits drivers/gpio and
drivers/pinctrl which is my own backyard anyway.

Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: Alek Du <alek.du@intel.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Jiri Kosina <jkosina@suse.cz>
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-11-19 09:24:35 +01:00
Hauke Mehrtens 69b5f4da26 bcma: add support for population subnodes also when build as module
of_default_bus_match_table was not exported earlier, so it could only
be accessed by code compiled into the kernel. A new function
of_platform_default_populate() was added which uses
of_default_bus_match_table and this function is also exported. This way
it is possible to create a bus with the content of
of_default_bus_match_table and we can remove the hacks from bcma.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-09-29 10:59:27 +03:00
Linus Walleij 74f4e0cc61 bcma: switch GPIO portions to use GPIOLIB_IRQCHIP
This switches the BCMA GPIO driver to use GPIOLIB_IRQCHIP to
handle its interrupts instead of rolling its own copy of the
irqdomain handling etc.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-08-18 09:08:47 +03:00
Hauke Mehrtens 53cd2fdb00 bcma: fix access to host_pdev for PCIe devices
bus->host_pdev is part of a union so bus->host_pdev != NULL is probably
also true for PCIe devices, because there it accesses bus->host_pci. If
we access the dev member at the offset defined in struct
platform_device in struct pci_dev instead we probably get something
else.

This patch adds a new function which returns the host dev struct and
NULL if we do not have a host dev. When this gets registered on MIPS
brcm47xx we do not have a host dev in some situations.
This function could also be used in other places.

This problem was introduced in this commit:
commit cae761b5a6
Author: Rafa? Mi?ecki <zajec5@gmail.com>
Date:   Sun Jun 28 17:17:13 2015 +0200

    bcma: populate bus DT subnodes as platform_device-s

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-08-10 22:20:46 +03:00
Hauke Mehrtens 92ff7a698b bcma: fix build error when build as module
Currently of_default_bus_match_table is not exported so we can only use
this feature when bcma is build into the kernel. This patch removes
support for child buses when bcma is build as a module as a temporary
fix for a build problem introduces in this commit:

commit cae761b5a6
Author: Rafał Miłecki <zajec5@gmail.com>
Date:   Sun Jun 28 17:17:13 2015 +0200

    bcma: populate bus DT subnodes as platform_device-s

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Fixes: cae761b5a6 ("bcma: populate bus DT subnodes as platform_device-s")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-07-26 14:53:37 +03:00
Rafał Miłecki cae761b5a6 bcma: populate bus DT subnodes as platform_device-s
Our bus should allow defining children nodes as we may want to specify
devices attached to the bus. This is required e.g. to specify NAND or
ChipCommon cores and use bus's address and IRQ mappings.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-07-21 17:06:06 +03:00
Rafał Miłecki 49280625eb bcma: lower dependency of BCMA_DRIVER_PCI_HOSTMODE
This extension of BCMA_DRIVER_PCI has no reason to depend on
BCMA_HOST_PCI. User may just want to have PCI device attached to SoC
registered without enabling any extra client mode code.
This can be useful when having non-bcma PCI device attached or when
using other PCI driver.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-06-08 14:33:26 +03:00
Felix Fietkau f022ea52d9 bcma: enable 32 GPIO pins for BCM4707
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-05-09 16:28:07 +03:00
Felix Fietkau 2d57b7126d bcma: use absolute base for SoC GPIO pins
On some BCM5301x ARM devices, user space still needs to control some
system GPIO pins for which no driver exists. This is a lot easier to do
with a predictable GPIO base.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-05-09 16:28:06 +03:00
Linus Torvalds bfaf245022 Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for MIPS for Linux 4.1.  Most
  noteworthy:

   - Add more Octeon-optimized crypto functions
   - Octeon crypto preemption and locking fixes
   - Little endian support for Octeon
   - Use correct CSR to soft reset Octeons
   - Support LEDs on the Octeon-based DSR-1000N
   - Fix PCI interrupt mapping for the Octeon-based DSR-1000N
   - Mark prom_free_prom_memory() as __init for a number of systems
   - Support for Imagination's Pistachio SOC.  This includes arch and
     CLK bits.  I'd like to merge pinctrl bits later
   - Improve parallelism of csum_partial for certain pipelines
   - Organize DTB files in subdirs like other architectures
   - Implement read_sched_clock for all MIPS platforms other than
     Octeon
   - Massive series of 38 fixes and cleanups for the FPU emulator /
     kernel
   - Further FPU remulator work to support new features.  This sits on a
     separate branch which also has been pulled into the 4.1 KVM branch
   - Clean up and fixes for the SEAD3 eval board; remove unused file
   - Various updates for Netlogic platforms
   - A number of small updates for Loongson 3 platforms
   - Increase the memory limit for ATH79 platforms to 256MB
   - A fair number of fixes and updates for BCM47xx platforms
   - Finish the implementation of XPA support
   - MIPS FDC support.  No, not floppy controller but Fast Debug Channel :)
   - Detect the R16000 used in SGI legacy platforms
   - Fix Kconfig dependencies for the SSB bus support"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits)
  MIPS: Makefile: Fix MIPS ASE detection code
  MIPS: asm: elf: Set O32 default FPU flags
  MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
  MIPS: Kconfig: Disable SMP/CPS for 64-bit
  MIPS: Hibernate: flush TLB entries earlier
  MIPS: smp-cps: cpu_set FPU mask if FPU present
  MIPS: lose_fpu(): Disable FPU when MSA enabled
  MIPS: ralink: add missing symbol for RALINK_ILL_ACC
  MIPS: ralink: Fix bad config symbol in PCI makefile.
  SSB: fix Kconfig dependencies
  MIPS: Malta: Detect and fix bad memsize values
  Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
  MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
  MIPS: Fix cpu_has_mips_r2_exec_hazard.
  MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
  MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
  MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
  MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
  MIPS: unaligned: Fix regular load/store instruction emulation for EVA
  MIPS: unaligned: Surround load/store macros in do {} while statements
  ...
2015-04-17 15:50:54 -04:00
Rafał Miłecki 138173d4e8 MIPS: BCM47xx: Move NVRAM header to the include/linux/.
There are two reasons for having this header in the common place:
1) Simplifying drivers that read NVRAM entries. We will be able to
   safely call bcm47xx_nvram_* functions without #ifdef-s.
2) Getting NVRAM driver out of MIPS arch code. This is needed to support
   BCM5301X arch which also requires this NVRAM driver. Patch for that
   will follow once we get is reviewed.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: linux-soc@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8619/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-01 17:22:00 +02:00
Rafał Miłecki 057fcd426e bcma: gpio: use predictable base for all BCM47XX buses
Some BCM47XX SoC routers have LEDs connected to extra PCIe bcma buses.
Handling them in arch code requires predictable GPIO numbers.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-20 09:08:56 +02:00
Rafał Miłecki 6029e0c59b Revert "bcma: Kconfig: Let it depend on PCI"
This reverts commit b09f5ec18b.

Now that we have fully working BCMA_DRIVER_PCI symbol (in can be safely
disabled), there is no risk bcma will try to use PCI code without PCI
available.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-13 16:25:54 +02:00
Rafał Miłecki 982a40f5c0 bcma: allow disabling (not building) PCI driver
It isn't required for bcma bus on SoCs, so provide some empty functions
and allow disabling it.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-13 16:25:50 +02:00
Rafał Miłecki 702131e2a3 bcma: move PCI IRQ control function to host specific code
This function isn't really related to any bus core. It touches PCI
device config registers only, so move it to the (PCI) host file.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-13 16:25:50 +02:00
Rafał Miłecki 1ca2760fb2 bcma: prepare Kconfig symbol for PCI driver
Driver for PCIe core requires PCI to be enabled, however we shouldn't
require it for the whole bus. Someone may be not interested in extra
PCI devices and what's more there are SoCs without any PCI at all (like
BCM5356C0, BCM5357*, BCM47186B0). For more details see Kconfig "help".
Please note this patch doesn't allow disabling PCI drivers yet, as it
requires more work on calls to bcma_core_pci_* functions.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-05 14:11:45 +02:00
Rafał Miłecki 0a4e699a41 bcma: move internal function declarations to private header
These functions are not exported nor used anywhere, so there is no
reason to put them in public headers.
Also drop unused bcma_chipco_(suspend|resume).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-05 14:11:43 +02:00
Chen Gang b09f5ec18b bcma: Kconfig: Let it depend on PCI
bcma also needs PCI, just like IOMEM and DMA, so let it depend on PCI,
or will cause building break for allmodconfig under c6x:

    CC [M]  drivers/bcma/driver_pcie2.o
  drivers/bcma/driver_pcie2.c: In function 'bcma_core_pcie2_up':
  drivers/bcma/driver_pcie2.c:196:8: error: implicit declaration of function 'pcie_set_readrq' [-Werror=implicit-function-declaration]
    err = pcie_set_readrq(dev, pcie2->reqsize);
          ^

Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-05 13:56:59 +02:00
Rafał Miłecki 0cbfc065fe bcma: gpio: enable GPIO IRQ domain on BCM5301X
Just like on BCM47XX arch, BCM5301X also has ChipCommon with IRQ for
GPIOs. Now we have interrupts working on BCM5301X we can finally make
use of it. This has been successfully tested on 5 different devices
(Buffalo, Luxul, Netgear).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-03 15:56:07 +02:00
Rafał Miłecki 2264fc857d bcma: add missing includes
kbuild found out that commit 804e27dee4 ("bcma: support bringing up
bus hosted on PCIe Gen 2") broke the build on m68k:

   drivers/bcma/driver_pcie2.c: In function 'bcma_core_pcie2_up':
>> drivers/bcma/driver_pcie2.c:196:2: error: implicit declaration of function 'pcie_set_readrq' [-Werror\
=implicit-function-declaration]
     err = pcie_set_readrq(dev, pcie2->reqsize);
     ^
   cc1: some warnings being treated as errors

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-03 15:26:38 +02:00
Rafał Miłecki 9b6cc9a807 bcma: enable support for PCIe Gen 2 host devices
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-02 16:59:45 +02:00
Rafał Miłecki 804e27dee4 bcma: support bringing up bus hosted on PCIe Gen 2
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-02 16:59:45 +02:00
Rafał Miłecki 5b6ff664c8 bcma: change IRQ control function to accept bus as an argument
It doesn't operate on PCI core, but PCI host device, so there is no
point of passing core related struct.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-02 16:59:45 +02:00
Rafał Miłecki 4186721d02 bcma: add helpers bringing PCIe hosted bus up / down
Bringing PCIe hosted bus up requires operating on host-related core.
Since we plan to support PCIe Gen 2 devices we should provide a helper
picking the correct one (PCIE or PCIE2).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-03-02 16:59:45 +02:00
Rafał Miłecki 8be08a39d4 bcma: implement host code support for PCIe Gen 2 devices
This is stil incomplete, so we don't add PCI IDs of new devices yet.
Purpose of this patch is to allow testing & adjusting rest of the code.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29 10:54:43 +02:00
Rafał Miłecki b504075f59 bcma: add early_init function for PCIe core and move some fix into it
There are some PCIe core fixes that need to be applied before accessing
SPROM, otherwise reading it may fail.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29 10:53:08 +02:00
Rafał Miłecki ae8ce289e5 bcma: add empty PCIe hostmode functions if support is disabled
This allows us to drop some #ifdef magic (mess).

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29 10:52:59 +02:00
Rafał Miłecki 3c31316135 bcma: detect SPROM revision 11
Extracting values from it is still unsupported, but at least we'll
display some meaningful error now.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29 10:49:28 +02:00
Rafał Miłecki 17fbaa6e42 bcma: simplify freeing cores (internal devices structs)
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29 10:49:28 +02:00
Rafał Miłecki 68fcd24503 bcma: fix watchdog on some ARM chipsets
These chipsets don't need changing clock mode.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-29 10:44:44 +02:00
Rafał Miłecki c5ed1df781 bcma: use standard bus scanning during early register
Starting with kernel 3.19-rc1 early registration of bcma on MIPS is done
a bit later, with memory allocator available. This allows us to simplify
code by using standard bus scanning method.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-23 21:47:55 +02:00
Rafał Miłecki 799038ea9b bcma: clean bus initialization code
This moves main bus init code to the main.c and renames old function to
make its purpose clear.
Thanks to this change we'll also be able to separate scanning from
registration (and support PCIe Gen 2 devices) in the future.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2015-01-23 19:44:58 +02:00